A DESIGN METHODOLOGY FOR CONTROL SYSTEMS
USING SYMBOLIC ARRAYS
by
Gary Dale Sullivan
B.S., University of New Orleans, 1984
A thesis submitted to the
University of Colorado at Denver
in partial fufillment
of the requirements for the degree of
Master of Science
Electrical Engineering
1999
1999 by Gary Dale Sullivan
All rights reserved.
This thesis for the Master of Science
degree by
Gary Dale Sullivan
has been approved
Jan T. Bialasiewicz
Miloje S. Radenkovic
Tom Altman
Date
Sullivan, Gary Dale (M.S., Electrical Engineering)
A design methodology for control systems using symbolic arrays
Thesis directed by Professor Jan T. Bialasiewicz
ABSTRACT
This thesis presents a methodology and associated symbolic
notation that provides for design of feedback control systems that operate
by using sets of symbolic arrays. By using symbolic arrays and the
mapping relationships between them, it is intended to replace boolean
logic and mathematical operations as the basic "modules" used for system
control.
A control system generated by this methodology emulates a
lookup table in operation, but capable of faster operation and of modifying
its behavior during operation. Presented in this thesis will be; methodology
of the symbolic notation, creation of a feedback control system based on
this notation and simulation/analysis of the resultant modeled control
system.
"MATHCAD" a math and text based software was used in the
creation of this thesis. Ail equations and simulations presented are
interactive with this text and are thus shown.
This abstract accurately represents the content of the candidate's thesis,
recommend its publication.
Signed
Jan T. Bialasiewicz
iv
DEDICATION
I dedicate this thesis to Joyce, my wife. It was her support, comfort and
cookies, which allowed this thesis and school to be completed.
CONTENTS
Figures..........................................................ix
Chapter
1. Introduction.............................................1
1.1 Control System Granularity...............................1
1.2 A Description of the Symbolic Control System.............1
1.3 A Description of this thesis.............................2
1.4 Restraints on System modeling............................2
2. Set S and the Symbolic Control System....................3
2.1 Set S....................................................3
2.2 Cardinality of the Set S.................................3
2.3 Process Signals and the Set S............................3
2.4 Set S and A/D, D/A Converters............................4
2.5 Set S and Arrays.........................................4
2.6 Set S and Symbol Generation..............................4
3. Mapping Notation.........................................5
3.1 General Notation.........................................5
3.2 Cell Pairs...............................................5
vi
3.3 Mapping of Arrays.......................................5
3.4 Mapping of A/D and D/A Converters.......................6
3.5 Array Operations........................................7
4. Operator Based Calibration.............................12
4.1 Process Signals and the Symbolic Control System........12
4.2 Time Resolution........................................12
4.3 Signal Strength Resolution.............................13
5. Methodology............................................14
5.1 Process and Control System Description.................14
5.2 Matrix M...............................................15
5.3 Time and the "elk" Array...............................16
5.4 Generation of the I/O Arrays...........................17
5.5 Generation of the Process Arrays.......................18
5.6 Generation of the Process Mapping......................20
5.7 Generation of the Mapping Matrix "Ma"..................22
5.8 Generation of the Mapping Matrix "Mb"..................26
5.9 Generation of the Mapping Arrays Couta and Coutb.......27
5.10 Generation of the Mapping Matrix "C"...................28
5.11 Final Mapping Relationships............................29
6. Control System Design and Modeling.....................31
6.1 Modeled Process and Input..............................31
6.2 Calibrating Input and Output Signals...................35
6.3 Generating the Mapping Arrays..........................38
vii
6.4 Final Control System....................................47
7. Analysis of Methodology................................50
7.1 Behavior due to Control System Granularity.............50
7.2 Resultant System Size..................................50
7.3 Methods for Improvement of Operation...................51
7.4 Conclusion.............................................52
bibliography....................................................53
viii
FIGURES
Figure
3-1 Functions A(t) and B(t)....................................8
3-2 Arrays Adk and Bdk.........................................9
3-3 Paths ABdk and BAdk.......................................10
3-4 Map AA and Map BB.........................................11
5-1 Process...................................................14
5- 2 Control System and Process................................14
6- 1 Illustration of Process Response..........................32
6-2 Input Test Signals fR(t) and fF(t)........................33
6-3 Output Test Signals Or(t) and Of(t)......................35
6-4 Arrays IRdk and IFdk.....................................36
6-5 Arrays ORdk and OFdk......................................37
6-6 Arrays Mldk and MOdk......................................38
6-7 Array IOdk................................................39
6-8A Ma, shifted by 64.........................................41
6-8B Ma, shifted by 192........................................42
6-9 Matrix Ma.................................................43
IX
6-10 Matrix C...................................................46
6-11 Control System; f(t) = fR(t), fF(t)......................48
6-12 Control System; f(t) = 1/2, f(t) = 0, f(t) = -1/2........48
6-13 Control System; f(t) = sin(t/70).........................49
1.
Introduction
1.1 Control System Granularity
Control systems are information based systems. They operate by
receiving information about a process and modifying this information via
control outputs. For digital control systems the process information,
composed of analog signals, are translated into/from strings of 1's and 0's.
This is done via analog to digital converters (A/D) and digital to analog
converters (D/A). These binary strings are of some fixed arbitrary length "L".
A binary string of length "L" provides a maximum of 2>- possible numerical
values that can be assigned to an analog signal.
A limited string length "L" implies that no matter how precise the
solution to a process transfer function, the input and output signals must still
be translated into one of a fixed number of numerical values based on the
length of the binary string. Such granularity is usually considered a
unavoidable restriction. For this methodology, it is the starting point as the
symbolic array sets are based on the granularity of a given control system.
1.2 A Description of the Symbolic
Control System
Input and output signal values for a process are represented in a
digital control system as finite length binary strings. This methodology views
these strings not as possible numerical values but as part of a unique
symbol set S of cardinality of 2>-+ C. Where "L" is the length of the binary
strings in the control system and "C" the number of converters and arrays
used.
An 8-bit A/D is then seen as generating one out of a possible 256
(28) symbols to represent a unique signal value. This "mapping" of a symbol
to a unique signal value results from the granularity of the control system. If
the binary strings had no fixed length, then the symbol set S would have to
include the unique values (as a function of the length of each binary string)
for all signals. This would result in set S having the size;
l
\ n= 1 /
+ c
Where "n" is a binary string of length "Ln" and "C"
is the number of converters and arrays used.
Without the granularity of fixed sized converters and thus a fixed length for a
binary strings, this methodology would become too unwieldy to be of use.
1.3 A Description of this Thesis
The purpose of this thesis is to evolve a methodology for designing
control systems whose functionality does not require numerical or Boolean
operations. These symbolic control systems instead would operate on a
more basic, mechanical/cellular, level. While not explored in this thesis, such
systems would appear to have the ability to "evolve" as mapping operations
can easily cross link to different symbolic systems.
1.4 Restraints on system modeling
Mathcad uses arrays based on sequential numbering of individual
elements. Due to this limitation and to satisfy the need to easily generate a
large symbol set, the set S will be composed of a sequential set of numbers
representing unique signal values and letters to represent arrays. Due to
time constraints on running simulations, 8-bit A/D and D/A's will be assumed
for all examples used. This results in "L" having the cardinality of 256. See
Chapter 2 for the precise definition of the set S.
"Custom built", this symbolic control system would consist of arrays
connected to each other via bundles of 256 wires, each representing a
symbol. Control system operation is accomplished by having the arrays shift-
symbols from bundle to bundle. This is done by selecting one of the 256
wires in a bundle.
2
2.
Set S and the Symbolic Control System
2.1 Sets
This methodology for design of symbolic control systems consist
of mapping symbols through a set of arrays. Initial symbols being
generated via A/D converters and resultant output symbols generating a
control signal via a D/A converter. The physical structure of the mapping
operation is then based on the set S and how it is represented in the
control system. As Mathcad will be the software used in system modeling,
the following is a result of both the physical control system and Mathcad
requirements.
2.2 Cardinality of the set S
The cardinality of the sets is given by the formula 2>- + C. "L" is
the length of the binary strings used in the control system and is based on
the resolution of the control systems' A/D and D/A converters. For the
purpose of this thesis L = 8. "C" is the number of converters and arrays
used in the control system. For the sample system used, C=12. The total
number of symbols in the set S is then given by; 28 + 12 = 268.
The cardinality of the set S is then: 268
2.3 Process Signals and the Set S
Process signals used in this thesis shall have a maximum
resolution of 256 possible signal values. Each of these unique signal
values to be matched to only one symbol from the set S. Matching of a
maximum of 256 unique process signal values to the subset "L" of the set
S is an Operator based calibration covered in chapter four.
3
2.4
Set S and A/D, D/A Converters
The control system shall use 8-bit converters, where each
converter used in the control system shall be assigned a unique symbol
from the subset "C" of the set S. Each of the 256 possible binary strings
generated or inputted to a converter to be matched to only one symbol from
the subset "L" of the set S.
2.5 Set S and Arrays
Each array used in the control system shall be assigned a unique
symbol from the subset "C" of the set S. An array shall consist of 256
matched pairs of cells. Each cell shall contain one symbol from the subset
"L" of the sets.
2.6 Set S and Symbol Generation
In order to simplify the array operations used in this thesis, the
symbols of set S shall have the following properties:
a. The 256 symbols representing a 8-bit binary string in a converter
shall consist of the numbers 1 through 256 in ascending order.
b. The least significant bit of all A/D and D/A converters shall be
assigned the number 1. The most significant bit shall be
assigned the number 128.
c. The 12 symbols denoting converters and arrays shall consist of
the following; InStatus, OutStatus, Cout, IF, OF, IR, OR, Ml,
MO, IO, Ma, Mb, C and elk. They will be defined as used.
4
3.
Mapping Notation
3.1 General Notation
Converters and arrays use identical notation and mapping
operations. Any reference to array notation also applies to converters. The
difference between the two is that one cell in each converter cell pair is
physically mapped to a process signal. In arrays, both cells in a cell pair are
mapped to other arrays or converters. Mapping between arrays is read
from the bottom up."" denotes a mapping relationship between arrays.
3.2 Cell Pairs
Converters and arrays both use blocks of 256 cell pairs. Each cell
pair is matched to a unique symbol from the subset "L". Mapping through
each pair is bidirectional and is determined during design.
Examples of cell pairs:
array / celll \ array_name(celll) celll
name ^ Cell2/ ce!12 array_name(ce!12)
Identifying this block of 256 cell pairs is the "array name",
consisting of a unique symbol from the subset "C". Each cell is identified by
the symbol it contains. This can be done as a cell pair is a physical
matching determined by design and during mapping of the process itself.
3.3 Mapping of Arrays
Mapping through an array (converter) is accomplished by
referencing, via symbol matching, a cell in an array. This cell is matched to
the second cell in the cell pair. The symbol contained in the second cell is
the mapped output. The following examples illustrate different mapping
operations.
5
a.
Symbol correlation between two arrays:
b.
c.
$ is equivalent to:
Mapping between two arrays:
12(B)
C
$ is equivalent to:
11(C)
A
Mapping between two arrays:
12(B)
C
is equivalent to:
c
11(A)
c
B
12(B)
A
12(B)
11(A)
3.4 Mapping of A/D and D/A Converters
Converters, as defined in this thesis (2.4), consist of 256 cell pairs.
In a cell pair, one cell contains the binary string corresponding to one of the
256 possible signal values "seen" by the converter. The second cell of the
pair is to contain a symbol from the subset "L" of the set S. Each unique
signal value shall be matched to only one symbol from the subset "L". The
following examples-illustrate different mapping operations.
6
a.
Signal/Symbol correlation in a converter:
Process input: Outstatus-
status_signal
Process
Output: output-
b. Mapping between converter and array:
12(B)
c
is equivalent to:
InStatus(C)
input_signal
12(B)
input_signal
3.5 Array Operations
A primary mapping operation performed by the control system
involves splitting and merging arrays. In the symbolic notation this can be
expressed as:
a. Splitting an array:
Split, with a
Original Array: common axis: Resultant Arrays:
7
\
b.
Merging two arrays:
Aligning along a Merged Array:
Original Arrays: common axis:
c
B
c. The following is an example of mapping two independent functions
together, illustrating the techniques to be used in this thesis.
c.1 Let there be two functions A(t) and B(t):
t :=0,2..300
A(t) :=250-((l e 66)) B(t) :=250-e 73
Plotted as a function of time; fiqure 3-1:
Figure 3-1:
8
c.2
Generating the arrays A and B from the functions: elk := 1,2..256
Array A:
Array B:
A : =
s< 0
for clke 1,2..256
IA <- ceil
elk
250-11 -e
elk
66
B : =
s< 0
for clke 1,2..256
/ _dk
BcIk<-ceil\250-e 73
B
|B
Note: Generation of arrays in this manner are used in this
thesis to emulate A/D and D/A digital converters, "ceil"
is a built in function that rounds up to the nearest
integer, this is required to generate arrays.Plotted as
a function of the elk array; figure 3-2:
Figure 3-2:
Where:
_A_
clk is the array representing: A(t) and
is the array representing: B(t)
elk
9
c.3 Mapping through the two array paths:
AB:
^A_
elk
elk
and:
BA:
B_
elk
A_
elk
Mapping through B to A:
AB :=
s<-0
for elke 1,2..256
AB
AB
Mapping through A to B:
BA : =
s<-0
for elke 1,2..256
BAc.k^BA
elk
BA
BA
This double pathway method of mapping is required as the
control system cannot distinguish the relative magnitude of two
functions. The resultant mapping of the two paths between A and
B are shown in figure 3-3.
Figure 3-3:
10
c.4
Mapping these two paths to each other:
mapAA :=
s-0
map^i
for clke 1,2..256
I mapAABAcik< ABclk
| mapAA
mapAA
mapBB : =
map256^ 1
for clke 1,2..256
mapBBABcik-BAcik
mapBB
mapBB
The results are shown in figure 3-4:
Figure 3-4:
This plot shows the "translation" a symbol generated by a function
(A or B) goes through; this operation is determined by the relative
values of the two functions at the point represented by the
symbol. If the two functions (A and B) were identical, this plot
would show a one to one symbol match between the two axis.
The straight lines of the mappings shown on the plot represent
rounding errors. These are due to the need to go from floating
point operations (A(t) and B(t)) to integer operations Adk and
BClk-
11
4.
Operator Based Calibration
4.1 Process Signals and the Symbolic
Control System
The symbolic control system begins operation by generating a set
of four arrays (IR, IF, OR, OF) that map the changes in process input and
output signals over time. System operation is then based on mapping to
these arrays as a function of current process values. Operator based
calibration consist of externally setting the Time and Signal Strength
resolutions to obtain optimal generation of these arrays.
Optimal generation of the arrays (IR, IF, OR, OF) is defined as
addressing the following control system restrictions:
a. The symbolic control system based on this methodology does not
have the capacity for Boolean operations. The ability to detect
unused cells and then externally assign symbols to them does not
exist.
b. Mapping operations are based on cycling through all 256 cell
pairs of an array. Due to (4.1 .a) the symbols in a cell pair must
have at least one match during the mapping between
arrays/converters.
c. Operator based calibration shall then consist of adjusting the
Time and Signal Strength resolutions so that the arrays IR, IF, OR
and OF satisfy (4.1.b).
4.2 Time Resolution
The symbolic control system based on this methodology does not
have the capacity for numerical operations. The ability to directly calculate
time based functions does not exist. Chapter (5.) deals with this problem by
generation of a "elk" array which sequentially cycles through the set of
symbols in the subset "L". The time required to cycle from one symbol to the
next in the "elk" array is defined as the Time resolution.
12
a. Calibration of the Time resolution is based on the total time
required to cycle through the 256 symbols of subset "L". This
length of time must equal the approximate settling time of the
process.
Time resolution is then given as 1/256 'th of this settling time.
4.3 Signal Strength Resolution
Due to the requirement of (4.1 .b), the calibration of the process
signals into/from the converters must ensure that the range of signal values
exceeds that of the converters. All converter cell pairs are then ensured of
being filled and providing a match during mapping operations.
As the control system resolution is restricted to 256 possible
symbols, calibration of the signal range to equal that of the converters
provides for optimal control system operation.
13
5.
Methodology
5.1 Process and Control system description
Let there be a process with input and output as shown in
figure 5-1.
Figure 5-1:
output
This design methodology shall generate a control system that
modifies the process in the following manner:
a. The control system shall intercept the process input and substitute
another signal (Cout) such that the output tracks the original
process input. To perform this operation, the control system shall
use two inputs and one output as shown in figure 5-2.
input
Figure 5-2:
Where "Instatus" and "Outstatus" are A/D converters and "Cout" is
a D/A converter. This system could be thought of as intercepting an
Operator setpoint and substituting another signal to achieve the
desired process input/output tracking.
14
b. The converters "InStatus", "OutStatus" and "Cout" are represented
symbolically as the arrays:
I InStatus \ / OutStatus \ (controi_output_to_process \
\input_signal_status/ \output_signal_status/ \ Cout /
5.2 Matrix M
Let there be a multidimensional matrix M. It shall have the
property such that past and present symbol assignments to Cout and
OutStatus maps a cell location in M. This cell location (elk) is to contain the
symbol that maps to the substitute signal sent to the process. From (5.1.a)
this signal shall be such that the process output tracks the original process
input. Symbolically, let the control system and matrix M be represented by:
@ time "t+1"
control_output_to_process
Cout
Cout
Couta Coutb
} matrix C
o
Ma {
Couta
InStatus OutStatus/
} matrix M {
I Coutb
\OutStatus_Cout
} Mb
0)
InStatus
input_signal_status
@ time "t"
OutStatus
output_signaI_status
@ time "t"
InStatus \
elkb /
time "t-T
I OutStatus
elkb
time "t'
15
The size of matrix M can be approximated by:
"g" is the graininess or converter resolution.
l(g)NJ N" is the number of system inputs/outputs.
"s" is the set of past and present integer values
For this system: N:=3 g =256 s:=2
matrix size :
[(*>T
matrix size = 2.815-1014
A matrix of this size is not very useful and a primary goal of this
methodology is to emulate the operation of the matrix M, not its
bulkiness.
a. One primary reason for the size of the matrix M results from
requiring a mapping for every combination of input/output symbols
For a system of three converters (two A/D, one D/A) of 256 bit
resolution, this mapping results in a submatrix "crystal" of size:
2563 = 1.678-107
Despite the large size of this submatrix, there are still only 256
possible symbols that can be assigned to the roughly 16 million
cells available.
5.3 Time and the "elk" array
The symbolic control system based on this methodology does not
have the capacity to perform Boolean or numerical operations. Time based
systems using mathematical manipulation of clock outputs are not possible.
A "elk" array was developed in chapter four that used the operator entered
settling time to sequence a fixed set of symbols consisting of the subset "L"
This symbol sequencing time is the Time Resolution (seconds). For "L"
equal to 256, (Time Resolution X 256) = process settling time.
16
Process arrays (5.5) are used to map process signals and time
together through "elk" based arrays. The control system then views time as a
point where different array mappings are matched together. This point is
represented by a "elk" symbol.
Let "elk" represent a future generated symbol, "elka" a presently
generated symbol and "elkb" a elk array symbol generated in the past.
5.4 Generation of the I/O Arrays
I/O arrays map signals into/out of the control system, these arrays
relate the process signals to sets of symbols. Process arrays map these
symbol sets to each other based on the process response.
a. I/O arrays "InStatus", "OutStatus" and "Cout" are represented
symbolically as:
I InStatus \ I OutStatus \ /control_output_to_process\
\input_signal_status/ \output_signal_status/ \ Cout /
The process signals shall be calibrated (chapter four); so that the
range of the control system I/O "input signal status", "output signal
status" and "control output" corresponds to the 256 symbols of the
subset "L". The I/O arrays InStatus, OutStatus and Cout shall
generate a single unique symbol based on the signal values at a
particular moment in time. The process arrays shall match these
unique symbols to a "elk" symbol for later mapping operations. The
resultant arrays are:
I InStatus \ / OutStatus\ /Cout\
\ elka / \ elka / \ elk /
17
5.5
Generation of the Process Arrays
Process arrays map the output as a function of two input test
signals f(t) and -f(t) using the "elk" array. Referring to (figure 5-1) this is
done by directly mapping the InStatus array to the Cout array so that the
control system is bypassed:
Represented symbolically: oroLutpuuj~ess
\ Cout
0
InStatus
input_signal_status
Two process arrays are created for each test signal; for the test
input signal fR(t) these two arrays are named IR and OR. The following
mapping occurs to generate the arrays:
a. The "elk" array symbol sequencing is started.
b. The test input signal fR(t) is applied to the process and the
associated array "InStatus" generates a symbol representing the
signal value.
c. The process output status array "OutStatus" generates a symbol
representing the process output value.
d. Both generated "InStatus" and "OutStatus" symbols are matched
to the "elk" symbol generated during the same cycle to create the
process arrays IR and OR These arrays are represented as:
and or
elka elka
18
e.
The steps followed above are represented symbolically as:
IR
clka
OR
clka] Generated Process Arrays
o
0
IR (clka) (clka) OR V mapping
\ InStatus/ ^OutStatus/
$ 0 O
InStatus \ j clka \ / OutStatus \ input symbol
, input_signal_status J l elk J \ output_signal_status / generation
fIR(t) Input Signals fOR(t)
Chapter six deals with generating the actual I/O and Process
arrays to be used, including these two. The result is four process
arrays generated by two test signals; fR(t) and fF(t). Where:
fR(t)= f(t) and fF(t)= -f(t)
The type of test signals to be used is an Operator entered
parameter. For this thesis the test signals shall be exponentially
based functions. The four generated process arrays are then:
test signal: fR(t) = f(t) test signal: fF(t)= -f(t)
IR IF
Process input array: clka Process input array: clka
Process output array: OR clka OF Process output array: clka
19
5.6 Generation of the Process Mapping
There are two types of mapping, mapping through the present
inputs and mapping through the past input values. Starting with the control
system of (5.2):
@ time "t+1"
control_output_to_process
Cout
0
Cout \
Couta_Coutb /
} matrix C
o
0
Ma {
Couta
\ InStatus OutStatus/
} matrix M {
Coutb
InStatus OutStatus/
-} Mb
o
o
InStatus
L
OutStatus
input_signal_status / \output_signal_status
time T
time T
InStatus
clkb
time "t-1
OutStatus \
clkb j
time "t-11
The goal of this control system is to intercept an input signal and
substitute a second one such that the output tracks the input. This allows the
mapping to consist of matrices that emulate the inversion of the Process
arrays (5.5) as the values of process input and output change.
20
The mapping starts with the generated test arrays:
a.
Process input/output
arrays for test signal
f(t):
IR OR
clka clka
Process input/output
arrays for test signal
-f(t):
IF OF
clka clka
b. Total range of the process input is from -f(t) to f(t); with the number
of unique signal values not exceeding 256. This being the
cardinality of the subset "L". This implies the cardinality of the four
Process arrays are such that:
b.1 Sum of the cardinalities of IR and IF equal 256.
b.2 Sum of the cardinalities of OR and OF equal 256.
b.3 It shall be assumed for this thesis that the cardinality of the four
process arrays shall be equal and number 128.
b. 4 From (2.6.a) the sequence of symbols for the subset "L" runs from
1 to 256. The midpoint is then at 129 (the "ceil" function in
Mathcad rounds 128.5 to 129).
c. The common mapping point between the test signals"f(t)" and
"-f(t)" is at f(0); this is the result of the calibration requirements of
chapter four.
d. Thus the mapping between the different arrays will be in blocks of
128 (common mapping point at the symbol 129) or 256 symbols.
Figures 6.4 and 6.5 plot the resultant process arrays.
21
5.7 Generation of the Mapping Matrix "Ma"
a. The process arrays map the relationship between the input/output
signals. This mapping is represented as:
For f(t): For -f(t):
OR OF
elkr elkf
OR
o mapping: IR o mapping:
elkr
elkf
IR IF
b. From (5.6.b) the process arrays contain independent values
mapped to a common symbol sequence (the "elk" array); the
arrays can then be combined to form:
OR . OF O test
maps: =
IR IF I test
c. An inverted form of this, when mapped to the test signal, will
generate an output signal that creates the original input signal.
Inverting and mapping the arrays:
IR elkr IF 0 elkf maps: MI elk test input signal mapped via "elk"
elkr * elkf 0 maps: MO "elk" mapped via
OR OF elk test output signal
Figure 6-6 plots the arrays Ml and MO.
22
d.
Mapping the two arrays Ml and MO:
input test signal: mi
elk
0) maps to:
MO
output test signal: clk
MI
MO
elk
This array represents the inverted test signal output/input mapping:
i_test
o test
Where "o_test" represents the system output (test signal) and
"i_test" the mapped signal to the process that would recreate the
test input signal at the output. Figure 6-7 plots the array:
With
MI
MO
elk
becoming the array:
elk
e. Starting with the matrix Ma used to map the present inputs:
Ma {
Couta
InStatus OutStatus
e.1 Then splitting the matrix Ma:
Ma { (-------------------\ becoming:
\ InStatus_OutStatus /
Couta
MI_MO
Q
MI MO
InStatus OutStatus
23
Couta
into two seperate arrays:
e.2 Splitting the matrix
MI_MO
Couta
MI
0
MI
With Couta becoming: [ M0\
MIMO [clkaj
0
clka
MI_MO
The mapping of is performed in (5.9).
MI
e.3 This mapping of the matrix Ma represents only the mapping for the
elk symbols common to both Ml and MO, the mapped test signals;
(figure 6-6).
To map the cells of the array:
with the referenced cells in the matrix:
MI
InStatus OutStatus
MI
Requires a shifting of the array /M0\ as a mapping of the signal
\ clka /
inputs "InStatus" and OutStatus".
MI
/MO)
\clka /
0
clka
MI_MO
MO
24
e.4 The shifting of clka in the matrix clka is based on the following:
MI MO
e.4.1 Each array, Ml and MO, is composed of two seperate arrays
based on on the rising and falling test signals. They are grouped
in symbol blocks of 1 to 128 and 129 to 256. As seen in figure
6-7, these two blocks are mirror images of each other.
e.4.2 When both arrays, Ml and MO, are mapped to a common elk
symbol, these two arrays can be thought of as in phase, with the
InStatus symbol operating as a type of reference point. As the
InStatus symbol sequences along the elk array, the OutStatus
mapping to the output/input array:
must be shifted by an equal amount. This is required to maintain
the phase relationship during the mapping of OutStatus to clka.
Chapter six (6.3.e) generates the complete matrix mapping for Ma,
with figures 6-8A and 6-8B illustrating the clka shifting. Matrix Ma is
mapped as:
MI
MO
clka
Couta
MI
Ma {
InStatus OutStatus
Couta
is mapped as:
MI
clka
MI MO
MI
MO
InStatus
OutStatus
25
5.8 Generation of the Mapping Matrix "Mb"
a. The mapping matrix Mb is first split in the same manner as the
matrix Ma:
Mb{ f--------------------) becoming:
\InStatus_OutStatus /
Coutb
MI_MO
MI MO
InStatus OutStatus
So that Mb is mapped as:
Coutb
MI
0
MI
(MO\
\clkbj
clkb
MIMO
0
MI MO
InStatus OutStatus
Where the shifting of clkb is performed in the same manner as in
matrix Ma. "Cout" represents the last symbol generated by the
control system that was outputted to the process.
The mapping of is performed in (5.9).
MI
Chapter six (6.3.f) generates the complete mapping of matrix Mb.
26
5.9 Generation of the Mapping Arrays Couta and Coutb
a. The mapping arrays:
Couta ^ Coutb
MI MI
can be generated via the method as (5.5.e):
Couta
cika
Coutb
clkb
Generated Mapping Arrays
o
o
(Couta) (clka)
0
clka
elk
(clkb) (Coutb)
clkb
elk
For this thesis there shall be a one to one mapping between the
"Cout" symbols and their respective "clk"symbols. This implies that:
Couta
MI
maps to:
clka
elk
which results in:
elk
and:
Coutb
MI
maps to:
clkb
elk
which results in:
elk
27
5.10 Generation of the Mapping Matrix C
a. From (5.2), matrix C is represented as:
Cout
Couta Coutb
} matrix C
From (5.9), this maps to:
Cout
elk
elk
elka elkb
(elk
---w*.--
clka_clkb
b.
Which from (5.2.a), is a submatrix "crystal" of size:
2562 = 6.554-104
The mapping of elk in the matrix)] is based on the following:
\clka elkb/
When both elka and elkb are mapped to the same symbol, these
two arrays can be thought of as in phase. The elka symbol, which
represents the present moment in time (5.3), operates as a type of
reference point. As the elka symbol sequences along the elk array,
the elkb mapping to the elk array must be shifted by an equal
amount. This is required to maintain the phase relationship during
the mapping of elk to elkb. Chapter six (6.3.g) generates the
complete matrix mapping for C.
28
5.11 Final Mapping Relationships
The resultant mapping relationships for the control system:
a. Initially:
@ time "t+1"
j control_output_to_process\
\ Cout /
0
Cout
Couta Coutb
} matrix C
Ma { (---------] } matrix M{
\InStatus_OutStatus /
Coutb
InStatus OutStatus
}
Mb
InStatus
input_signal_status
@ time "t"
OutStatus
output_signal_status
@ time Y
/ InStatus \
\ clkb /
time "t-1"
OutStatus \
clkb /
! time "t-1"
29
b. Final Mapping:
@ time "t+1"
control_output_to_process
elk
/ elk
\clka elkb
} matrix C
Ma {
elka
elk
0
MI
MO
elka
0
elka
MI_MO
fl>
MI
InStatus
} fixed mapping {
} elk shifting {
MO
elkb
elk
MI
MO
elkb
elkb
MI_MO
0
OutStatus
MI
0
InStatus
0
} Mb
MO
OutStatus
4>
InStatus
input_signal_status
@ time "t"
OutStatus
output_signal_status
@ time T
InStatus
elkb
OutStatus
elkb
time "t-1" @time"t-1"
30
6.
Control System Design and Modeling
6.1 Modeled Process and Input
a. Let the Process be described by the discrete transfer function:
ytH-2= l-67-yt+]-.67-yt+.211.xt+1 + .185-xt
Which is represented in this thesis as:
Output(t + 2) = 1.67-Output(ti-1) ,67-Output(t) + ,211-Input(t f 1) + .185-Input(t)
Plotting the outputs generated by some input signals, it can be
seen that this is not an inherently stable process. See figure 6-1:
t =i,2.. 1500 process input: fi(t) :=-
01 : =
s<-0
for te 1,2.. 1500
01^0
oi2<-o
Ilj*0
01t+2^ 1-67-01t+i .67-01t+ .211-Ilt+1 -t- .185-Ilt
01
02 : =
s-0
for te 1,2.. 1500
O2j<-0
02 0
L
02 - 1.67-02 .67-02t + .211-12 x + .185-I2t
02
31
process input: f(t) :=i-sin[)
03 := | s< 0 \170/
for te 1,2.. 1500
O3j<-0
032-
I3i<_0
D.+rt)
03, -1.67-03, - .67-03,-1- .211-13 + .185-13,
03
Figure 6-1:
Process outputs for inputs: fl(t) : = - f2(t) : = f3(t) := l-sin(
3 3 l170
b. For the purpose of this thesis, all Inputs to the control system shall
have the following properties:
b.1 Input signal values shall be within the range of +/-1.
b.2 Input signal settling times shall be no greater than Operator
determined process settling time.
32
b.3 The two test signals to be used shall be:
b.3.1 Continuously increasing input signal: fR(t) := i-(i e 70
b.3.2 Continuously decreasing input signal: fF(t) :=i-(e 70 1,
b.3.3 Plotting the input test signals fR(t) and fF(t); figure 6-2:
Figure 6-2:
33
b.4
Generating the resultant outputs OR(t) and OF(t):
t := 1,2.. 300
Rising input test signal; fR(t) := i-\i e
70
Generating the resultant output:
Or
s<0
for te 1,2..300
Orj<-0
Or2<-0
Ir^O
Ort+2-1.67-Ort+1- .67-Ort+.21Mrt+1 + .185-Ir(
Or
Falling input test signal; fF(t) := i-
_t_
70
- 1
Generating the resultant output:
Of := I s<-0
for tg 1,2..300
Of^O
Of2^0
Ifj-0
ft+2- 1 -67-Of,+, .67-Of, + .211-Ift+, + .1 85-If(
Of
34
b.5 Plotting the resultant outputs of the test signals, Or(t) and Of(t),
see figure 6-3.
Figure 6-3:
6.2 Calibrating Input and Output Signals
Shifting the amplitude of the signals into the range required in
chapter four:
a. Test Inputs:
fR(t) := l-(l e 70
fF(t) :=l-(e 70 1
elk := 1,2..256
Generating the calibrated input symbols from the A/D converter
"InStatus":
IR :=
s<- 1
IF := S'
1
for elke 1,2..256
1 IRclke- ceil( 128-fR(clk) -t- 128)
| IR
IR
for elks 1,2..256
IFcIk-ceH( i^-fFCdk)-t- i28)
IF
IF
35
a.1 Plotting the input test signals after translation through the A/D
converter "InStatus", figure 6-4.
Figure 6-4:
a.2 Generating the resultant calibrated output symbols from the D/A
converter "OutStatus":
OR :=
s<-0
for clke 1,2 ..256
r
o2^o
Ir
cIk+2- l-tf-Odk+i -t** -211-Wi + 185 Iclk
OR
elk
ceil[ 'Oclk +-128
OR
OR
36
OF : =
s-0
for clke 1,2-256
oro
o2-o
!r0
Wrff(dk)
dk+2- 1'67-dk+. 67'c.^ 211-Iclk^l + 185'1clk
OF
elk
ciHl.Ot|li+ 128
OF
OF
b. Plotting the output test signals after translation through the A/D
converter "OutStatus", figure 6-5.
Figure 6-5:
37
6.3
Generating the Mapping Arrays
a. Mapping together and inverting the input and output arrays per
chapter five (5.7.c):
MI := s<-0
I for elke 1,2..256
I MI 128
clIk
I MI
for elke 1,2..256
MI
IF.
elk
elk
.MI
for elke 1,2..256
ML
IR
elk
elk
MI
MI
MO :=
s*-0
for elke 1,2..256
I MO 128
| elk
I MO
for elke 1,2..256
MO,
OF.
elk
-elk
I MO
for elke 1,2..256
MO,
OR
elk
elk
MO
MO
b. Plotting the resultant mappings Ml and MO, figure 6-6:
The points across the center of the plot represent gaps in the
arrays caused by converting floating point values to integer. These
gaps must be filled for the mapping operations to occur (4.1).
Erratic system operation can occur due to the arbitary nature of
filling in these gaps.
38
c.
Mapping the "elk" array through Ml to MO per chapter five (5.7.d):
io
s<-0
for elke 1,2..256
10 MI
elk
(MOclk)
10
d. Plotting the resultant mapping IOdk, figure 6-7.
Figure 6-7:
39
e.
Generation of the mapping matrices Ma and Mb per chapter five
(5.7.e):
Ma :=
s<-0
for clke 1,2..256
for clkae 1,2..256
^dk.dka^128
L- 128
for clke 1,3 ..255
for clkae 1,2.. 128
MbMIclk'MOclka^IOclka + L
L<-L- 1
L- 128
for clke 2,4..256
for clka e 1,2.. 128
MaMIClk'MOolka"I0^a + L
L-L- 1
L<-0
for clke 1,3..255
for clkae 129,130..256
^dk-^dka^^clka-L
L-L-t- 1
L*-0
for clke 2,4..256
for clkae 129,130..256
MaMIdk-Mdka^I0<=lka-L
L-L+- 1
Ma
40
Figure 6-8A; Ma, with 10 shifting of the symbol block [1 to 128] at
elk symbol "64":
Figure 6-8A:
41
Figure 6-8B; Ma, with 10 shifting of the symbol block [129 to 256]
at elk symbol "192":
Figure 6-8B:
42
Figure 6-9; Matrix Ma at the midpoint, showing the cross
correlation between the input/output mapping of
Ma and Mb versus the inverted 10 response. The
10 response is based on a desired one to one
matching of process input and output (5.1 .a).
The symbol "128" represents gaps in the matrix
created during generation. Chapter seven details
the results of these gaps.
Figure 6-9:
ST| 119 .120: 121 122 M3 124 125 1126 1*27. 128 M9 .130, -m ;13I !S3i 18
fl9 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128
m 128 20 128 18 128 17 128 128 128 128 128 12 128 11 128 128
0b 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128
122 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128
Si 128 64 128 61 128 59 128 56 128 49 128 53 128 50 128 48
\i4 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128
Wi 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128
,V\ 12S 128 18 128 17 128 128 128 128 128 128 128 11 128 128 128 128
Wk 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128
111 128 97 128 92 128 88 128 86 128 137 128 79 128 76 128 74 .
H 128 65 128 64 128 61 128 59 128 53 128 54 128 53 128 50
iP 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128
131 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128
132. 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128
fH 128 17 128 128 128 128 128 12 128 128 128 128 128 128 128 7
134 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128
13.5 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128
136 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128 128
43
Generating the matrix Mb:
Mb : =
s-0
for clke 1,2..256
for clkbe 1,2..256
Mhdk.dkb- 128
L<- 128
for clke 1,3 ..255
for clkbe 1,2.. 128
Mbyr l^fO * 10 ... T
^dk-^clkb clkb + L
L<-L- 1
L<- 128
for clke 2,4..256
for clkbe 1,2.. 128
Mb
,MIclk ^clkb< IOclkb-i-L
_ LL- 1
L< 0
for clke 1,3 ..255
for clkbe 129,130..256
MbMIdk'MOdkb^IOcikbL
L-L-t- 1
L<-0
for clke 2,4..256
for clkbe 129,130..256
Mb
|L-L + 1
Hlk-MOdkb"I0^b-L
Mb
44
g-
Generation of the mapping matrix C per chapter five
(5.10.a):
for clkae 1,2.. 128
for clkbe 1..256
r <_1
dka.dkb
for clkae 129,130..256
for clkbe 1..256
Cclka,clkb<_ 256
L< 1
for clkae 1,2.. 128
M<-L
for clkbe L.. 1
^dka.dkb*- ^
M*-M-h 1
U-L+- 1
L<- 1
for clkae 1,2.. 128
M-L
for clkbe L..Cl j
I ^dka, dkb^~ ^
M<-M- 1
L-L+ 1
for clkae 129,130..256
Lf- clka
for clkbe clka..256
^dka.dkb*- ^
L-L- 1
L< 1
45
L<- 1
for clkae 128,129 ..255
M*- clka
for clkb e clka.. CL t
^clka.clkb*- ^
M<-M+ 1
L
|c
Figure 6-10; Matrix C at the midpoint, showing the mapping
between matching input and output blocks. If the
matrices Ma and Mb generate elk symbols in
different blocks; i.e. one symbol is from the block
[1 to 128] and the second is from the block [129 to
256] no mapping can occur. The system cannot
identify relative signal polarities between InStatus
and OutStatus.
Figure 6-1:
.1221 123* 125: T26' 127 128 A 29 130 "131!
15 120 119 118 117 116 115 114 113 112 Ill
H 122 121 120 119 118 117 116 115 114 113
12% 124 123 122 121 120 119 118 117 116 115
M 126 125 124 123 122 121 120 119 118 117
125 128 127 126 125 124 123 122 121 120 119
126 130 129 128 127 126 125 124 123 122 121
12?. 132 131 130 129 128 127 126 125 124 123
m 134 133 132 131 130 129 128 127 126 125
p--, M 136 135 134 133 132 131 130 129 128 127
It 138 137 136 135 134 133 132 131 130 129
13-1" 140 139 138 137 136 135 134 133 132 131
in 142 141 140 139 138 137 136 135 134 133
WWAS* i3.3; 144 143 142 141 140 139 138 137 136 135
w 146 145 144 143 142 141 140 139 138 137
46
6.4
Final Control System
The original modeled process (no control system):
O :=
s<-0
for te 1,2.. 1500
10^0
o2-
!r0
ot+2*-i.(n-ot+l-.67-0^211^.1*5^
0
The process with symbolic control system:
O =
s<-0
for tG 1,2..300
r'
o2<-o
i.-
InStatus- ceil( 128-f(t) +-128)
OutStatus<- ceil^8-0( +- 128 j
mb , OutStatus
OutStatus*- ceil^2-0(+ j +-128^
ma<- MaInStatus0u(Status
Cout*- C
I.
t-f-1
,
O
} input to system
ma,mb
Cout- 128
128
t+2. 1.67.0t+]-.67-0t^.21Mt+1-b.l85.It
} input to process
47
Figure 6-11:
OR" Process output for: fR(t) :=l-(l e 70
OF" Process output for: fF(t) '= 1 -(e 70 1(
Figure 6-12:
"05" Process output for: f(t) :=-
2
"Oo" Process output for: f(t) :=o
"0_5" Process output for: f(t)
2
48
Figure 6-13:
"OS" Process output for: f(t) :=sinf]
\70 /
49
7.
Analysis of Methodology
7.1 Behavior due to Control System Granularity
Chapter one described how this methodology is based on the
fundamental granularity of a digital control system. As can be seen from
Figures 6-12 and 6-13, this granularity also causes problems. During the
initial process mapping, a continuos process of rounding off occurs. This
produces "gaps" which accumulate during the generation of the mapping
matrices.
A great proportion of this thesis was devoted to methods of
eliminating these gaps without numerical or Boolean methods. Figure 6-9
illustrates the extent these gaps (symbol "128") occur.
There were two major effects these gaps produced:
a. The gain of the past "OutStatust" and present "OutStatust+i"
calibration functions in (6.4.b). These were to have been a gain
of 1/2 based on (6.2.a.2). Different modes of operation appeared
at different values. Accurate reproduction of some constant inputs
occurring at gains of eight and two respectively. This seemed to
be based on having enough gain so that the next process value
could generate a different control symbol. The initial test input
signals tolerated a wide range of gains, from 4 to 60.
b. Figure 6-12 illustrates the problems these gaps created for
constant input signals. Any values that generate mapping into the
gaps produce erratic operation. These gaps have patterns.
Variable input signals allow a set of stable mapping relationships
to be generated by "sweeping" across these mapping patterns.
50
7.2
Resultant System Size
Csize :=3-(2562) + 3-(256) + 5
Csize = 1.974* 105
a. This does not include the size of the matrix generation operation:
Msize : = 2-(2562)-4
Msize= 5.243-105
b. The total size of this system is then:
Total := Csize +- Msize
Total =7.217-105
c. A complete solution (5.2) produced a system size of:
matrix_size : = 2.185-1014
or
matrix size
-----= =3.028-10 Big size savings.
Total
51
7.3 Methods for Improvement of Operation
To produce satisfactory operation, a separate mapping system
that modifies the matrices Ma and Mb based on current behavior is
desired. This input/output symbol mapping would then eleminate the fixed
test functions fF(t) and fR(t). Gaps would then be filled as the system
operated.
7.4 Conclusion
During work on this thesis, the evolving control system seemed to
resemble a primitive cell. Only a few simple mapping pathways available
to perform an operation, with signal variations required to achieve a stable
mode of operation.
Assuming a midpoint average, each decision making operation
requires:
Csize :=3-(l282) +- 3-( 128) +- 5
Msize :=2-(1282)-4
Csize +- Msize = 1.806 105
A total of 180 thousand symbols to be mapped. Using a special
built symbolic control system (1.4), this results in three cycles being requirec
to operate.
52
bibliography
1. Mike Radenkovic, course notes EE-5466: "Adaptive Control
System Design", University of Colorado, Fall 1996.
2. David G. Luenberger, "Introduction to Dynamic Systems",
Stanford University: John Wiley & Sons, 1979.
3. Chang C. Hang, "Adaptive Control", Instrument Society of
America, 1993.
4. John C. Doyle, "Feedback Control Theory", California Institute of
Technology: Macmillan Publishing Company, 1992.
53