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Construction and analysis of a BJT simulator

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Title:
Construction and analysis of a BJT simulator
Creator:
Luzietti, Jason Charles
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English
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59 leaves : illustrations ; 28 cm

Subjects

Subjects / Keywords:
Bipolar transistors ( lcsh )
Junction transistors ( lcsh )
Bipolar transistors ( fast )
Junction transistors ( fast )
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bibliography ( marcgt )
theses ( marcgt )
non-fiction ( marcgt )

Notes

Bibliography:
Includes bibliographical references (leaf 59).
General Note:
Department of Electrical Engineering
Statement of Responsibility:
by Jason Charles Luzietti.

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University of Colorado Denver
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Auraria Library
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ocm49642019
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Full Text
Construction and Analysis of a BJT Simulator
by
Jason Charles Luzietti
B.S., Metropolitan State College at Denver, 1996
A thesis submitted to the
University of Colorado at Denver
in partial fulfillment
of the requirements for the degree of
Master of Science
Electrical Engineering
2001


2001 by Jason Charles Luzietti
All rights reserved.


This thesis for the Master of Science
degree by
Jason Charles Luzietti
has been approved
by
Jan T. Bialasiewicz
1I I "Z- c / O I
Date


Luzietti, Jason Charles (M.S., Electrical Engineering)
Construction and Analysis of a BJT Simulator.
Thesis directed by Associate Professor Hamid Z. Fardi
ABSTRACT
This thesis explains the physical properties and electronic models of the
Bipolar Junction Transistor. The pn junction, DC, small signal, high
frequency, and modified high frequency models are discussed.
This thesis explores the construction and verification of a BJT simulator.
Engineering and programming techniques in the construction of a simulator
are detailed. The simulator is written for a BJT in the forward active region
using integrated circuit 2.5-micron vertical NPN process parameters. The
simulator uses a modified high frequency BJT model. Simulation results are
verified with Pspice.
This abstract accurately represents the contents of the candidates thesis. I
recommend its publication.
Signed
Hamid Z. Fardi
IV


DEDICATION
I dedicate this thesis to my family. I dedicate this to my mother and
father for instilling in me the drive to be my best, and the work habits
necessary to do it. I dedicate this to my family who has shown me that
inspiration in Electrical Engineering sometimes comes from following lifes
other paths. I would like to thank my sister and my mother for listening, or at
least pretending to listen, to my explanations of electrical properties.
Lessons learned from:
My mother Carol and my father Richard:
Self Be who you are.
My brother Steven:
Read There is always something new to learn.
My brother Brian:
Confidence Trust in yourself.
My brother Alan:
Strength Find your power.
My sister Sara:
Life It is less than it seems and more than you think. Have fun.


ACKNOWLEDGEMENT
My thanks to the staff of the Electrical Engineering Graduate School for their
support and understanding. This staff is very understanding to the plight of
the individual who balances their career in academia versus their career in the
workplace. Thanks to my advisor Professor Hamid Fardi for his patience with
me during the selection of my thesis topic. Thank you all for having a passion
for Electrical Engineering and the profession of education.


CONTENTS
Figures............................................................ix
Tables..............................................................x
Chapter
1. Authors Background.............................................1
2. Introduction (Thesis Direction).................................2
3. IC Processes....................................................3
3.1 Bipolar Process.................................................4
4. BJT Introduction/Definition.....................................6
4.1 N-Type Semiconductor............................................6
4.2 P-Type Semiconductor............................................7
4.3 PN Junction.....................................................7
4.3.1 Depletion Layer...............................................8
5. BJT Model Types and Electronic Model Definition................10
5.1 DC Model.....................................................10
5.2 Small Signal Model.............................................14
5.3 High Frequency Model...........................................15
5.3.1 Parasitic Capacitances.......................................16
5.3.1.1 PN Junction Capacitances...................................16
5.3.1.2 Majority Carrier Charge Accumulation Capacitances..........17
6. Modified High Frequency Model..................................19
6.1 Model Defined Parameters (Constants)...........................21
6.2 User Defined Parameters (Variables)............................23
6.3 Equations......................................................23
7. Simulation of the Modified High Frequency Model................25
7.1 Methodology (Language, GUI, 00, Inputs, Outputs)...............26
7.2 Order of Calculations..........................................28
8. Simulator Results..............................................32
8.1 Small Collector-Substrate Junction at High Frequency...........32
8.2 Large Collector-Substrate Junction at High Frequency...........36
9. Comparison with Pspice.........................................39
10. Conclusions....................................................43


Appendix
A. BJT Simulator Source Code.....................................45
B. Pspice Netlist of Modified High Frequency Model................57
References........................................................59
viii


FIGURES
Figure
3.1 Types of Major IC Processes......................................3
3.2 Top View of Vertical NPN Transistor..............................5
3.3 Cross-Section of Transistors in the Bipolar Process..............5
4.1 N-Type Semiconductor Atomic Structure............................6
4.2 P-Type Semiconductor Atomic Structure............................7
4.3 PN Junction Depletion Layer......................................7
4.4 Electron Flow Through a PN Junction..............................8
4.5 Basic NPN BJT Construction.......................................9
4.6 Basic PNP BJT Construction.......................................9
5.1 Ebers-Moll DC Model of the BJT..................................11
5.2 BJT Modes of Operation..........................................11
5.3 BJT Equivalent Circuits for the Modes of Operation..............13
5.4 BJT Ic vs. VCE Plot.............................................14
5.5 BJT Small Signal Model..........................................15
5.6 Cross-Section of Vertical NPN and Lateral PNP BJT...............16
5.7 BJT High Frequency Model........................................18
6.1 Modified BJT High Frequency Model...............................20
7.1 Simulated Circuit Schematic.....................................25
7.2 Simulated AC Circuit Schematic..................................25
8.1 Simulator Screen Shot of Scenario 1 at 120KHz...................34
8.2 Simulator Screen Shot of Scenario 1 at 250KHz...................35
8.3 Simulator Screen Shot of Scenario 2 at 120KHz...................37
8.4 Simulator Screen Shot of Scenario 2 at 250KHz...................38
9.1 Pspice Simulation of Scenario 1.................................41
9.2 Pspice Simulation of Scenario 2.................................42
IX


TABLES
Table
3.1 Electrical Components Available in the Bipolar Process...........4
5.1 Simplified Model of BJT Regions of Operation....................12
5.2 BJT Small Signal Model Parameters...............................15
5.3 PN Junction Capacitance Equations...............................16
5.4 Majority Carrier Charge Accumulation Equations..................17
6.1 NPN BJT Model Conditions of Simulated Circuit...................20
6.2 Constants of the Simulated Circuit..............................21
6.3 Variables of the Simulated Circuit..............................23
6.4 Modified High Frequency Model Equations.........................24
8.1 Scenario 1 Parameters...........................................32
8.2 Scenario 1 at 120KHz Simulator Input Parameters.................33
8.3 Scenario 1 at 120KHz Simulator Results..........................33
8.4 Scenario 1 at 250KHz Simulator Input Parameters.................35
8.5 Scenario 1 at 250KHz Simulator Results..........................35
8.6 Scenario 2 Parameters...........................................36
8.7 Scenario 2 at 120KHz Simulator Input Parameters.................36
8.8 Scenario 2 at 120KHz Simulator Results..........................36
8.9 Scenario 2 at 250KHz Simulator Input Parameters.................37
8.10 Scenario 2 at 250KHz Simulator Results.......................37
9.1 Comparison of Pspice and Simulator Results.....................39
x


1. Authors Background
Academic Background:
I am Jason Luzietti a Masters of Science Candidate in Electrical Engineering
with an emphasis in VLSI & Microelectronics. My current GPA is 3.8 and I
am graduating this Fall 2001.
Professional Background:
I am a senior consultant for CIBER Inc. I specialize in web and database
development. I design the database structures and develop applications that
act upon these database structures. I work on projects that reengineer old
paper processes into web accessible applications. The programming and
scripting languages I use are PL/SQL, C, Perl, SQL, HTML, and JavaScript.
1


2. Introduction (Thesis Direction)
This thesis involves detailed analysis of the npn BJT. This thesis applies the
engineering round trip.
The engineering round trip is a process used to solve problems. The
engineering round trip includes four distinct phases. The phases in order of
execution are analysis, modeling, simulation, and verification.
The analysis phase centers on the gathering and studying of data. In this
phase physical properties, models and their equations are investigated.
It is in the modeling phase that the engineer constructs his or her own model.
This model is constructed from the data uncovered in the analysis phase. It is
in this construction of a model that the engineer will test their hypothesis
against. In many cases the model constructed is a combination of the high and
low fidelity models.
The simulation phase is where the engineer puts their computer science skills
to use. The engineer will construct a computer simulator. The computer
simulator is a great means to capture thoughts. These thoughts can be easily
presented to their peers. With this simulator the engineer can also use the
results to refine their model.
The verification phase informs the engineer of the validity of their model. In
this phase a comparison between the engineers simulator and an industry
standard circuit simulator is made. In this thesis Pspice version 9.1 is used.
In conclusion, this thesis will inform of the inner workings of the BJT. It will
give background on BJTs and the fabrication processes. It will explain BJT
modeling, as well as detailed analysis of the high frequency model. It will
also explain the process involved in authoring a simulator in an industry
standard programming language. Then the verification is done with Pspice.
?


3. IC Processes
Figure 3.1: Types of Major IC Processes.
This thesis analyzes the IC (Integrated Circuit) BJT (Bipolar Junction
Transistor). The BJT resides in the bipolar IC process listed above in Figure
3.1. The bipolar process separates itself from the other processes in its
construction and its process parameters [1]. The process parameters define the
materials used and the geometry of the components [2]. For example the
minimum distance between metal 1 and metal 2 is defined in the process
parameters. There is a whole science behind the definition of IC processes
that this thesis will not explore
3


3.1 Bipolar Process
Electrical components available in the bipolar processes
1. npn bipolar transistors._____________________________
2. pnp bipolar transistors._____________________________
3. Resistors.___________________________________________
4. Capacitors.__________________________________________
5. Diodes.______________________________________________
6. Zener Diodes.________________________________________
Table 3.1: Electrical Components Available in the Bipolar Process.
The Bipolar process was very popular in the 60s and the 70s. The
bipolar process allows for high frequency operation, and it has large
transconductances. The bipolar process also includes these shortfalls: high
power dissipation, and a device density lower than MOS processes [1]. The
components that the bipolar process delivers are listed in Table 3.1.
There are two techniques for creating transistors on an IC. Both the
npn and the pnp transistor can be fabricated either vertically (Figure 3.2) or
horizontally (Figure 3.3). While the view from above of a transistor might
look clean and simple the cross-sectional view in Figure 3.3 shows otherwise.
The construction of these transistors depends on the substrate type. The
vertical npn BJT is used in the modified high frequency model discussed later.
4


Top view of vertical npn transistor

emitter
base p base region
collector___________________________n' epi region
Isolation diffusion_____________________________________________
n+ emitter region
Figure 3.2: Top View of Vertical NPN Transistor
collector base
transistor transistor
Figure 3.3: Cross Section of Transistors in a Bipolar Process.
5


4. BJT Introduction/Definition
4.1 N-Type Semiconductor
A substrate is doped to increase its number of conduction band
electrons. Commonly uses pentavalent (five valence electrons) impurity
atoms are added. Some of the common elements used in n-type doping are
arsenic, phosphorus, and antimony [3].
Antimony is used in this case (Figure 4.1) to form covalent bonds with
the surrounding silicon atoms. Four of the antimony atoms valence electrons
are used to make covalent bonds while the fifth valence electron is a free or
conduction electron not attached to any atom.
Free (conduclion) electron
Figure 4.1: N-Type Semiconductor Atomic Structure.
6


4.2 P-Type Semiconductor
A substrate is doped to increase its number of holes. To achieve more
holes in the substrate, trivalent (three valence electron) impurity atoms are
added. Some of the common elements used in p-type doping are aluminum,
boron, and gallium [3].
Boron is used in this case (Figure 4.2) to form covalent bonds with the
surrounding silicon atoms. All three of the boron valence electrons are used to
make covalent bonds. The absence of a four valence electrons in the boron
atom produces a hole in the doped substrate.
4.3 PN Junction
Figure 4.2: P-Type Semiconductor Atomic Structure.
Depletion layer
Figure 4.3: PN Junction Depletion Layer.
1


4.3.1 Depletion Layer
At equilibrium the PN junction forms a depletion layer. Figure 4.3
displays this depletion layer and barrier voltage. Some of the conduction
electrons from the n- type cross the junction to the p-type and recombine with
the holes. For each electron that crosses from the n region to the p region and
combines with a hole, the pentavalent atom of the n region is left with a
positive charge (a positive ion) [4]. When this electron recombines with a
hole in the p region a trivalent atom acquires a negative charge (negative ion).
Due to this, a large number of positive and negative ions builds up
towards the p-n junction. This is the depletion layer. Free electrons from the
n-type must now overcome the attraction to the positive ions and the repulsion
from the negative ions. This depletion layer results in barrier potential or
barrier voltage (VB).
Depiction
lavei
Figure 4.4: Electron Flow Through a PN Junction.
8


Figure 4.5: Basic NPN BJT Construction.
p n P
Emitter Base Collector
region region.. region
I
4
B
Figure 4.6: Basic PNP BJT Construction.
The three-terminal semiconductor definition is as follows. The basic
principle of the three-terminal semiconductor device is the use of the voltage
between two terminals to control the current flow in the third. From this one
can create a controlled source, very important in amplifier design. Another
mode of operation is the switch, this is very important in digital electronics.
These two modes make the transistor unique as well as important in modem
electronic designs.
- Sedra[4]
The BJT definition is as follows. The bipolar transistor is constructed
of two pn junctions connected in series. The pn junctions can be assembled
in the npn (Figure4.5) and pnp (Figure4.6) formats. The name bipolar is due
to the current being conducted by both electrons and holes.
- Floyd [3]
9


5. BJT Model Types and Electronic Model Definition
Device modeling in general
The fundamental goal in device modeling is to obtain the functional
relationship among the terminal electrical variables of the device that is to be
modeled [1].
The models are expressed in the basic electronic elements (voltage sources,
current sources, resistors, capacitors, inductors).
Design versus Process parameters
The circuit designer has control of the design parameters and judiciously sets
these parameters during design. The process parameters are characteristics of
the semiconductor process itself and are not modifiable [1].
5.1 DC Model
Definition: The DC model of a device is an electronic model that is accurate
over a large range of voltages at dc and low frequencies.
The DC model has four modes of operation; The saturation, cutoff,
forward active, and reverse active region. The saturation region occurs when
the base-emitter and base-collector junctions are forward biased. When this
happens, increases to the base current do not increase the collector current. In
the cutoff region the voltage across the base-emitter junction does not
approach the barrier breakdown voltage of the junction. When this occurs no,
or very little, current flows through the junction and thus cannot be amplified.
The output current is zero. This is clearly seen in Figure 5.3. The forward
and reverse active regions are the amplification regions. They are the regions
between cutoff and saturation. A plot of these regions is in Figure5.4. Table
5.1 includes the parameters of each mode of operation.
The Ebers-Moll model (Figure 5.1) defines the BJT at DC with two
diodes and two current sources [1,4]. The base-emitter and the base-collector
junctions are modeled with a diode, while the collector-emitter junction is
10


modeled with two current sources. This model works for all of the modes of
operation. As seen in Figure 5.2 the Voltage on the base-emitter and base-
collector junctions define the mode of operation. The mode of operation this
thesis focuses on is the forward active region.
Ebers-Moll DC model of the BJT
Ic
Figure 5.1: Ebers-Moll DC Model of the BJT.
Figure 5.2: BJT Modes of Operation.
11


Region of Operation NPN PNP
Forward active Ic = PfIb Ic = PfIb
Vrf = 0.6 V Vrc = -0.6 V
Reverse active Ic = PrIb Ic = PrIb
Vbc = 0.6 V Vbc = 0.6 V
Forward saturated Vbe = 0.7 V Vbe = 0.7 V
Vcf = 0.2 V VCE = 0.2 V
Reverse saturated VBC = 0.7 V VBC = 0.7 V
VCE = 0.2 V VCE = 0.2 V
Cutoff lc = 0 Ic = 0
Ib = 0 Ib = 0
Table 5.1: Simplified Model ofBJT Regions of Operation.
12


cutoff
E
B

o./ v p U.2 V
forward saturated
C
E

0./ V P- U.2 V
reverse saturated
Figure 5.3: BJT Equivalent Circuits for the Modes of Operation.
13


Regions of Operation
Forward active. Most applications use the transistor in this region.
Good current amplifier.
Reverse active. Smaller range of operation than the forward active
region.
Cutoff. Collector and Base currents are very small. Most models
define Ic = IB = 0.
Saturation. In the saturation region the transistor can be modeled by
two voltage sources VBe and VCe, the actual values depend on the
device.
5.2 Small Signal Model
Definition: Many applications of electronic components are used in a specific
operating range. Minimum input signal, maximum input signal, and
frequency range are usually defined for applications and occur around a
nonzero operating point. In many cases the inputs are sinusoids of small
amplitude. Analysis of these small sinusoidal inputs and how they traverse
throughout the circuit is small-signal or AC analysis [1,4]. Whether the small
signal model is valid depends on the device characteristics and circuit layout.
There is no simple rule declaring the range of input signals valid with the
small signal model.
14


The AC model shown in Figure 5.5 is of an npn BJT operating in the
forward active region. The small-signal model is the first time that the
junctions are assumed non-ideal conductors [1,4]. This model may be used
once the DC model is solved, calculating the base and collector currents. The
small-signal model parameters can be computed using Table 5.2. Input
admittance g, and output admittance g0 used with biasing resistors will
determine the output voltage.
Small signal model parameters
Ycb = gm = ICO / Vt___________
Ybe = g* = gm / Pf____________
Ybc ~ Q_______________________
Ycc ~ go ~ gm^t ^AF_________
Table 5.2: BJT Small Signal Model Parameters.
Small signal BJT Model
Ib Ic
Figure 5.5: BJT Small Signal Model.
5.3 High Frequency Model
Definition: In certain devices the DC and small-signal models are not
accurate when analyzing high frequency operation. In transistors, for
instance, parasitic capacitances come into play. The high frequency is usually
a refinement of the small signal model.
The high frequency model introduces two main types of capacitances.
These capacitances are junction capacitances, and charge accumulation
15


capacitances [1,4, 5]. The following sections lay out the background and
equations for these two types of capacitance.
5.3.1 Parasitic Capacitances
Figure 5.6: Cross-Section of Vertical NPN and Lateral PNP BJT.
5.3.1.1 PN Junction Capacitances
The depletion region creates the pn junction capacitances. These
capacitances are shown in Figure 5.6. At high frequencies these capacitances
become significant. The BJT junction capacitances are the same as those for
the pn junction diode model. The table below defines the values of pn
junction capacitances in the two regions of operation (forward and reverse
bias).
Equation Condition
C = Cj0A / (1 V / cpR)n V < cpB / 2
C = 2nCi0A r(2nV/(pB) + (l-n)l V > (pB / 2
Table 5.3: PN Junction Capacitance Equations.
Cjo is the junction capacitance density at zero volts bias.
A is the area of the pn junction,
cpe is the barrier potential,
n is a constant depending on the type of junction.
16


5.3.1.2 Majority Carrier Charge Accumulation Capacitances
The majority carrier charge accumulation occurs when the BJT is in the
forward active region. In this region of operation a second parasitic
capacitance is introduced at the base emitter junction. This capacitance is
caused by the discrepancy in the doping between the base and emitter regions.
Equation___________________
Cac = tflcQ / kT = t|gm
tf=WV2D
Table 5.4 Majority Carrier Charge Accumulation Equations.
tf is the base forward transit time. [5]
Icq is the quiescent collector current.
WB is the base width.
Dn is the electron diffusion constant.
Typical values for tf range from 0.1 nanosecond to 1 nanosecond for vertical
npn transistors, which are what this thesis analyzes.
When these parameters (Table 5.3 and 5.4) are solved they are placed
into the High Frequency Model of Figure 5.7. Note that the capacitor CBe is a
composite capacitance. The base-emitter junction has both a parasitic pn
junction, and a majority carrier charge accumulation capacitance.
17


High Frequency BJT Model
Rb
B -AAA-
c,
Figure 5.7: BJT High Frequency Model.
Rc
vW C
18


6. Modified High Frequency Model
Design Engineer vs. Process Engineer
The modified high frequency model developed is constructed for the
Design Engineer and not the Process Engineer. What is a process engineer?
A process engineer is someone who deals with the intimate workings of the
actual construction of a BJT. The process is analyzed and defined from the
silicon seed used to grow the ingot, to the etching of the substrate [1], For
example, the process engineer defines the minimum metal-to-metal distance.
The process engineer also defines the substrate capacitances and resistances.
The design engineer simply takes all of the parameters defined by the process
engineer and constructs a device to suit his or her application.
Model paradigm
The modified high frequency model constructed uses the design rules
for a typical bipolar process where X = 2.5 p [1]. The modified high
frequency model is a based on the small signal and high frequency models.
The entire small signal model (Chapters 5.2) is included, while only parts of
the high frequency model (Chapters 5.3) is used. The model used in the
simulation is not as thorough as the SPICE (modified Gummel-Poon) model
of the BJT. The model used in simulation for this thesis does not account for
noise parameters or temperature characteristic parameters. The model does
accept DC parameters, resistance and capacitance parameters, and physical
parameters (area and thickness).
19


Schematic
Modified high frequency BJT Model
Ib Ic
Definition
The model above takes into account the parasitic capacitances of the
base-emitter junction and the collector-substrate junction. The majority
carrier charge accumulation capacitance for the base-emitter junction is also
accounted for. The resistive properties of the base, collector, and emitter leads
have been ignored. The resistive properties of the emitter include a very small
voltage drop and only attenuate the output signal slightly.
Assumptions
Situation Description
Vbe > Vbc < Vcs < Table 6.1: NPN BJT Model Conditions of Simulated Circuit.
20


The modified high frequency model defined here assumes that the
base-emitter junction is greater that half of its barrier voltage, while both the
base-emitter and collector-substrate junctions are less than one half of their
barrier voltages. This is shown in Table 6.1. Thus the npn BJT is in the
forward active mode of operation.
6.1 Model Defined Parameters (Constants)
Constant Value Description
X (Lambda) 2.5 microns Length unit of measure

Cbeo 0.78 fempto F/micron2 Zero voltage base-emitter junction capacitance
Cbco 0.14 fempto F/micron Zero voltage base-collector junction capacitance
Ccso 0.062 fempto F/micron2 Zero voltage collector- substrate junction capacitance

Abe Ae Common Area of the base- emitter junction
Abc Ab Common Area of the base- collector junction
Acs Ac Common Area of the collector-substrate junction

9be 0.7 V Base-emitter barrier breakdown voltage

Vee 0 V Voltage at the emitter
Vcc 10 V Voltage at the collector
Table 6.2: Constants of the Simulated Circuit.
21


VsUB 0 V Voltage at the substrate

Vbe 0.7 V Voltage drop across base- emitter junction
Vcs 10 V Voltage drop across collector-substrate junction

R-bb 500KQ Resistance of base terminal
Rcc 3KQ Resistance of collector terminal
Ree 0 Q Resistance of emitter terminal

Tf 0.1 ns forward transit time (width of base)2/2(electron diffusion constant)
N 0.99 emission coefficient
Bf 100 DC current gain of BJT

Vt 25 mV Temperature dependant parameter
vAF 200 V Forward early voltage. Process Parameter.

Vin (0.003)sin(27rft) V AC voltage into base
Table 6.2: Constants of the Simulated Circuit (Continued).
22


6.2 User Defined Parameters (Variables)
Variable Value Description
Frequency (f) Hertz Frequency of voltage at base
Abe Lambda squared Area of the be junction
Acs Lambda squared Area of the cs junction
Table 6.3: Variables of the Simulated Circuit.
6.3 Equations
The equations required to solve this model are borrowed from the
previously discussed models. The DC model gives us the equations for the
current into the base, the current into the collector, and the DC current gain.
The small signal model gives the equations necessary to solve the input
resistance, the output resistance, AC current gain, the current into the base,
and the current into the collector. The high frequency model defines where
the pn junction and the majority carrier charge accumulation capacitances
reside. The high frequency model also defines the equation for the majority
charge accumulation capacitance. The model of the PN junction gives us the
equations for the parasitic capacitances.
The bias points of the BJT must first be solved. This is calculated with
the equations from the DC model outlined in Chapter 5.1. Table 5.1:
Simplified Model of BJT regions of operation contains the DC equations.
Fundamental Electrical theory is required to solve the external circuitry.
Chapter 7 will deliver the whole solution, while this chapter concentrates on
the modified high frequency model of the BJT.
The small-signal equations from Chapter 5.2 will also be used. Table
5.2: BJT Small signal model parameters list these equations. The
transconductances, g parameters, are necessary to solve this model.
As seen in Figure 6.1 the high frequency model in Chapter 5.3 is
23


needed. The capacitances CBe and CCs are calculated with the equations from
Table 5.3 pn junction capacitance equations, and Table 5.4 Majority carrier
charge accumulation equations.
These three models (DC, small-signal, high frequency) together with
the model-defined parameters of Table 6.1 give us the equations of Table 6.4.
Equation Description
Ic = PfIb DC current through the collector
gm = Icq / Vt AC model parameter determines internal current source
git = gm / Pf AC model parameter input conductance
CbE = CbEI + CBE2 Total capacitance across base emitter junction
CBEi=(2n) CBE0 Abe [2*n (VBE/ cpBE) + (1-n)] Parasitic pn junction capacitance across base emitter junction
CBE2=tf|CGm Majority carrier charge accumulation capacitance across the base emitter junction
Ccs= Ccso Acs [1/(1 (Vcs/ Table 6.4: Modified High Frequency Mode Equations.
24


7. Simulation of the Modified High Frequency Model
The circuit simulated is a base biased BJT circuit (Figure 7.1). The
models of the previous chapters must be used to analyze this circuit. This
circuit must be solved with the DC model, the small signal model, and finally
the modified high frequency model. This is exactly what the simulation
computes. The BJT symbol in Figure 7.1 is replaced with the modified high
frequency model defined in Chapter 6. The same circuit looks different to
AC. This is shown in Figure 7.2.
Simulated AC circuit
0.003sm(2*pi*ft) C\j)
500K
|^BE |^ct
3K
Figure 7.2 Simulated AC Circuit Schematic
25


7.1 Methodology (Language, GUI, OO, Inputs, Outputs)
This simulator was built with several goals in mind. There were seven
main goals. One: the simulator will use a standard Microsoft Windows
interface. Two: the simulator will be written in a standard programming
language. Three: the simulator will be created as a portable compiled
executable file. Four: the simulator will use a familiar user interface. Five:
the simulator will allow the user to supply text inputs. Six: the simulator will
output both text, and a graphics. Seven: the simulator will generate the text
and graphical output based on the modified high frequency model of a BJT.
Borland C++ Builder 5.0 was chosen as the development tool for many
reasons. With its basis on C++ it inherently allows compilation of code into
executable files. This is different from interpreted languages like Perl. It
allows for the creation of a clean and solid user interface [6, 7]. Its form
editor includes all of the standard GUI objects. The menu bar, the text box,
the window, the checkbox, and the button and many more are defined as
objects. All of these objects had events that can be trapped. This allows for
an interactive simulation. The Borland C++ builder allowed for text field
manipulation and pixel manipulation [6, 7]. This allowed me to output text
and waveforms. Understanding the choice of Borland C++ Builder as the
language for the application, the C++ Builder code is discussed.
Borland C++ Builder has two main programming types. These two
programming types are forms and units [6, 7]. The form is a graphical entity.
It is the window to which information is to be presented. The unit is the code
that acts upon the changes to the window. The unit could be compared to the
electronics of a TV, while the form is just the CRT.
The forms are created with the visual editor of the Borland C++ builder
IDE (Integrated Development environment). They are purely graphical
objects that have a common set of events that may be trapped by other code.
This simulator has three forms, main, graph, and about.
26


The main form is the first form that is displayed on the launch of the
simulator. This form contains all of the input and output text boxes. It also
includes a menu bar that includes a call to both the about box and the analyze
function. When the main form is closed the entire program terminates.
The graph form is the form that is spawned when the main forms
analyze button is clicked. This form defines the height and the width of the
waveform output.
The about form is the form that contains information about the
simulator. It lists the author, date, title, and revision of the software.
The units make the program work. A functional breakdown the main,
graph, and about units are next. The main unit defines the main form and all
global variables, constants, and functions. The simulators main unit includes
the event handlers for clicking on the analyze, exit, and the about
buttons. The graph unit does all of the calculations and outputs both the text
and the graphics. The about unit is the smallest of the three units. The about
unit only needs to open the about form. No other processing is required.
There are many unique features included in this simulator. One of the
unique features is the graphing function. The graphing function is
independent of the graph form. The graph form can be stretched to be larger
or smaller, square or rectangular. The graphing function always gets the width
and height of the form during compilation. This allows the programmer to
separate the presentation from the computation. First the graphing function
was written then a good size for the graphing window was determined.
The graphing function also only displays 5 periods of the waveform no
matter the frequency. The amount of periods of the waveform are displayed in
the window are independent of frequency. This is easier for the user to
analyze.
There is one form for both the input and the output. This way the user
can easily compare the input parameters with the results.
27


7.2 Order of Calculations
An order of calculations must be applied to the equations discussed in
Chapter 6. Calculations for DC model must be completed first. The DC
analysis results in the bias voltages and currents (IBq, Icq, Vce, Vbc). This is
displayed in the code snippet below.
//--------------------------------------------------------------------
// DC model parameters
//--------------------------------------------------------------------
double I _bq = (V cc - V be) / R bb;
double l" _cq = Bf dc * I_bq;
double V ce = V cc - (R cc I cq);
double v" be = V be - V ce;
The results of the DC analysis are used in the AC analysis. The g
parameters, transconductances, rely on ICq. The calculation of the g
parameters is listed below. The equations for the g parameters are located in
Table 5.2. If it was decided that the small-signal analysis is satisfactory the
program need not progress, but this simulator will also include the high
frequency parameters.
// Calculate G parameters
double G_m = I_cq/Vt;
double G_pi = G_m/Bf_dc;
double G_o = I_cq/Vaf;
Calculations for modified high frequency model include the parasitic
pn junction and majority carrier charge accumulation capacitances. The
collector-substrate junction has only a parasitic pn junction capacitance, while
the base-emitter junction has both. The simulator outputs the AC voltage
gain, total voltage out, and the phase angle of the voltage out in text format.
The solution to these values is next. An AnsiString (C++ variable type
syntax) variable is created for each of the text outputs. The AnsiString
variables are populated in the code below. Now that the text has been output
the graphic can be output.
28


The waveform that is to be output needs is a function of time. Once the
capacitances and conductances have been defined the voltage dependant
current source of the modified high frequency model in Figure 7.2 must be
solved. Voltage is time dependent, forcing us to construct a loop structure in
the program code.
// Tranform Junction Areas from LambdaA2 into MicronA2
A_be = A_be pow(Lambda, 2);
A_cs = A_cs pow(Lambda, 2);
// Calculate parasitic capacitances
double C_bel = pow(2, N) C_beO A_be (2 N (V_be /
PHI_be) + (1 N));
double C_cs = C_csO A_cs (1 /pow((l (V_cc / PHI_cs)), N));
// Calculate majority carrier capacitances
double C_be2 = Tf G_m;
// Calculate total base-emitter Capacitance
double C_be = C_bel + C_be2;
//Calculate Currents
double Iin_max_ac = Vin_max_ac G_pi;
double I_t_max_ac = Vin_max_ac G_m;
// Calculate admittance of back half of BJT model
double Yt_r = G_o + (1 / R_cc);
double Yt_i = 2 M_PI f C_cs;
complex Yt(Yt_r, Yt_i);
// Calculate Peak AC Voltage and Curent Output
complex Vout_max_ac = I_t_max_ac / Yt;
double Iout_max_ac = Vout_max_ac.real() / R_cc;
// Calculate voltage gain ac
AnsiString V_gain_str;
double V_gain_ac = Vout_max_ac.real() / Vin_max_ac;
V_gain_str.printf("%.31f", V_gain_ac);
MainForm->ac_gain->Text = V_gain_str;
// Construct Vout text output
AnsiString V_out_str;
V_out_str.printf("%.31f %.61fsin(2*pi*%.Olf)", V_ce,
Vout_max_ac.real() f);
MainForm->V_out->Text = V_out_str;
// Calculate phase shift on Voltage
29


AnsiString phase_shift_str;
double phase_shift = atan( (180/M_PI) * (Vout_max_ac.imag() /
Vout_raax_ac.real()));
phase_shift_str.printf("%.61f", phase_shi ft);
MainForm->phase->Text = phase_shift_str;
The graphic output is the last of the major steps in the simulation. The
following code has been trimmed to display the basic programming structure.
Please refer to the full code source in Appendix A. First the period of the input
signal is determined. Once this is completed a mapping of the width of the
graphing form to five periods of the input signal is done. A step size in pixels
is produced as well as the seconds per pixel. Construction of a for loop that
will compute the time dependent voltage output. The for loop initiates the
x-coordinate to zero. The for loop has an exit condition of x coordinate
greater than or equal to the graph form width. The for loop also increments
the value of the time variable every pass through the loop. Inside of the
graphing loop the voltage out is computed for the specific instant in time.
Then a mapping between the voltage and the graph form height is done to
establish the y coordinate. Now that both the x and y coordinates have been
established for the graph form a line can be drawn [8], The line is drawn from
the previous point the current point. At this point the major steps of the
simulator have been completed.
//---------------------------------------------------------
// Calculate the period and the step size for the graph
//---------------------------------------------------------
double period = 1 / f; // seconds per cycle
const int numPeriods = 5;
const double stepSize = numPeriods period / xExtent;
const double timePerPixel = numPeriods period xExtent;
// seconds per pixel
double time;
int x, y; // (x,y) coordinate system
//--------------------------------
// Plotting Loop.
// Iterate through time (X-axis)
//--------------------------------
for ( x = 0, time = 0; x < xExtent; x++, time += timePerPixel )
{
// Calculate time dependant Current and Volyage.
Vout ac = Vout max ac.real () * sin(2 M PI f *time);
30


// Assign time for this iteration
time = x stepSize;
// Map voltage Vc to pixels
y = lmap( Vout_ac.real(), -1, 1,
// Plot Vc over time
if ( x == 0 ){
Canvas->PenPos = TPoint( x
}
Canvas->LineTo( x, y );
}
//
0, yExtent )
y ) ;
31


8. Simulator Results
This chapter focuses on the use of the simulator. The circuit simulated
is shown above in Figure 7.1. In the simulator adjustment of the area of the
collector- substrate junction and the frequency of the circuit is allowed.
Adjusting the size of the base-collector junction is a non-factor in this
schematic. The base-collector junction size is a non-factor for capacitance due
to the base bias circuit. The base bias circuit places an ideal voltage source in
parallel to CBe, which is in parallel with gn. The voltage on gn will always be
Vin. The filtering of the signal occurs on the back half of the schematic. The
back half of the schematic is a voltage dependant current source in parallel to
go, CCs, and the 3KQ resistor. The current divider rule is used to determine
the amount of signal attenuation [10].
All analysis is done with the simulator explained in Chapter 6 and
listed in Appendix A. The two scenarios will analyze a small collector-
substrate junction at high frequency (Chapter 8.1), and a large collector-
substrate junction at high frequency (Chapter 8.2).
8.1 Small Collector-Substrate Junction at High Frequency
In this scenario the simulation of the circuit in Figure 7.1 is done with
the modified high frequency model defined in Chapter 6. The simulation is
done with simulator discussed in Chapter 7 and listed in Appendix A. The
parameters of this scenario include a small collector substrate junction. This
scenario is used to set a baseline. The results of this scenario will be
compared with those of scenario 8.2. The scenario parameters chosen are
listed below in Table 8.1.
Ccs 25.7pF
Frequency 120KHz & 250KHz
Table 8.1: Scenario 1 Parameters
32


The simulator only accepts lambda squared as an input. It is from this
that Ccs is calculated. Solution for ACs must be done in the following
equation from Table 6.4 CCs = CCso(Acs)(l-(Vcc/ Acs* Vcc, (Pcs* K and n are listed in Table 6.2. The result gives ACs in
micron A quick conversion to X is required for input into the simulator.
The resulting ACs is listed in Table 8.2.
First the results with a frequency of 120KHz are computed. Notice that
the AC gain just above 200 is an average gain. Take into account the
frequency of 120 KHz, and this is an above average gain for a BJT. Also a
small phase shift is recorded of less than 1.5 degrees.
Vin 0.003sin(27tft)
Frequency 120 KHz
Abe 40 X2
Acs 4,618.9 X1
Table 8.2: Scenario 1 at 120KHz Simulator Input Parameters
AC Voltage gain 216.449
Vout phase angle -1.271452 Degrees
Vqut 4.420 0.649348sin(2*7r* 120000*t) Volts
Table 8.3: Scenario 1 at 120KHz Simulator Results
33


I ftfl.lJyw
Input
''*> JCl003*n|?Dtr) **
Frequency |l2COOO H#rtr
Aieab-e 140 tawtida irfitd
Aneat-s 14618 9 kawbda rtfaawsd
Hf3f3
Anafcae
Output
ACVetoge He 143
Sean '
Voupnaw |-i 271452
angle *
Otgaan
V<** jl 420 0643348rVt 200001
[|An% Reitit
IVt#
A A A 4 '
/ 1 \ ; 1 \ j s 1 i ' { t 1 \ / / j
\ t i \ \ i ] } 1 j S 1 f i r
i i ? 1 1 /
\! 1 1
\ / \ /
-1 Vo v* Ttae-?
Figure 8.1: Simulator Screen Shot of Scenario 1 at 120KHz.
34


Second, the results with a frequency of 250KHz are computed. Notice
that the attenuation of the AC gain is less than 1% of the gain at 120KHz.
The phase shift increases 10.7%, yet still remains less than two degrees.
Vin 0.003sin(27tft)
Frequency 250 KHz
Abe 40 X1
Acs 4,618.9 X2
Table 8.4: Scenario 1 at 250KHz Simulator Input Parameters
AC Voltage gain 214.169
V0ut phase angle -1.423729 Degrees
Vqut 4.420 0.642506sin(2*7t* 120000*t) Volts
Table 8.5: Scenario 1 at 250KHz Simulator Results
WT A******
Par*ne*fs
Input
^ |0.003sn(?"pfVt) ^
Freojency jaflOOC Hotr
Aioob-e |4g Saerfedo xquecetf
A^nsc-s fi^T89----------------- imtaAn tt***e
Output
ACVolege 1^141SS
Gin 1
Voutptwi* It 423723
Angle 1
Degrees
lf.,Ana1ptt* Result*
IVo*
/ \ / ( \ \ / \ / \ t i
/ l l \ t j > t 1 \ ; < > t t J i i \ I i ) f i j ? i / \ i \ \ I i r t l. t' i i i / i 1 s ) \ / 1 i f i
\ \ \ 1V* i \ y i \ >- fme
Figure 8.2: Simulator Screen Shot of Scenario 1 at 250KHz.
35


8.2 Large Collector-Substrate Junction at High Frequency
This scenario includes the same input parameters as scenario 8.1 except
for CCs- CCs is a factor of ten greater than the CCs used of the scenario 1
above. Acs and CCs are directly proportional. Thus Acs is a factor of ten
greater than the ACs of scenario 1.
Ccs 257pF
Frequency 120KHz & 250KHz
Table 8.6: Scenario 2 Parameters
First the results with a frequency of 120KHz are computed. The AC
gain of 164.522 is less than both of the AC gains listed in scenario 1 by 50.
The phase shift increases by 0.1 degrees to -1.539945.
vin 0.003sin(2;rft)
Frequency 120 KHz
Abe 40 Ir
Acs 46,189
Table 8.7: Scenario 2 at 120KHz Simulator Input Parameters
AC Voltage gain 164.522
V0ut phase angle -1.539945 Degrees
VoUT 4.420 0.493565sin(2*7t*120000*t) Volts
Table 8.8: Scenario 2 at 120KHz Simulator Results
36


Parameters Input
Vfi jaocort?prni v#
Fretjjency J12000D Hot;
Aieb*e po
Aleac-t p_ taribdneyjaHMj

Output
ACVqMgr 1164.522
: Gri '
Vtul(* ] t 539045
Results
tVc*
Oegfes
^ |l 420 0 4S3965wl?p*12O0CW ^
time ->
Figure 8.3: Simulator Screen Shot of Scenario 2 at 120KHz.
Second, the results with a frequency of 250KHz are computed. The
AC gain has been attenuated to 90. This is a 45% decrease from 120KHz.
The phase shift has stabilized to -1.55 degrees.
vin 0.003sin(27rft)
Frequency 250 KHz
Abe 40 l1
Acs 46,189 X1
Table 8.9: Scenario 2 at 250KHz Simulator Input Parameters
AC Voltage gain 90.923
V0ut phase angle -1.555984 Degrees
Vqut 4.420 0.272770sin(2*jc*120000*t) Volts
Table 8.10: Scenario 2 at 250KHz Simulator Results
37


I MSB
Input
}0003*ni2-prf-|} **
riSMney 1253000
A A Hoi*
aotula squaeetl
tambdqud
Ana^
Output
ACVo*gc j 30 323
bam *
Wutffrj:* j 1 55598*
angle *
Vcvl
Oegreei
{4420 ft 2<7770sin(2pi*250000)
HjAih^w Rcu*U I
tVtfl
x \ i \ f \ / / \ A
t \ / , \ ; } \ / \ \ \ \ f
\ / * / l- J \J \_
-1Vs*
Figure 8.4: Simulator Screen Shot of Scenario 2 at 250KHz.
It is noticed that the area of the collector-substrate junction drastically
affects the AC Voltage gain. The AC voltage gain is inversely proportional to
Acs- This is also true for the relationship between AC voltage gain and ACs-
Phase angle is minimally affected. All of the results produced phase angles
less than -1.6 degrees.
38


9. Comparison with Pspice
This chapter focuses on the results of this circuit simulated in Chapter
8. Pspice is the standard in electrical circuit simulations. In chapter 7 a
simulator was created. In chapter 8 data was gathered from the simulator.
Accuracy of the simulator is tested in this chapter. Pspice transient analysis is
performed on the circuits of Figure 9.1 and Figure 9.2. This analysis plots
2000 points over the 200Hz to 800KHz frequency range. The graphs define
the BJT model output voltage at a frequency. Results from the comparison are
listed in Table 9.1.
Ccs Frequency Pspice Vout Simulator Vout
25.7pF 120KHz 650mV 649mV
25.7pF 250KHz 647mV 642mV
257pF 120KHz 562mV 493 mV
257pF 250KHz 425mV 272mV
Table 9.1: Comparison of Pspice and Simulator Results.
The Pspice comparison with the results from scenario 1 (Chapter 8.2)
is favorable. A maximum of a 5 mV difference is seen with CCs = 25.7 pF.
The voltage difference between Pspice and the simulator is increasing with
frequency. There is only a lmV difference at 120KHz. This voltage
difference increases 5 times at 250KHz. Thus, the simulator constructed in
Chapter 7 is accurate over these frequencies with small collector-substrate
capacitances.
There are large discrepancies in Pspice and the constructed simulator
voltage output. The trend noticed in scenario 1 is present in scenario 2 as
well. The voltage differences between the simulator and Pspice increase with
frequency. Yet, there is another parameter driving this discrepancy between
the simulator and Pspice. The collector-substrate capacitance is ten times the
value in scenario 1. Ccs is creating larger discrepancies in the output voltage
than the frequency is. The maximum voltage difference has grown to 153mV
39


Again, just like scenario 1 this maximum voltage discrepancy was at 250KHz.
The Constructed simulator is not accurate at high frequencies with large
collector-substrate capacitances.
The error in the simulation is introduced in the filtering elements of the
circuit. The elements involved in the filtering of the output are: Ccs, Rco and
Go- The gain circuit is can be disregarded as the error producer. At low
frequencies with low capacitances Vout was nearly identical. Pspice should
be used instead of the simulator for high frequency, and large capacitance (CCs
> 25.7pF) simulations.
40


*,* ~mt mt
a>IU; at alW-M ^I^WU viTlQIS^l 1G ...............................3 Stet Om^~3 flit MlH*
My Modl
Allow uur to modify:
Cct and Cba
Figure 9.1: Pspice Simulation of Scenario 1.
41


* t* Umw g*tp $* If*** itx* m-iw £*ow g*
*mm *iii>.i i -i.............................................l mm vim-
My Model
Mow usor to modify:
Cc* and Cbo
Figure 9.2: Pspice Simulation of Scenario 2.
42


10. Conclusions
The BJT is a multimode device. The BJT has three distinct models that
must be used in its analysis. The DC model defines the bias voltages of the
junctions. These junction voltages define whether the BJT is operating in the
Saturation, Cutoff, Forward Active or Reverse active modes. The small signal
AC model defines the resistive properties of the BJT. Input impedance, output
impedance and AC current gain are defined in the small signal model. The
High frequency AC model defines the reactance in the BJT. Parasitic
Capacitances of the pn junction are voltage and frequency dependant.
Majority charge accumulation of the pn junction occurs on the base-emitter
junction.
A BJT must be constructed to a particular technology. The process
technology is the minimal size to which the set of machines can construct
devices on a substrate. The process used in this thesis was the 2.5-micron
technology. The technology defines the number of layers that are available.
An example of these layers the designer would use is metal 1, metal 2, n, n+,
n-, p, p+, p-, and substrate type. The process technology defines the length,
width, overlap, and depth of these layers. The process also defines the
impedance and reactance between the layers.
The BJT junctions affect the signal output. The pn junctions create
capacitance. The majority of the BJT capacitances are the pn junction
parasitic capacitances. These capacitances have more to do with attenuation
of the signal than with the phase shift of the signal. AC voltage gain decreases
at 12 to 1 ratio versus phase angle. Even some of the largest pn junctions
create a very small phase shift.
A Simulator must take a host of concepts into play. What is the target
platform? In this thesis Windows 9x PCs was chosen. What language should
be used? Borland C++ builder is used in this thesis. It is based on the
standard application language C++. A large amount of documentation is
available on the language and the Development Environment. It allows for an
Object Oriented design.
43


How will the information be delivered? From a User interface perspective the
simulator should deliver the information as quickly and easily as possible.
The user must know what is expected for input and what will be returned as
output. Once these questions have been answered, the coding technique
comes into play.
Good coding techniques will allow for the programmer to take
advantage of a good design [9], People should approach programming with
the mindset that the audience is greater than the author. More than one
individual will write and maintain all of the code. Code reuse, ease of
maintenance, and ease of understanding all relate. For if program code is
broken down into generic functional areas that are well commented, reuse,
ease of maintenance, and understanding are built in.
A simulator should be valid over a large range of frequencies and other
input parameters. Pspice should always be used a benchmark for all hand
calculations, models, and simulations.
This thesis outlines the engineering round trip. One: this paper delivers
the information necessary for the reader to understand the physics behind the
packaging of a BJT. The equations, and models for BJT analysis have been
discussed. Two: the definition of a new model by the engineer. Many times a
combination of the low fidelity and high fidelity models are used to formulate
hypothesis, and lend direction to the engineer. Three: the construction of a
computer simulator. The computer simulator can be used as a means to
quickly test a hypothesis over an over. It can be used as a means to deliver
information to colleagues. A computer simulator allows for easy model
refinement. Four: the verification of the simulator must occur. Pspice is the
industry standard.
44


Appendix
A. BJT Simulator Source Code
//----------------------------------------
// File: Main.h
//----------------------------------------
//----------------------------------------
ifndef MainH
#define MainH
//----------------------------------------
#include
#include
#include
#include
include
include
include
include
//----------------------------------------
class TMainForm : public TForm
{
__published: // IDE-managed Components
TStatusBar *StatusBarl;
TMainMenu *MainMenul;
TMenuItem *Filel;
TMenuItem *ImportVariablesl;
TMenuItem *ExportVariablesl;
TMenuItem *N1;
TMenuItem *SaveResultsl;
TMenuItem *N2;
TMenuItem *Exitl;
TMenuItem *Helpl;
TMenuItem *Aboutl;
TGroupBox *GroupBoxl;
TImage *Imagel;
TMenuItem *Analyzel;
TLabel *Label7;
TLabel *Label9;
TEdit f;
TEdit *V;
TButton *Buttonl;
TEdit *Abe;
TLabel *Labell;
TEdit *Acs;
45


TLabel *Label2;
TLabel *Label3;
TLabel *Label4;
TPanel *Panel1;
TPanel *Panel2;
TLabel *Labe15;
TLabel *Label6;
TEdit *ac gain;
TEdit *phase;
TLabel *Label8;
TEdit *V out;
TLabel *LabellO,
TLabel *Labelll,
TLabel *Labell2
TLabel *Labell3
TLabel *Labell5
TLabel *Labell6
void _ fastcall ImportVariableslClick(TObject *Sender);
void fastcall ExportVariableslClick(TObject *Sender);
void fastcall SaveResultslClick(TObject *Sender);
void fastcall ExitlClick(TObject *Sender);
void _ fastcall AboutlClick(TObject *Sender);
void fastcall OnCreate(TObject *Sender);
void fastcall AnalyzelClick(TObject *Sender);
void fastcall CbeOChange(TObject *Sender);
void fastcall ButtonlClick(TObject *Sender);
private: // User declarations
double ___fastcall StringToDouble( AnsiString& s );
public: // User declarations
___fastcall TMainForm(TComponent* Owner);
void ___fastcall DisplayHint(TObject Sender);
double Getf( void )
{ return StringToDouble(f->Text); )
double GetAbe( void )
{ return StringToDouble(Abe->Text); }
double GetAcs( void )
{ return StringToDouble(Acs->Text); }
};
//-----------------------------------------------------
extern PACKAGE TMainForm *MainForm;
//-----------------------------------------------------
#endif
46


//---------------------------------------------
// File: Graph.h
//---------------------------------------------
//---------------------------------------------
#ifndef GraphH
#define GraphH
//---------------------------------------------
#include
#include
include
include
include
//---------------------------------------------
class TGraphBox : public TForm
f
__published: // IDE-managed Components
TPaintBox *PaintBoxl;
TLabel *Labell;
TLabel *Label2;
TLabel *Label3;
void __fastcall OnPaint(TObject *Sender);
private: // User declarations
public: // User declarations
__fastcall TGraphBox(TComponent* Owner);
void __fastcall Init( void ) ;
} ;
//---------------------------------------------
extern PACKAGE TGraphBox *GraphBox;
//---------------------------------------------
endif
47


//--------------
// File: About.h
//--------------
//---------------------------
#ifndef AboutH
define AboutH
//---------------------------
include
include
include
include
include
include
include
include
include
include
//---------------------------
class TAboutBox : public TForm
{
__published:
TPanel *Panell;
TImage *ProgramIcon;
TLabel *ProductName;
TLabel *Version;
TLabel *Copyright;
TLabel *Comments;
TButton *OKButton;
TLabel *Labell;
TLabel *Label2;
private:
public:
virtual ___fastcall TAboutBox(TComponent*
};
//--------------------------------------------
extern PACKAGE TAboutBox *AboutBox;
//-----------------------------------
endif
AOwner);
48


//----------------
// File: Main.cpp
//---------------
//-----------------------------------------------------------------
// Bipolar Junction Transistor Analyzer
// Copyright (C) 2001 by Jason Luzietti
//-----------------------------------------------------------------
#include
#include // sscanf()
pragma hdrstop
include "Main.h"
include "About.h"
include "Graph.h"
//-----------------------------------------------------------------
pragma package(smart_init)
pragma resource "*.dfm"
TMainForm *MainForm;
//-----------------------------------------------------------------
// StringToDouble utility function
//
double __fastcall TMainForm::StringToDouble( AnsiString& s )
{
double d = 0;
sscanf( s.c_str(), "%lf", &d );
return d;
}
//-----------------------------------------------------------------
__fastcall TMainForm::TMainForm(TComponent* Owner)
: TForm(Owner)
{
)
//-----------------------------------------------------------------
// OnCreate event handler
void __fastcall TMainForm::OnCreate(TObject *Sender)
{
// Set app's OnHint handler
Application->OnHint = DisplayHint;
}
//-----------------------------------------------------------------
// The application's OnHint handler
void __fastcall TMainForm::DisplayHint(TObject Sender)
{
// Display hint text on status bar
StatusBarl->SimpleText = GetLongHint( Application->Hint ) ;
}
//-----------------------------------------------------------------
// OnClick Event Handler for "File | Import Variables..."
void __fastcall TMainForm::ImportVariableslClick(TObject *Sender)
49


{
::MessageBox( Handle, "Not yet implemented", "TODO",
MB_OK|MB_TASKMODAL|MB_ICONEXCLAMATION );
}
//-----------------------------------------------------------------
// OnClick Event Handler for "File I Export Variables..."
void __fastcall TMainForm::ExportVariableslClick(TObject *Sender)
{
::MessageBox( Handle, "Not yet implemented", "TODO",
MB_OK|MB_TAS KMODAL|MB_ICONEXCLAMATION );
}
//-----------------------------------------------------------------
// OnClick Event Handler for "File | Analyze..."
void __fastcall TMainForm::AnalyzelClick(TObject *Sender)
{
//::MessageBox( Handle, "Not yet implemented", "TODO",
MB_OK|MB_TAS KMODAL|MB_ICONEXCLAMATION );
GraphBox->ShowModal();
}
//-----------------------------------------------------------------
// OnClick Event Handler for "File | Save Results..."
void __fastcall TMainForm::SaveResultslClick(TObject *Sender)
{
::MessageBox( Handle, "Not yet implemented", "TODO",
MB_OK|MB_TASKMODAL|MB_ICONEXCLAMATION );
}
//-----------------------------------------------------------------
// OnClick Event Handler for "File | Exit"
void __fastcall TMainForm::ExitlClick(TObject *Sender)
{
Application->Terminate();
}
//-----------------------------------------------------------------
// OnClick Event Handler for "Help I About..."
void ___fastcall TMainForm::AboutlClick(TObject *Sender)
{
AboutBox->ShowModal();
}
void __fastcall TMainForm::CbeOChange(TObject *Sender)
{
double val;
}
//
void
{
fastcall
TMainForm::ButtonlClick(TObject
GraphBox->ShowModal();
}
//-------------------------
*Sender)
50


//-----------------
// File: Graph.cpp
//-----------------
//---------------------------------------
// Bipolar Junction Transistor Analyzer
// Copyright (C) 2001 by Jason Luzietti
//---------------------------------------
include
include
include
// pow(), M_PI
// C++ complex number template class
include
include
include "Graph.h"
include "Main.h"
pragma hdrstop
// need access to MainForm object
//--------------------------
pragma package(smart_init)
pragma resource "*.dfm"
TGraphBox *GraphBox;
//--------------------------
// Constant High Frequency Substrate level BJT model parameters
//---------------------------------------------------------------
const double Lambda = 2.5; // microns
const double PHI be - 0.7; // Volts
const double PHI_cs = 80; // Volts
const double V ee - 0; // Volts
const double V cc = 10; // Volts
const double V sub = 0; // Volts
const double V be = 0.7; // Volts
const double Bf dc = 100; // no unit
const double R_bb = 500000; // Ohms
const double R cc = 3000; // Ohms
const double per micron~2 C beO = 0.062 * pow(10, -15); //Farad
const double per micron~2 C csO = 0.780 * pow(10, -15); //Farad
const double Tf = 0.1 * pow(10, -9); // seconds
const double coefficient N = 0.99; // emission
51


const double Vt = 0.025;
const double Vaf = 200;
const double Vin max ac = 0.003;
// Volts
// Volts
// Volts
//---------------------------------------------------------------------
// GraphBox constructor
//---------------------------------------------------------------------
__fastcall TGraphBox;:TGraphBox(TComponent* Owner)
: TForm(Owner)
{
}
//---------------------------------------------------------------------
// GraphBox Init method
//---------------------------------------------------------------------
void __fastcall Init( void )
{
//. .
)
//---------------------------------------------------------------------
// Linearly map value x in range xlow to xhigh into y in range ylow
to yhigh
//---------------------------------------------------------------------
inline int lmap( double x, double xlow, double xhigh, int ylow, int
yhigh )
{
return (yhigh ylow) (x xlow) / (xhigh xlow);
}
//---------------------------------------------------------------------
// PaintBoxl's OnPaint Event Handler Draw the graph
//---------------------------------------------------------------------
void __fastcall TGraphBox::OnPaint(TObject *Sender)
{
int oldMapMode;
SIZE oldViewportExt, oldWindowExt;
POINT oldViewportOrg;
const int xExtent = ClientWidth; //ClientWidth; // Max
value for X-axis
const int yExtent = ClientHeight; // Max value for Y-axis
//----------------------------------------------------------------
// Setup Windows plotting for Cartesian coordinate system
//----------------------------------------------------------------
oldMapMode = GetMapMode( Canvas->Handle );
SetMapMode( Canvas->Handle, MM_ANISOTROPIC );
SetWindowExtEx( Canvas->Handle, xExtent, yExtent, SoldWindowExt
) ;
52


SetViewportExtEx( Canvas->Handle, ClientWidth, -ClientHeight,
&oldViewportExt );
SetViewportOrgEx( Canvas->Handle, 0, ClientHeight,
SoldViewportOrg );
// Set plotting color
Canvas->Pen->Color = clRed;
// Retreive user-defined variables
double f = MainForm->Getf(); // Hertz
double A_be = MainForm->GetAbe(); // lambda
double A_cs = MainForm->GetAcs(); // lambda
// Tranform Junction Areas from Lambda/'2 into MicronA2
A_be = A_be pow(Lambda, 2);
A_cs = A_cs pow(Lambda, 2);
//----------------------------------
// BJT model parameters
//----------------------------------
//----------------------------------
// DC model parameters
//----------------------------------
double I_bq = (V_cc V_be) / R_bb;
double I_cq = Bf_dc I_bq;
double V_ce = V_cc (R_cc I_cq);
double V be = V be V ce;
//-----------------------------------------------------------------
// AC model parameters
//-----------------------------------------------------------------
// Calculate G parameters
double G_m = I_cq/Vt;
double G_pi G_m/Bf_dc;
double G_o = I_cq/Vaf;
// Calculate parasitic capacitances
double C_bel = pow(2, N) C_be0 A_be (2 N (V_be /
PHI_be) + (1 N) ) ;
double C_cs = C_cs0 A_cs (1 /pow((l (V_cc / PHI_cs)), N));
// Calculate majority carrier capacitances
double C_be2 = Tf G_m;
// Calculate total base-emitter Capacitance
53


double C_be = C_bel + C_be2;
//Calculate Currents
double Iin_max_ac = Vin_max_ac G_pi;
double I_t_max_ac = Vin_max_ac G_m;
// Calculate admittance of back half of BJT model
double Yt_r = G_o + (1 / R_cc);
double Yt_i = 2 M_PI f C_cs;
complex Yt(Yt_r, Yt_i);
// Calculate Peak AC Voltage and Curent Output
complex Vout_max_ac = I_t_max_ac / Yt;
double Iout_max_ac = Vout_max_ac.real() / R_cc;
// Calculate voltage gain ac
AnsiString V_gain_str;
double V_gain_ac = Vout_max_ac.real() / Vin_max_ac;
V_gain_str.printf("%.31f", V_gain_ac);
MainForm->ac_gain->Text = V_gain_str;
// Construct Vout text output
AnsiString V_out_str;
V_out_str.printf("%.31f %.61fsin(2*pi*%.Olf)", V_ce,
Vout_max_ac.real(), f);
MainForm->V_out->Text = V_out_str;
// Calculate phase shift on Voltage
AnsiString phase_shift_str;
double phase_shift = atan( (180/M_PI) (Vout_max_ac.imag() /
Vout_max_ac.real()));
phase_shift_str.printf("%.61f", phase_shift);
MainForm->phase->Text = phase_shift_str;
// Time dependant Current and Voltage
complex I_t_ac;
complex Vout_ac;
//--------------------------------------------------------
// Calculate the period and the step size for the graph
//--------------------------------------------------------
double period = 1 / f; // seconds per cycle
const int numPeriods = 5;
const double stepSize = numPeriods period / xExtent;
const double timePerPixel = numPeriods period xExtent; //
second per pixel
double time;
int x,y; // (x,y) coordinate system
54


ofstream log( "log.txt", ios_base::trunc );
log << "-----------bjt log file-------------\n";
log << "xExtent = << xExtent << endl;
log << "yExtent = << yExtent << endl;
log << "period = << period << endl;
log << "numPeriods period = << numPeriods << << period
<< = << numPeriods period << endl;
//--------------------------------
// Plotting Loop.
// Iterate through time (X-axis)
//--------------------------------
for ( x = 0, time =0; x < xExtent; x++, time += timePerPixel )
{
// Calculate time dependant Current and Volyage.
Vout_ac = Vout_max_ac.real() sin(2 M_PI f *time);
// Log stuff
log << "time = << time << endl;
log << "Vout_ac = << Vout_ac.real() << endl;
// Assign time for this iteration
time = x stepSize;
// Map voltage Vc to pixels
y = lmap( Vout_ac.real(), -1, 1, 0, yExtent );
// Plot Vc over time
if ( x == 0 ){
Canvas->PenPos = TPoint( x, y );
)
Canvas->LineTo( x, y );
)
//----------------------------------------------------
// Restore old Windows plotting system
//----------------------------------------------------
SetMapMode( Canvas->Handle, oldMapMode );
SetWindowExtEx( Canvas->Handle, oldWindowExt.cx,
oldWindowExt.cy, NULL );
SetViewportExtEx( Canvas->Handle, oldViewportExt.cx,
oldViewportExt.cy, NULL );
SetViewportOrgEx( Canvas->Handle, oldViewportOrg.x,
oldViewportOrg.y, NULL );
}
//---------------------------------------------------------
55


//-----------------
// File: About.cpp
//----------------
//----------------------------------------------------
// Bipolar Junction Transistor Analyzer
// Copyright (C) 2001 by Jason Luzietti
//----------------------------------------------------
#include
pragma hdrstop
#include "About.h"
//----------------------------------------------------
pragma resource "*.dfm"
TAboutBox *AboutBox;
//----------------------------------------------------
__fastcall TAboutBox::TAboutBox(TComponent* AOwner)
: TForm(AOwner)
{
}
//----------------------------------------------------
56


B. Pspice Netlist of Modified High Frequency Model
** 10/06/01 15:19:19 *** Evaluation PSpice (Nov 1999) **
* C:\Program Files\OrCAD_Demo\PSpice\Test\my_model.sch *
* CIRCUIT DESCRIPTION
* Schematics Version 9.1 Web Update 1
* Sat Oct 06 15:19:15 2001
** Analysis setup **
.OP
* From [PSPICE NETLIST] section of pspiceev.ini:
.lib "nom.lib"
.INC "my_model.net"
**** INCLUDING my_model.net ****
* Schematics Netlist *
R R1 0 $N 0001 500k
C_C1 0 $N_ "oooi 7.4pf
C_C2 0 $N_0001 170.4pf
C_C5 0 $N_0002 257.4pf
R R3 0 $N 0002 3k
G G2 $N 0002 0 $N 0001 0 0.0744
R_R2 0 $N 0001 1344
V_V4 $N_0001 0 DC 0
+ SIN 0V 3mV 10kHz 000
R_R6 0 $N_0002 107526
+ RESUMING my_model. cir * *
. INC "my model.als"
INCLUDING my model .als * *
* Schematics Aliases *
.ALIASES
R_R1 R1(1=0 2=$N 0001 )
C Cl Cl(1=0 2=$N 0001 )
C C2 C2(1=0 2=$N 0001 )
C C5 C5(1=0 2=$N 0002 )
R R3 R3(1=0 2=$N 0002 )
G G2 G2(3=$N 1 o o o M| i£s II o 1=$N 0001
R R2 R2(1=0 2=$N 0001 )
57


V_V4 R R6 .ENDALIASES V4(+=$N 0001 -=0 ) R6 (1=0 2=$N_0002 )
**** RESUMING my_model.cir ***+
.probe .END ** 10/06/01 15:19:19 *** Evaluation PSpice (Nov 1999) **
* C:\Program Files\OrCAD_Demo\PSpice\Test\my_model.sch *
* SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.000 DEG C
NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE
VOLTAGE
($N_0001) 0.0000 ($N_0002) 0.0000
VOLTAGE NAME SOURCE CURRENTS CURRENT
> > 0.000E+00
TOTAL POWER DISSIPATION 0.00E+00 WATTS
** 10/06/01 15:19:19 *** Evaluation PSpice (Nov 1999) **
* C:\Program Files\OrCAD_Demo\PSpice\Test\my_model.sch *
* OPERATING POINT INFORMATION TEMPERATURE = 27.000 DEG C
**** VOLTAGE-CONTROLLED CURRENT SOURCES
NAME I-SOURCE G_G2 0.000E+00
JOB CONCLUDED
TOTAL JOB TIME .10
58


References
[1] Geiger, Randall L.; Allen, Phillip E.; Stradler, Noel R. VLSI Design
Techniques for Analog and Digital Circuits, McGraw-Hill, 1990.
[2] Wolf, Wayne Modern VLSI Design A Systems Approach, Prentice Hall,
1994.
[3] Floyd, Thomas L. Electronic Devices 3rd Ed., Merrill, 1992.
[4] Sedra, Adel S.; Smith, Kenneth C. Microelectronic Circuits. 4th Ed.,
Oxford University Press, 1998.
[5] Soclof, Sydney Design and Application of Analog Integrated Circuits,
Prentice Hall, 1991.
[6] Calvert, Charlie Borland C+ + Builder 3 Unleashed, SAMS, 1998.
[7] Reisdorph, Kent Teach Yourself Borland C++ Builder 4 in 24 hours,
SAMS, 1999.
[8] Petzold, Charles; Yao, Paul Programming Windows 95, Microsoft Press,
1996.
[9] Lakos, John Large-Scale C+ + Software Design, Addison Wesley, 1996.
[10] Bogart, Theodore F. Jr. Electric Circuits, 2nd Ed., Glencoe, 1992.
59