Citation
Design and analysis of high-speed clock circuits

Material Information

Title:
Design and analysis of high-speed clock circuits
Creator:
McDonnell, Michael John
Publication Date:
Language:
English
Physical Description:
67 leaves : ; 28 cm

Thesis/Dissertation Information

Degree:
Master's ( Master of science)
Degree Grantor:
University of Colorado Denver
Degree Divisions:
Department of Electrical Engineering, CU Denver
Degree Disciplines:
Electrical engineering

Subjects

Subjects / Keywords:
Printed circuits -- Design and construction ( lcsh )
Timing circuits -- Design and construction ( lcsh )
Printed circuits -- Design and construction ( fast )
Timing circuits -- Design and construction ( fast )
Genre:
bibliography ( marcgt )
theses ( marcgt )
non-fiction ( marcgt )

Notes

Bibliography:
Includes bibliographical references (leaves 66-67).
General Note:
Department of Electrical Engineering
Statement of Responsibility:
by Michael John McDonnell.

Record Information

Source Institution:
University of Colorado Denver
Holding Location:
Auraria Library
Rights Management:
All applicable rights reserved by the source institution and holding location.
Resource Identifier:
45211989 ( OCLC )
ocm45211989
Classification:
LD1190.E54 2000m .M36 ( lcc )

Full Text
DESIGN AND ANALYSIS OF
HIGH-SPEED CLOCK CIRCUITS
by
Michael John McDonnell
B.S.E.E., University of Colorado at Denver, 1987
A thesis submitted to the
University of Colorado at Denver
in partial fulfillment
of the requirements for the degree of
Master of Science
Electrical Engineering
2000


Copyright 2000 by Michael John McDonnell
All rights reserved.


This thesis for the Master of Science
degree by
Michael John McDonnell
has been approved
by
Hamid Fardi
Miloje Radenkovic
V//3 (2a
CO
Date


McDonnell, Michael John (M.S., Electrical Engineering)
Design and Analysis of High-Speed Clock Circuits
Thesis directed by Professor Hamid Fardi
ABSTRACT
This thesis describes the design and analysis of high-speed clock circuits
implemented in a printed circuit board. The design requirements of 53 and 106
megahertz (MHz) clock circuits are outlined. Printed circuit board theory is used to
design the layout of the high-speed clock signals. Signal integrity issues such as
impedance matching, proper termination, and transmission line properties of high-
speed signals are examined. The physical properties of the high-speed clock signals
are modeled using simulation software from HyperLynx. This simulator requires
parameters such as dielectric properties of the printed circuit board, distance of the
trace to a reference plane, and the length of traces. A printed circuit board is
fabricated containing these high-speed clock circuits, and real time measurements are
recorded of the clock circuit using a digital oscilloscope. The theoretical equations,
simulation results, and real time measurements are compared and the discrepancies
are discussed.
This abstract accurately represents the content of the candidates thesis. I
recommend its publication. _____________
Signed
Hamid Fardi
IV


DEDICATION
I dedicate this thesis to my wife Patricia, for her unfaltering understanding and
support while I spent numerous weekend and evening hours researching and writing.


ACKNOWLEDGEMENTS
I would like to thank my fellow coworkers and brilliant engineers, Ken Jessop and
Jerry Dallmann, for their patience and assistance in the materialization of this thesis.
I would also like to thank my current employer and the management of McDATA
Corporation. The hardware and software support that was given to me enabled the
fruition and completion of this thesis.
Special thanks to my advisor, Hamid Fardi, for his guidance to keep me on track
and his patience with me during this past year.


CONTENTS
Figures.......................................................................... x
Tables......................................................................... xii
Chapter
1. Introduction................................................................. 1
2. Specification of the High-Speed Clock Circuits............................... 2
2.1 Logic Design of the High-Speed Clock Circuits............................... 6
2.2 Physical Properties of the High-Speed
Clock Circuits............................................................... 9
3. Theoretical Analysis of the High-Speed
Clock Circuits.............................................................. 13
3.1 Transmission Line Theory................................................... 13
3.2 Source Terminated Transmission Lines....................................... 16
3.3 Microstrip Topology Equations.............................................. 19
3.4 Stripline T opology Equations.............................................. 21
3.5 Parameter Calculations for the High-Speed
Clock Circuits.............................................................. 23
3.5.1 Calculations for CLK106_1................................................. 23
3.5.2 Calculations for CLK106_2................................................ 23
3.5.3 Calculations for CLK53 1................................................. 24
vii


3.5.4 Calculations for CLK53_2............................................. 24
4. Simulation of the High-Speed Clock Circuits............................. 26
4.1 Simulation Setup...................................................... 26
4.2 Simulation Results..................................................... 26
4.2.1 CLK106_1 Simulation Results........................................... 27
4.2.2 CLK106_2 Simulation Results........................................... 29
4.2.3 CLK53_1 Simulation Results............................................ 31
4.2.4 CLK53_2 Simulation Results........................................... 33
5. Oscilloscope Measurements of the High-Speed
Clock Circuits.......................................................... 35
5.1 Oscilloscope Setup..................................................... 35
5.2 Oscilloscope Results................................................... 36
6. Analysis of Results..................................................... 51
6.1 Theoretical and Simulation Comparisons.................................. 52
6.2 Theoretical and Oscilloscope Measurement
Comparisons............................................................. 55
6.3 Simulation and Oscilloscope Measurement
Comparisons............................................................. 55
7. Conclusions............................................................. 58
Appendix
A. Matlab Programs......................................................... 61
viii


References
66
IX


FIGURES
Figure
2.1 High-Speed Clock Circuit Specifications........................... 2
2.2 High-Speed Clock Circuit Designs.................................. 6
2.3 Representative Stack Up of PCB................................... 10
2.4 PCB Trace of CLK106_1............................................ 11
2.5 PCB Trace of CLK106_2............................................ 11
2.6 PCB Trace of CLK53_1............................................. 12
2.7 PCB Trace of CLK53_2............................................. 12
4.1 CLK106_1 Simulation Schematic.................................... 27
4.2CLK106_1 Simulation Waveform Results............................. 28
4.3 CLK106_2 Simulation Schematic.................................... 29
4.4 CLK106_2 Simulation Waveform Results............................. 30
4.5 CLK53_1 Simulation Schematic..................................... 31
4.6 CLK53_1 Simulation Waveform Results.............................. 32
4.7 CLK53_2 Simulation Schematic..................................... 33
4.8 CLK53_2 Simulation Waveform Results.............................. 34
5.1 CLK106_1 Source Waveform......................................... 37
5.2 CLK106_1 Load Waveform........................................... 38
5.3 CLK106_2 Source Waveform......................................... 39
x


5.4 CLK106_2 Load Waveform................................. 40
5.5 CLK53_1 Source Waveform................................. 41
5.6 CLK53.1 Load Waveform................................... 42
5.7 CLK53_2 Source Waveform................................. 43
5.8 CLK53_2 Load Waveform................................... 44
5.9 CLK106_1 Trace Delay.................................... 45
5.10 CLK106_2 Trace Delay................................... 46
5.11 CLK106_1 and CLK106_2 Source Skew..................... 47
5.12 CLK53_1 Trace Delay.................................... 48
5.13 CLK53_2 Trace Delay.................................... 49
5.14 CLK53_1 and CLK53_2 Load Skew......................... 50
xi


TABLES
Table
2.1 Input Specifications for LOAD A........................................... 3
2.2 Input Specifications for LOAD B............................................... 4
2.3 Input Specifications for LOAD C............................................... 5
2.4 Input Specifications for LOAD D............................................... 5
2.5 Output Specifications for CLOCK DRIVER A...................................... 7
2.6 Output Specifications for CLOCK DRIVER C...................................... 8
6.1 Theoretical and Simulation Propagation Delay Results......................... 53
6.2: Theoretical and Simulation Inductance Results............................. 54
6.3: Theoretical and Simulation Capacitance Results............................ 54
xii


1. Introduction
In the high technology industry, computer systems increase in speed every year.
In order for these systems to increase in speed, clock frequencies are getting faster
and propagation delays through digital logic gates are getting shorter. To keep up
with the requirements of faster systems, integrated circuit chip vendors are shrinking
their die to make the transistors smaller and faster. As the transistors become smaller,
the time it takes for the transistor to switch between a high logic state and a low logic
state, or vice-versa, is faster. These edge rates were in the 20 nanosecond range in the
1980s and today they can be in the sub-nanosecond range [1]. It is the fast edge rates,
not the fast frequencies, of signals that cause most signal integrity issues [1-3]. Some
examples of these signal integrity issues are overshoot, undershoot, and ringing that
occur when signals switch from one logic state to another.
Clocks in a printed circuit board (PCB) must be clean in terms of signal integrity,
i.e. very small overshoot, undershoot, and ringing. Transmission line effects and
clock skew must be considered when designing digital clock circuits in PCBs. There
are tools available to help design high-speed clock traces. Some of these tools are
theoretical transmission line equations and commercially available design simulators.
These tools are used to predict the parameters and waveforms of high-speed clock
traces before they are fabricated in a PCB. The intent of this paper is to explore the
design of high-speed clock circuits in a PCB. The main objectives are to find the
accuracy of the theoretical equations and the accuracy of the design simulator to
predict the parameters and waveforms of high-speed clock circuits fabricated in a
PCB.
The specifications of the high-speed clock circuits are first outlined in this thesis.
The circuits are then analyzed using circuit design techniques and transmission line
theory. The HyperLynx computer aided design simulator, LineSim, is used to predict
the signal waveforms of these high-speed clock circuits before they are implemented
in a PCB. A digital oscilloscope is used to measure the actual waveforms of these
clock circuits after they are fabricated in a PCB. Finally, the results from the
theoretical transmission line equations, design simulator, and oscilloscope
measurements are compared.
1


2. Specification of the High-Speed Clock Circuits
The specifications of the high-speed clock circuits will be explained in this section
and are shown in Figure 2.1. The clock circuits are contained on one PCB.
Figure 2.1: High-Speed Clock Circuit Specifications
The clocks that will be analyzed in this thesis are two 106.25 MHz clocks and two
53.125 MHz clocks. The 106.25 MHz clocks are named CLK106_1 and CLK106_2
in Figure 2.1. The 53.125 MHz clocks are named CLK53_1 and CLK53_2 in Figure
2.1. These two clock frequencies are generated from the oscillators as shown in
Figure 2.1.
The 106.25 MHz clock oscillator is required to drive two loads. These loads are
named LOAD A and LOAD B in Figure 2.1. The clock signals driving LOAD A and
LOAD B are CLK106_1 and CLK106_2, respectively. The clock skew between
CLK106_1 and CLK106_2 should be less than 1 nanosecond (ns). Clock skew is the
difference in time of the same clock arriving at two different registers or gates [3].
The clock skew requirement in this circuit is placed only on the rising edges, so the
rising edges at LOAD A and LOAD B must be within 1 ns of each other.
2


The 53.125 MHz clock oscillator is also required to drive two loads. As shown in
Figure 2.1, these loads are named LOAD C and LOAD D. The clock signal driving
LOAD C is CLK53_1. The clock signal driving LOAD D is CLK53_2. The clock
skew between CLK53_1 and CLK53_2 should also be less than 1 ns. The clock skew
requirement in this circuit is placed only on the rising edges, so the rising edges at
LOAD C and LOAD D must be within 1 ns.
The integrated circuit (IC) chip used for LOAD A is a serial high-speed backplane
transceiver manufactured by Applied Micro Circuits. This IC chip is in a ball grid
array (BGA) package, and the part number is S2067 [4]. The reference clock input
pin of this chip is driven by CLK106_1. Table 2.1 contains the input specifications
for LOAD A. This load has a-100 minimum, +100 maximum parts per million
(ppm) frequency tolerance, and a 40 percent (%) minimum, 60 % maximum duty
cycle tolerance. A frequency tolerance of 100 ppm means a 0.01 % change in the
period. The maximum cycle to cycle clock jitter is 80 picoseconds (ps) to maintain a
77 % eye opening. The maximum rise and fall time for the reference clock input is 2
ns, measured between the 20 % and 80 % points of the peak voltage. The input
voltage range of this load is from -0.5 volts to 3.47 volts. This load also has a
minimum input high voltage of 2.0 volts and a maximum input low voltage of 0.8
volts. The maximum input high and low currents are 40 microamperes (uA) and 600
uA, respectively. The maximum input capacitance of LOAD A is 3 picofarads (pF).
Table 2.1: Input Specifications for LOAD A
Parameter Minimum Maximum Units
Frequency Tolerance -100 +100 ppm
Duty Cycle 40 60 %
Clock Jitter 80 ps
Rise and Fall Time 2.0 ns
Input Voltage Range -0.5 3.47 Volts
Input High Voltage 2.0 Volts
Input Low Voltage 0.8 Volts
Input High Current 40 uA
Input Low Current 600 uA
Input Capacitance 3.0 pF
3


The IC chip used for LOAD B is a field programmable gate array (FPGA)
manufactured by Xilinx. This IC chip is from Xilinxs Virtex family of FPGAs, is in
a BGA package, and the part number is XCV300 [5]. One of the four global clock
input pins of this chip is driven by CLK106_2. Table 2.2 contains the input
specifications for LOAD B, which is a high frequency global input pin of a Virtex
FPGA. This clock input requires a frequency between 60 and 200 MHz and a
minimum pulse width of 2.0 ns. The clock period tolerance is 1.0 ns and the cycle to
cycle jitter is plus or minus 150 ps. The input voltage range is from -0.5 volts to 5.5
volts. This clock input has a minimum input high voltage of 2.0 volts and a
maximum input low voltage of 0.8 volts. The input leakage current is plus or minus
10 uA. The maximum input capacitance of LOAD B is 8 pF-
Table 2.2: Input Specifications for LOAD B
Parameter Minimum Maximum Units
Clock Frequency 60 200 MHz
Clock Pulse Width 2.0 ns
Clock Period Tolerance 1.0 ns
Clock Jitter, cycle to cycle +/-150 ps
Input Voltage Range -0.5 5.5 Volts
Input High Voltage 2.0 Volts
Input Low Voltage 0.8 Volts
Input Leakage Current +/-10 uA
Input Capacitance 8
The IC chip used for LOAD C is the same FPGA that is used for LOAD B.
However, a different global clock input pin is used and is driven by CLK53_1. Table
2.3 contains the input specifications for LOAD C, which is a low frequency global
input pin of a Virtex FPGA. This clock input requires a frequency range between 25
and 100 MHz and requires a minimum pulse width of 2.5 ns. The clock period can
vary by 1.0 ns, but the cycle to cycle jitter is plus or minus 300 ps. The input voltage
range of this load is from -0.5 volts to 5.5 volts. This clock input has a minimum
input high voltage of 2.0 volts and a maximum input low voltage of 0.8 volts. The
input leakage current is plus or minus 10 uA. The maximum input capacitance of
LOAD C is 8 pF.
4


Table 2.3: Input Specifications for LOAD C
Parameter Minimum Maximum Units
Clock Frequency 25 100 MHz
Clock Pulse Width 2.5 ns
Clock Period Tolerance 1.0 ns
Clock Jitter, cycle to cycle +/-300 ps
Input Voltage Range -0.5 5.5 Volts
Input High Voltage 2.0 Volts
Input Low Voltage 0.8 Volts
Input Leakage Current +/-10 uA
Input Capacitance 8 pF
The IC chip used for LOAD D is an edge-triggered D-type flip-flop manufactured
by Texas Instruments. This IC chip is in a surface mount, thin shrink small-outline
package, and the part number is SN74LVTH374 [6]. The clock input pin of this chip
is driven by CLK53_2. Table 2.4 contains the input specifications for LOAD D,
which is the clock input pin of the SN74LVTH374. This clock input has a maximum
clock frequency of 150 MHz and a minimum pulse width requirement of 3.3 ns. The
maximum rise and fall time is 10 ns per volt. The maximum input voltage of this load
is 5.5 volts. This clock input also has a minimum input high voltage of 2.0 volts and
a maximum input low voltage of 0.8 volts. The leakage current of this load is plus or
minus 1 uA. The maximum input capacitance of LOAD D is 3 pF-
Table 2.4: Input Specifications for LOAD D
Parameter Minimum Maximum Units
Clock Frequency 150 MHz
Clock Pulse Width 3.3 ns
Rise and Fall Time 10 ns/Volt
Input Voltage Range 5.5 Volts
Input High Voltage 2.0 Volts
Input Low Voltage 0.8 Volts
Input Leakage Current +/-1 uA
Input Capacitance 3 pF
5


2.1 Logic Design of the High-Speed Clock Circuits
The logic design of the high-speed clock circuits will be explained in this section
and are shown in Figure 2.2.
Figure 2.2: High-Speed Clock Circuit Designs
To reduce part count and cost, only one clock oscillator is used, as shown in
Figure 2.2. A 106.25 MHz clock oscillator is the source for the circuits requiring this
frequency. For the circuits requiring a 53.125 MHz clock, a 106.25 MHz clock is
divided by 2.
As discussed earlier, CLK106_1 and CLK106_2 have a skew requirement of Ins
between them. To achieve this goal, the chip generating the 106.25 MHz signals
should have minimum skew. Due to this skew requirement and drive capability,
CLK106_1 and CLK106_2 are driven from a clock driver chip and not directly from
6


the 106.25 MHz oscillator. This clock driver is labeled CLOCK DRIVER A in
Figure 2.2. The IC chip selected for CLOCK DRIVER A is a 1-line to 10-line clock
driver chip manufactured by Texas Instruments. This IC chip is in a surface mount,
shrink small outline package, and the part number is CDC319 [7]. This part was
selected because of its low skew between output pins and its drive capability. Table
2.5 contains the output characteristics of CLOCK DRIVER A, which is an output pin
of the CDC319 clock driver. This chip has a maximum pin to pin output skew of 250
ps and a maximum pulse skew of 500 ps, which are within the skew requirements
placed on this, circuit. The CDC319 has a maximum output rise and fall time of 1.3
ns, and a minimim output rise and fall time of 0.5 ns. The maximum high and low
drive currents of this chip are -24 mA and 24 mA, respectively. The minimum output
high voltage is 2.4 volts when the power pins are at 3.135 volts and the output current
is -1 mA. The maximum output low voltage is 0.6 volts when the power pins are at
3.135 volts and the output current is 6 mA. The output capacitance of the CDC319 is
6 pF.
Table 2.5: Output Specifications for CLOCK DRIVER A
Parameter Minimum Maximum Units
Pin-to-Pin Output Skew 250 ps
Output Pulse Skew 500 ps
Output Rise and Fall Time 0.5 1.3 ns
Output High Current -24 mA
Output Low Current 24 mA
Output High Voltage 2.4 Volts
Output Low Voltage 0.6 Volts
Output Capacitance 6
Series terminators are shown in Figure 2.2 for CLK106_1 and CLK106_2. These
terminators are named R1 and R2, and they should also be matched for low skew
purposes. More information about these termination resistors will be discussed later
in this chapter and in chapter 3.
Figure 2.2 shows CLOCK DRIVER A driving CLK106_1, CLK106_2, and a third
106.25 MHz clock named CLK106_3. CLK106_1 and CLK106_2 drive LOAD A
and LOAD B, respectively. CLK106_3 is driven to a divide-by-2 circuit to generate a
53.125 MHz clock, which is named CLK53. The divide-by-2 circuit is contained in a
7


programmable logic device (PLD). Therefore, the PLD is the source of the 53.125
MHz clock.
Due to skew requirements, the PLD can not drive multiple loads. Clock driver
chips are used to fanout the 53.125 MHz clock to drive multiple loads. The clock
driver chip, CLOCK DRIVER B, is driven by CLK53, and CLOCK DRIVER B
generates the 53.125 MHz clock named CLK53_ON. There are other 53.125 MHz
clocks driven by CLOCK DRIVER B. However, these clocks will not be discussed,
so they are not shown in Figure 2.2. The chip selected for CLOCK DRIVER B is the
same as the chip selected for CLOCK DRIVER A, which is a CDC319 chip from
Texas Instruments.
Figure 2.2 shows a clock driver chip, CLOCK DRIVER C, generating CLK53_1
and CLK53_2, and receiving CLK53_ON. The skew requirements placed on
CLK53_1 and CLK53_2 require CLOCK DRIVER C to have low skew between its
output signals. There are other constraints on CLOCK DRIVER C, but they will not
be discussed since they do not influence the operation of CLK53_1 and CLK53_2.
However, one of these constraints requires CLOCK DRIVER C to have a phase
locked loop (PLL). The IC chip selected for CLOCK DRIVER C is a PLL clock
driver from Quality Semiconductor (Quality Semiconductor is now owned by
Integrated Device Technology). This IC chip is in a surface mount, small outline
package, and the part number is QS5LV919 [8]. This part was selected based on its
low skew between output pins, its drive capability, and its on chip PLL. Table 2.6
contains the output characteristics of CLOCK DRIVER C, which is a regular clock
output pin of the QS5LV919 PLL clock driver. The QS5LV919 has a maximum pin
to pin output skew of 300 ps and a cycle-to-cycle jitter of plus or minus 0.15 ns,
Table 2.6: Output Specifications for CLOCK DRIVER C
Parameter Minimum Maximum Units
Pin-to-Pin Output Skew 300 ps
Cycle-to-Cycle Output Jitter -0.15 0.15 ns
Output Rise and Fall Time 0.3 2.0 ns
Output High Current -24 mA
Output Low Current 24 mA
Output High Voltage 2.4 Volts
Output Low Voltage 0.45 Volts
8


which are within the skew requirements placed on this circuit. This chip has a
maximum output rise and fall time of 2.0 ns, and a minimum output rise and fall time
of 0.3 ns. The rise and fall times are measured between 0.8 volts and 2.0 volts. The
maximum high and low drive currents of this chip are -24 mA and 24 mA,
respectively. The minimum output high voltage is 2.4 volts when the power pins are
at 3.0 volts and the output current is -24 mA. The maximum output low voltage is
0.45 volts when the power pins are at 3.0 volts and the output current is 24 mA.
Figure 2.2 shows CLK53_1 driving LOAD C and CLK53_2 driving LOAD D.
Both of these trace lengths should be equal to meet the 1 ns skew requirement.
CLK53_1 and CLK53_2 are series terminated by the resistors named R6 and R7,
respectively. Resistors R6 and R7 should also be matched to meet the 1 ns skew
requirement. More information about these termination resistors will be discussed
later in this chapter and in chapter 3.
The 1 ns skew requirement for CLK106_1 and CLK106_2 will be met when using
the CDC319 clock driver if the traces lengths are equal and R1 and R2 are matched.
The maximum clock skew contributed from the CDC319 chip is 250 ps.
The 1 ns skew requirement for CLK53_1 and CLK53_2 will be met when using
the QS5LV919 clock driver if the trace lengths are equal and R6 and R7 are matched.
The maximum clock skew contributed from the QS5LV919 chip is 300 ps.
All of the clock signals shown in Figure 2.2 are routed point to point and contain
series termination resistors. These resistors are labeled R1 through R7. More
information about series termination will be discussed later in this chapter and in
chapter 3.
2.2 Physical Properties of the High-Speed
Clock Circuits
This section will discuss the physical properties of the high-speed clock circuits in
the fabricated PCB. The clocks that will be discussed are CLK106_1, CLK106_2,
CLK53_1, and CLK53_2. These clocks are shown in Figure 2.2.
A representative stack up of the PCB that the clocks are routed in is shown in
Figure 2.3. Due to proprietary information, the actual stack up of the PCB can not be
shown. The main goal of this stack up is to show the distance between trace and
9


reference planes, the materials used, and the dimensions of the materials. In this
respect, there is no loss of information between the representative stack up and the
actual stack up.
4.0 mils
4.0 mils
4.0 mils
4.0 mils
4.0 mils
4.0 mils
4.0 mils
1, w=7.0 mils, t=1.75 mils 1.50 oz
2, reference, t=1.4 mils, 1.0 oz
3, reference, t=1.4 mils, 1.0 oz
4, w=5.0 mils, t=1.4 mils, 1.0 oz
5, w=5.0 mils, t=1.4 mils, 1.0 oz
6, reference, t=1.4 mils, 1.0 oz
7, reference, t=1.4 mils, 1.0 oz
8, w=7.0 mils, t=1.75 mils 1.50 oz
Figure 2.3: Representative Stack Up of PCB
ESEl ESSl
FR-4 Glass
ftYYYYYYYYYYYYYYYYYYYYYYYY
FR-4 Glass
k\\\\\\\Y\\\\\\\\\Y\\\\\\Y
FR-4 Glass
ESSE ESS
FR-4 Glass
ESS ESS
FR-4 Glass
FR-4 Glass
AYYYYYYYYYYYYYYYYYYYYYYYY
FR-4 Glass
EES ESS
The core material used in this PCB is FR-4 glass. The traces in this PCB are made
of copper. The outer layers, 1 and 8, contain 1.5 ounce copper traces. The inner
layers, 2 through 7, contain 1.0 ounce copper traces or planes. The trace width (w) of
the traces on the outer layers are 7.0 thousandths of an inch (mils) wide and have a
trace thickness (t) of 1.75 mils. The inner layer traces have a trace width of 5.0 mils
and a trace thickness of 1.4 mils. All reference planes, layers 2, 3, 6, and 7, have a
thickness of 1.4 mils. All of the core material layers have a height of 4.0 mils. All of
these dimensions have a tolerance of plus or minus 10 %.
The trace of CLK106_1 is routed as shown in Figure 2.4. From CLOCK DRIVER
A, CLK106_1 is routed on layer 8 for 0.185 inches to the 56.2 ohms resistor. This
10


value of termination resistor was picked by "trial and error." A number of different
resistor values were selected and tested in the lab. The 56.2 ohms resistor was found
to have the best signal integrity for CLK106_1 at LOAD A and for CLK106_2 at
LOAD B. More information about selecting termination resistors will be discussed in
chapter 3. The trace of CLK106_1 is then routed from the resistor on layer 4 for
1.727 inches, and then it is routed on layer 5 for 1.228 inches to LOAD A.
CLOCK
DRIVER
A
0.185
layer: 8
56.2
Ohms ^ 727"
A/-----------
layer: 4
1.228"
layer: 5
LOAD A
Figure 2.4: PCB Trace of CLK106_1
The trace of CLK106_2 is routed as shown in Figure 2.5. From CLOCK DRIVER
A, CLK106_2 is routed on layer 8 for 0.468 inches to the 56.2 ohms resistor. This
value of termination resistor was picked as stated in the previous paragraph. The
trace of CLK106_2 is then routed from the resistor on layer 4 for 2.926 inches to
LOADB.
Figure 2.5: PCB Trace of CLK106_2
The trace of CLK53_1 is routed as shown in Figure 2.6. From CLOCK DRIVER
C, CLK53_1 is routed on layer 5 for 0.626 inches to the 36.5 ohms resistor. This
value of termination resistor was picked by "trial and error." A number of different
resistor values were selected and tested in the lab. The 36.5 Ohms resistor was found
to have the best signal integrity for CLK53_1 at LOAD C and for CLK53_2 at LOAD
D. The trace of CLK53_1 is then routed from the resistor on layer 4 for 3.942 inches,
and then it is routed on layer 5 for 1.993 inches to LOAD C.
li


CLOCK 0.626"
DRIVER ---------
c layer: 5
36.5
Ohms
V-
3.942"
layer: 4
1.993
layer: 5
* LOAD C
Figure 2.6: PCB Trace of CLK53_1
The trace of CLK53_2 is routed as shown in Figure 2.7. From CLOCK DRIVER
C, CLK53_2 is routed on layer 5 for 0.505 inches to the 36.5 ohms resistor. This
value of termination resistor was picked as stated in the previous paragraph. The
trace of CLK53_2 is then routed from the resistor on layer 4 for 5.902 inches to
LOAD D.
CLOCK
DRIVER
C
0.505"
layer: 5
36.5
Ohms
-V
5.902"
layer: 4
* LOADD
Figure 2.7: PCB Trace of CLK53_2
12


3. Theoretical Analysis of the High-Speed
Clock Circuits
This chapter analyzes the transmission line effects of the high-speed clock circuits.
The properties influencing the signal integrity of the clock signals will be discussed.
Some of these signal properties are the trace lengths, edge rates, termination resistors,
and physical layout of the clock signals.
3.1 Transmission Line Theory
A transmission line is a conductor, such as a wire or PCB trace, that transfers an
electric signal or power between two terminals [1]. A transmission line is formed in a
PCB when a signal trace is routed next to a reference plane. The reference plane can
be a power or ground plane. There are two basic structures of transmission lines in a
multilayer PCB, microstrip and stripline topology. Microstrip topology is when a
signal trace is routed on an outer layer of a PCB. Stripline topology is when the
signal trace is routed on an inner layer of a PCB. The high-speed clock circuits
exhibit both of these topologies.
Transmission line effects, such as reflections, occur when a trace is electrically
long [1]. An electrically long trace, in the time domain, is one in which the round-trip
propagation delay is longer than the rise or fall time of the driving signal [1], [3].
When the edge transition time of the signal is less than the time it takes for the signal
to travel from source to load and return from load to source, functionality and signal
integrity issues exist.
A transmission line that is electrically long requires termination [1]. An
unterminated or improper terminated transmission line can cause electromagnetic
interference or the circuit to not function properly. A signal trace that has a round-
trip propagation delay that is longer than the rise or fall time will exhibit poor signal
qualities if it is not terminated correctly [1], [3]. These types of transmission lines
can exhibit overshoot, undershoot, ringing, and cause crosstalk. Some of todays logic
devices exhibit sub-nanosecond edge rates. When these devices are used, careful
attention to transmission line effects must be considered.
The impedance of a trace is an important transmission line characteristic. A signal
will be absorbed at its load if it is terminated in the characteristic impedance of the
trace [1-3], If the signal is not terminated correctly, part of the transmitted signal will
13


be reflected back to the source. Multiple reflections can occur. This can cause
multiple overshoots on the signal, which will require a longer time for the signal to
settle to a steady state. These multiple overshoots are known as ringing in a signal.
The characteristic impedance (Zo) of an ideal transmission line is the square root
of the inductance per unit length (Lo) divided by the capacitance per unit length (Co),
and is also equal to the line voltage (V) divided by the line current (I) [1], [3]. This is
shown in equation 3.1 and is identified as Zo. The voltage to current ratio is constant
only if the termination impedance always matches the characteristic impedance of the
transmission line. The characteristic impedance of traces in a PCB is typically
between 50 and 75 ohms [3].
The resistance of a trace in a PCB is a function of the trace width and trace
thickness. The resistance per unit length (Rl) measured in ohms per inch, for a PCB
trace, is shown in equation 3.2 [3].
0.65866* 10'6
The characteristic impedance can change depending on the frequency of the
signal. Equation 3.3 shows the characteristic impedance as a function of frequency
[1], [3]. In this equation, the frequency ((D) is in radians, Rl is in ohms per inch, Lo is
in henries per inch, and Co is in farads per inch. When the frequency is low, Rl
exceeds coLo and the characteristic impedance is inversely proportional to the square
root of the frequency. When the frequency is high, coLo exceeds Rl, and the
characteristic impedance becomes constant.
The propagation delay per unit length (5) of an ideal transmission line is the
square root of the inductance per unit length multiplied by the capacitance per unit
length [1], [3]. This is shown in equation 3.4.
(3.1)
Z
o
(3.3)
14


s =
(3.4)
The length of a rising edge (Lr) is equal to the rise time (tr) divided by the
propagation delay per unit length [3]. This is shown in equation 3.5. Rise time is
usually measured in picoseconds and propagation delay per unit length is usually
measured in picoseconds per inch.
Electronic circuits are classified as distributed or lumped systems depending on
the rise time of the signals flowing through them. Circuit traces smaller than one-
sixth of Lr (Lj/6) are considered lumped circuits [3]. However, some authors consider
traces smaller than one-fourth of Lr or smaller than Lr divided by the square root of 2
times pie as lumped circuits. In this thesis, we will consider lumped circuits as those
traces that are smaller than one-sixth of 1^. A distributed system is one in which the
reaction of the system to an incoming signal is distributed along the trace [3]. At one
instant of time, different points on a trace in a distributed system can have different
voltage potentials. A lumped system is one in which the trace is short enough that all
points on the trace react together. At one instant of time, different points on a trace in
a lumped system will have the same voltage potential. Distributed circuits always
ring unless terminated [3]. Lumped circuits may not ring if left unterminated.
Lumped circuit theory does not apply to distributed circuits. Therefore, a distributed
circuit model must be used when simulating distributed circuit designs.
The IC used for CLOCK DRIVER A has a rise and fall time specified between 0.5
ns and 1.3 ns. The propagation delay per unit length of an inner trace of a PCB using
FR-4 glass is typically 180 ps/inch [3]. Using equation 3.5, the length of the
minimum rising edge is 2.78 inches. The lumped circuit criteria of L/6 is equal to
0.46 inches. The 106.25 MHz clock circuits will behave as distributed systems since
they have a trace length of approximately 3 inches. Therefore, both of the 106.25
MHz clock circuits will need termination.
The IC used for CLOCK DRIVER C has a rise and fall time specified between 0.3
and 2.0 ns. Assuming the same propagation delay of 180 ps/inch for FR-4 glass, the
minimum rising edge length is 1.67 inches. The lumped circuit criteria of IJ6 is
equal to 0.28 inches. The 53.125 MHz clock circuits will behave as distributed
L,
K
5
(3.5)
15


systems since they have a trace length of approximately 6 inches. Therefore, both of
the 53.125 MHz clock circuits will need termination.
3.2 Source Terminated Transmission Lines
The best method of terminating a transmission line when the line has a lumped
load or a single component at the end of the routed trace is source termination [1].
Source termination is selected for the high-speed clock circuits because they are all
routed point-to-point, and they have a single device at the end of their traces. Source
termination is defined as connecting a series resistor between the driving gate and
before the transmission line that the gate drives. The series resistor should be placed
as close as possible to the driving gate. Source termination matches the impedance of
the series resistor plus the output impedance of the driving gate to the characteristic
impedance of the transmission line [1]. If the impedances are perfectly matched, the
series resistor absorbs all of the reflections. There is no reflection at the source, and a
clean signal is observed at the load.
An ideal source terminated circuit has the following properties [3]:
The series terminator reduces the driving waveform to half of its full voltage
before it propagates down the line.
The driving waveform propagates at half the full voltage all the way down the
transmission line to the load.
Assuming a high impedance at the end of the transmission line, the signal doubles
at the end of the transmission line. The original incoming signal is half the full
voltage, and all of this voltage is reflected back up the transmission line.
Therefore, the signal at the end of the transmission line is at full voltage.
The reflected half voltage signal propagates back up the transmission line on top
of the driving half voltage waveform. There is now a full voltage waveform on
the transmission line. Both sides of the source terminator then go to the same
voltage potential.
When the reflection returns to the driver, the drive current drops to zero.
A series resistor (Rs) should be used when the output resistance (R0) is less than
the characteristic impedance of the trace. The series resistor should be placed as
close to the driver as possible. The series resistor value is equal to the characteristic
impedance minus the output resistance of the driver [1], [3], This calculation is
16


shown in equation 3.6. The value used for series resistors is typically between 15 and
75 ohms.
Rs = Z0-R0 (3.6)
Assuming a perfect voltage divider, the impedance of the output driver plus the
series resistor will equal the characteristic impedance of the trace. The voltage at the
output of the series resistor will be one-half the voltage level sourced by the driver. If
the load or receiver has a high input impedance, the full waveform will be observed at
the receiver. As stated previously, half of the waveform is driven to the load, and half
is reflected back to the source. The driver will receive the full waveform when the
half voltage level is reflected back to the driver. The amount of time this takes is
equal to the round trip propagation delay of the signal.
When using source termination, all loads must be at the end of the line. Daisy
chaining the trace does not work well. A load connected in the middle of a source
terminated line will see half the voltage when the gate is driving the line, and then see
the full voltage when the wave is reflected back to the driving gate.
One of the main problems with source termination is the output impedance of the
driver. An ideal driver has an output impedance of zero ohms. However, real drivers
have a small resistive output impedance. As stated previously, the driver output
impedance plus the series termination resistor must match the characteristic
impedance of the trace. The issue with Transistor-Transistor Logic (TTL) and
Complimentary Metal Oxide Semiconductor (CMOS) circuits is that their output
impedances can be different in their high and low states [1], [3]. Therefore, a
compromise must be made between picking a source termination for the rising edge
and the falling edge. However, a source termination can still be effective despite
these different impedances.
An advantage of using series termination is that a DC current path to ground or
power does not exist through the terminator [1]. Therefore, the output high voltage
and output low voltage are not degraded. When a driver on a series terminated trace
sends a high logic signal, a direct path to ground does not exist. A pull-down resistor
would create a path to ground and cause the whole circuit to consume more power.
When a driver on a series terminated trace sends a logic low signal, the driver does
not consume extra power. A pull-up resistor in the circuit would cause the driver to
consume extra power to keep the signal at a logic low level. Therefore, a series
17


terminated circuit consumes less power than the same circuit with a pull-down or
pull-up terminated resistor.
The rise time can be degraded in a series terminated trace. The response of a
capacitive load (C) on a source terminated line will behave like a resistor-capacitor
(RC) low-pass filter [3]. The RC time constant is ZqC. The 10 % to 90 % rise time
(T10-90) at the load is shown in equation 3.7.
= 2 2Z0C (3.7)
A high source impedance line is one in which the source impedance is much
higher than the characteristic impedance of the transmission line. The step response
of this line is the same as the response of a RC filter. The RC time constant is equal
to the source impedance (Zsource) multiplied by the total line capacitance (Ctot) [3].
This is appropriate for short transmission lines. The 10 % to 90 % rise time (ThSi) of
this high source impedance line is shown in equation 3.8 [3].
T^j = 2.2 ZsourceClot (3.8)
Series termination provides the following advantages [1]:
Reflections are absorbed by the series resistor and are removed or reduced.
A slower rise time can occur, which reduces electromagnetic interference.
Overshoot is reduced.
Ground bounce is reduced.
The quality and integrity of the signal is enhanced.
Less power is consumed than if a pull-up or pull-down resistor is used.
Series termination has the following disadvantages [1]:
It is difficult to match the characteristic impedance when TTL or CMOS devices
are series terminated if their output impedances are different in the high and low
states.
Series termination is not optimal for multiple loads or loads distributed along a
single trace, because there is a period of time that the waveform is only at half the
source voltage.
Daisychain topologies do not work well when source terminated, because of the
reasons previously described. Source termination works best when there is a
single load at the end of the trace.
18


3.3 Microstrip Topology Equations
This section contains equations for microstip routed traces [3]. The trace height
above the reference plane (h), the trace width (w), the trace thickness (t), and the trace
length (L) are measured in inches. The relative permittivity (Er) of the material
between trace and reference plane is dimensionless.
The calculation of the effective relative permittivity (EEFF) is shown in equation
3.10 for wide traces (w > h). Equation 3.9 (E_temp) is an intermediate calculation.
The reason for using the wide trace equations are that the microstrip traces shown in
Figure 2.3 have a trace width of 7 mils and a height above the reference plane of 4
mils. EEFF is a dimensionless quantity.
E temp{h, w, Er)
Er +1
2
1 $ I l r \2h~\ l +
L 2 J w
EEFF(h,w,t,Er) = E _temp(h,w,Er)
(3.9)
(3-10)
The calculation of the effective trace width (WE) is shown in equation 3.11 for
wide traces (2tcw > h). The unit of measurement for WE is inches.
WE(h,w, t)
w +
1.25f
Jt
'2/iT
l + ln
t J
(3 -11)
The calculation of microstrip characteristic impedance (ZMSTRIP) for wide traces
(w > h) is shown in equation 3.13. Equation 3.12 (ZMS_temp) is an intermediate
calculation. The unit of measurement for ZMSTRIP is ohms.
ZMS temp(h, w, t)
I20;r
WE(h,w,t) +1.393+0.667 In
h L h J
(3.12)
19


ZMSTRIP(h, w, t, Er)
(3.13)
ZMS tempih, w, t)
jEEFF(h,w,t,Er)
Accuracy of better than 2 % can be obtained for ZMSTRIP under the following
three conditions shown in equations 3.14, 3.15, and 3.16.
0 < < 0.2
h
(3.14)
0.1 < < 20 (3.15)
h
0 < Er < 16 (3.16)
The calculation of propagation delay for microstrip traces (PMSTRIP) is shown in
equation 3.17. The unit of measurement for PMSTRIP is seconds/inch.
PMSTRlPQi, w,t, Er) = 84.72x10 ~12 ^EEFF(h, w, t, Er) (3.17)
The calculation of inductance for microstrip traces (LMSTRIP) is shown in
equation 3.18. The unit of measurement for LMSTRIP is henries (H).
LMSTRIP(h, w, t, Er, L) = PSTRIP(h, w, t, Er) ZMSTRP(h, w, t, Er) L (3.18)
The calculation of capacitance for microstrip traces (CMSTRIP) is shown in
equation 3.19. The unit of measurement for CMSTRIP is farads (F).
CMSTRIP {h, w,t, Er, L)
PMSTRIPjh, w, t, Er)
ZMSTRIP(h, w,t, Er)
(3.19)
20


3.4 Stripline Topology Equations
This section contains equations for stripline routed traces [3]. The trace height
above the lower reference plane (hi), the trace height below the upper reference plane
(h2), and the total separation between reference planes (b) are measured in inches. As
in the microstrip equations; w, t, and L are measured in inches for the stripline
equations.
The calculation of stripline characteristic impedance (ZSTRIP) for skinny traces
(w/b < 0.35) is shown in equation 3.21. Equation 3.20 (ZSTR_temp) is an
intermediate calculation. The reason for using the skinny trace equations are that the
stripline traces shown in Figure 2.3 have a trace width of 5 mils and a distance
between reference planes of 14.8 mils. The unit of measurement for ZSTRIP is
ohms.
ZSTR temp(w, t)
w t 4kw t" 2"
1+ 1 + ln + 0.255
L 2 J K W t _w _
(3.20)
ZSTRIP(b, w,t, Er)
60 , 4b
j= In -----------------
V£r \_7T ZSTR _temp(w,t)
(3.21)
Accuracy of better than 1.3 % is obtained for ZSTRIP under the following two
conditions shown in equations 3.22 and 3.23. The value of Er does not effect this
accuracy.
- < 0.25 (3.22)
b
< 0.11 (3.23)
w
If the stripline trace is not centered between the reference planes, then the
parameters hi and h2 are not equal. This is an offset or asymmetric stripline trace.
The calculation of offset stripline characteristic impedance (ZOFFSET) is shown in
equation 3.24. The unit of measurement for ZOFFSET is ohms.
21


ZOFFSET (h\, hi, w, t, Er) =
2 ZSTRIP(2 h\ +t, w, t, Er) ZSTRIPj 2 hi +t, w, t, Er) (3.24)
ZSTRIP( 2 *1 + f, w, t, Er) + ZSTRIP(2 hi +1, w, t, Er)
The calculation of propagation delay for stripline traces (PSTRIP) is shown in
equation 3.25. This equation is for centered and offset stripline traces. The unit of
measurement for PSTRIP is seconds/inch.
PSTRIP(Er) = 84.72x10 _12V£r (3.25)
The calculation of inductance for centered stripline traces (LSTRIP) is shown in
equation 3.26. The unit of measurement for LSTRIP is H.
LSTRIP(b, w, t, Er, L) = PSTRIP(Er) ZSTRP(b, w,t,Er)-L (3.26)
The calculation of inductance for offset stripline traces (LOSTRIP) is shown in
equation 3.27. The unit of measurement for LOSTRIP is H.
LOSTRIP{h\, h2, w,t, Er, L) = PSTRIP (Er) ZOFFSET (h\, hi, w, t, Er) L (3.27)
The calculation of capacitance for centered stripline traces (CSTRIP) is shown in
equation 3.28. The unit of measurement for CSTRIP is F.
CSTRIP(b, w, t, Er, L)
PSTRIP(Er)
ZSTRIP(b,w,t,Er)
(3.28)
The calculation of capacitance for offset stripline traces (COSTRIP) is shown in
equation 3.29. The unit of measurement for COSTRIP is F.
COSTRlP(h\,h2, w, t, Er, L)
PSTRIP(Er)
ZOFFSET (h\, hi, w,t, Er)
(3.29)
22


3.5 Parameter Calculations for the High-Speed
Clock Circuits
This section calculates the characteristic impedance, propagation delay,
transmission line inductance, and transmission line capacitance of the high-speed
clock circuits shown in section 2.2. Programs were written using the Matlab numeric
computation software to calculate the microstrip and stripline equations. These
programs are shown in appendix A. The parameters for each trace were inputs to the
programs, and the results of the programs are documented below. The accuracy of
the programs was checked by hand calculations.
3.5.1 Calculations for CLK106_1
The PCB stack up for CLK106_1 is shown in Figure 2.3, and the physical
parameters of the CLK106_1 trace are shown in Figure 2.4. Both of these figures
contain the information needed to calculate the parameters outlined in sections 3.3
and 3.4.
Using the microstip equations in section 3.3, the characteristic impedance for the
0.185 inch trace is 48.99 ohms and the propagation delay is 146.77 ps/inch. The total
propagation delay for this trace is 27.15 ps, the inductance is 1.33 nanohenries (nH),
and the capacitance is 554.28 femtofarads (fF).
Using the stripline equations in section 3.4, the offset characteristic impedance for
the 1.727 inch trace is 44.07 ohms and the propagation delay is 175.68 ps/inch. The
total propagation delay for this trace is 303.40 ps, the offset inductance is 13.37 nH,
and the offset capacitance is 6.88 pF.
The offset characteristic impedance for the 1.228 inch trace is 44.07 ohms and the
propagation delay is 175.68 ps/inch. The total propagation delay for this trace is
215.73 ps, the offset inductance is 9.51 nH, and the offset capacitance is 4.89 pF.
3.5,2 Calculations for CLK106_2
The PCB stack up for CLK106_2 is also shown in Figure 2.3, and the physical
parameters of the CLK106_2 trace are shown in Figure 2.5. Both of these figures
23


contain the information needed to calculate the parameters outlined in sections 3.3
and 3.4.
Using the microstip equations in section 3.3, the characteristic impedance for the
0.468 inch trace is 48.99 ohms and the propagation delay is 146.77 ps/inch. The total
propagation delay for this trace is 68.69 ps, the inductance of this trace 3.37 nH, and
the capacitance of this trace is 1.40 pF.
Using the stripline equations in section 3.4, the offset characteristic impedance for
the 2.926 inch trace is 44.07 ohms and the propagation delay is 175.68 ps/inch. The
total propagation delay for this trace is 514.04 ps, the offset inductance is 22.66 nH,
and the offset capacitance is 11.66 pF.
3.5.3 Calculations for CLK53_1
The PCB stack up for CLK53_1 is also shown in Figure 2.3, and the physical
parameters of the CLK53_1 trace are shown in Figure 2.6. Both of these figures
contain the information needed to calculate the stripline parameters outlined in
section 3.4.
Using the stripline equations in section 3.4, the offset characteristic impedance for
the 0.626 inch trace is 44.07 ohms and the propagation delay is 175.68 ps/inch. The
total propagation delay for this trace is 109.98 ps, the offset inductance is 4.85 nH,
and the offset capacitance is 2.50 pF.
The offset characteristic impedance for the 3.942 inch trace is 44.07 ohms and the
propagation delay is 175.68 ps/inch. The total propagation delay for this trace is
692.53 ps, the offset inductance is 30.52 nH, and the offset capacitance is 15.71 pF.
The offset characteristic impedance for the 1.993 inch trace is 44.07 ohms and the
propagation delay is 175.68 ps/inch. The total propagation delay for this trace is
350.13 ps, the offset inductance is 15.43 nH, and the offset capacitance is 7.94 pF.
3.5.4 Calculations for CLK53_2
The PCB stack up for CLK53_2 is also shown in Figure 2.3, and the physical
parameters of the CLK53_2 trace are shown in Figure 2.7. Both of these figures
24


contain the information needed to calculate the stripline parameters outlined in
section 3.4.
Using the stripline equations in section 3.4, the offset characteristic impedance for
the 0.505 inch trace is 44.07 ohms and the propagation delay is 175.68 ps/inch. The
total propagation delay for this trace is 88.72 ps, the offset inductance is 3.91 nH, and
the offset capacitance is 2.01 pF.
The offset characteristic impedance for the 5.902 inch trace is 44.07 ohms and the
propagation delay is 175.68 ps/inch. The total propagation delay for this trace is
1.037 ns, the offset inductance is 45.70 nH, and the offset capacitance is 23.53 pF.
25


4. Simulation of the High-Speed Clock Circuits
A PCB trace simulator called LineSim, from the HyperLynx suite of computer
aided design software, was used to simulate the high-speed clock circuits. The stack
up shown in Figure 2.3 was used to enter schematics of the clock circuits, as well as
pertinent data from Figures 2.4 through 2.7. LineSim is a professional simulator used
in industry for simulating PCB related issues such as signal integrity, electromagnetic
interference, and signal crosstalk concerns.
4.1 Simulation Setup
The schematics used to simulate the high-speed clock circuits are shown in
Figures 4.1,4.3,4.5, and 4.7. The traces that were routed in a microstrip and stripline
topologies were schematically captured as microstrip and stripline traces,
respectively, with the appropriate stack up. The parameters entered to simulate the
microstrip traces were the trace width, trace thickness, trace length, distance between
the trace and reference plane, dielectric constant, and the weight of copper used for
the trace. The parameters entered to simulate the stripline traces were the trace width,
trace thickness, trace length, distances to both the lower and upper reference planes
from the trace, dielectric constant, and the weight of copper used for the trace. The
dielectric constant used for all simulations was 4.3, which is the standard for FR-4
glass [3]. The other parameters used for simulation can be found in Figures 2.3
through 2.7. For simulation, the clock at the driver was set to a 50 % duty cycle, fast
transition time, and strong drive. The board temperature was set to 20 degrees
Celsius. All of the schematics have a 1 megaohm pull-down resistor and a 1 pF
capacitor at the receiver. The resistor and capacitor model the extra load that an
oscilloscope probe adds to the circuit [9]. More information about the probe and
oscilloscope will be discussed in the next chapter.
4.2 Simulation Results
This section contains the high-speed clock circuit simulation schematics, the
waveform simulation results, and other results from the LineSim simulator. The
waveform simulation results show the predicted clock waveforms at the driver and
receiver. The other results from the simulator are what LineSim calculated to be the
characteristic impedance of the trace, the total propagation delay of the trace, the
inductance of the trace, and the capacitance of the trace.
26


4.2.1 CLK106_1 Simulation Results
The schematic used for simulating CLK106_1 is shown in Figure 4.1.
U(A0) K
CDC319^
1Y0
47.9 ohms
27.778 ps
0.185 in
Microstrip
44.3 ohms
215.747 ps
1.228 in
Stripline
U(B2)
S2067
REFCLK
Figure 4.1: CLK106_1 Simulation Schematic
27


The waveform simulation results for CLK106_1 are shown in Figure 4.2. Probe 1
is the clock waveform at U(A0) or the output of the CDC319 driver as shown in
Figure 4.1. It is a 106.25 MHz clock. Probe 2 is the clock waveform at U(B2) or the
input of the S2067 receiver as shown in Figure 4.1. The simulator models used for
the driver and receiver are Input/Output Buffer Information Specification (IBIS)
models. IBIS is an electronic design industry standard for modeling IC devices [10].
The total delay from the CDC319 driver to the S2067 receiver is approximately 778
ps as measured at 1.5 volts of the waveforms. LineSim reported a characteristic
impedance of 47.9 ohms for the microstrip routed trace and 44.3 ohms for the
stripline routed traces. The simulator calculated a total propagation delay of 27.778
ps, an inductance of 1.3 nH, and a capacitance of 580.3 fF for the microstrip routed
trace. The 1.727 inch stripline routed trace was calculated to have a total propagation
delay of 303.417 ps, an inductance of 13.4 nH, and a capacitance of 6.9 pF. The
1.228 inch stripline routed trace was calculated to have a total propagation delay of
215.747 ps, an inductance of 9.6 nH, and a capacitance of 4.9 pF.
1:U(A0)
3:U(B2)
Figure 4.2: CLK106_1 Simulation Waveform Results
28


4.2.2 CLK106_2 Simulation Results
The schematic used for simulating CLK106_2 is shown in Figure 4.3.
U(AO)K
CDC319*'
1Y1
47.9 ohms
70.270 ps
0.468 in
Microstrip
Stripline
U(B2)
Virtex
LVTTL12F_I
Figure 4.3: CLK106_2 Simulation Schematic
29


The waveform simulation results for CLK106_2 are shown in Figure 4.4. Probe 1
is the clock waveform at U(A0) or the output of the CDC319 driver as shown in
Figure 4.3. It is a 106.25 MHz clock. Probe 2 is the clock waveform at U(B2) or the
input of the Virtex receiver as shown in Figure 4.3. The simulator models used for
the driver and receiver are IBIS models. The total delay from the CDC319 driver to
the Virtex receiver is approximately 981 ps as measured at 1.5 volts of the
waveforms. LineSim reported a characteristic impedance of 47.9 ohms for the
microstrip routed trace and 44.3 ohms for the stripline routed trace. The simulator
calculated a total propagation delay of 70.27 ps, an inductance of 3.4 nH, and a
capacitance of 1.5 pF for the microstrip routed trace. The 2.926 inch stripline routed
trace was calculated to have a total propagation delay of 514.069 ps, an inductance of
22.8 nH, and a capacitance of 11.6 pF.
1 :U(A0)
3:U(B2)
Figure 4.4: CLK106_2 Simulation Waveform Results
30


4.2.3 CLK53_1 Simulation Results
The schematic used for simulating CLK53_1 is shown in Figure 4.5.
U(AO) N
QS5V919
N16
/y\
44.3 ohms
109.982 ps
0.626 in
Stripline
u
36.5 ohms 44.3 ohms
____V£T~ 692.570 ps~\
3.942 in
Stripline

44.3 ohms
350.150 ps
1.993 in
Stripline
U(B2) yi
Virtex \[
LVTTL12FJ
1.0
M ohms
1
I
1.0 pF
Figure 4.5: CLK53_1 Simulation Schematic
31


The waveform simulation results for CLK53_1 are shown in Figure 4.6. Probe 1
is the clock waveform at U(A0) or the output of the QS5V919 driver as shown in
Figure 4.5. It is a 53.125 MHz clock. Probe 2 is the clock waveform at U(B2) or the
input of the Virtex receiver as shown in Figure 4.5. The simulator models used for
the driver and receiver are IBIS models. The total delay from the QS5V919 driver to
the Virtex receiver is approximately 1.39 ns as measured at 1.5 volts of the
waveforms. LineSim reported a characteristic impedance of 44.3 ohms for the
stripline routed traces. The simulator calculated a total propagation delay of 109.982
ps, an inductance of 4.9 nH, and a capacitance of 2.5 pF for the 0.626 inch stripline
routed trace. The 3.942 inch stripline routed trace was calculated to have a total
propagation delay of 692.57 ps, an inductance of 30.7 nH, and a capacitance of 15.6
pF. The 1.993 inch stripline routed trace was calculated to have a total propagation
delay of 350.15 ps, an inductance of 15.5 nH, and a capacitance of 7.9 pF.
1:U(A0)
3:U(B2)
Figure 4.6: CLK53_1 Simulation Waveform Results
32


4.2.4 CLK53_2 Simulation Results
The schematic used for simulating CLK53_2 is shown in Figure 4.7.
U(AO) N
Qssvgig^
N16
44.3 ohms
88.723 ps
0.505 in
Stripline
Stripline
U(B2)
74LVTH16374
CP1
1.0
M ohms
Figure 4.7: CLK53_2 Simulation Schematic
33


The waveform simulation results for CLK53_2 are shown in Figure 4.8. Probe 1
is the clock waveform at U(A0) or the output of the QS5V919 driver as shown in
Figure 4.7. It is a 53.125 MHz clock. Probe 2 is the clock waveform at U(B2) or the
input of the 74LVTH16374 receiver as shown in Figure 4.7. The simulator models
used for the driver and receiver are IBIS models. The total delay from the QS5V919
driver to the 74LVTH16374 receiver is approximately 1.315 ns as measured at 1.5
volts of the waveforms. LineSim reported a characteristic impedance of 44.3 ohms
for the stripline routed traces. The simulator calculated a total propagation delay of
88.723 ps, an inductance of 3.9 nH, and a capacitance of 2.0 pF for the 0.505 inch
stripline routed trace. The 5.902 inch stripline routed trace was calculated to have a
total propagation delay of 1.037 ns, an inductance of 45.9 nH, and a capacitance of
23.4 pF.
Probe 1:U(A0)
Probe 3:U(B2)
Figure 4.8: CLK53_2 Simulation Waveform Results
34


5. Oscilloscope Measurements of the High-Speed
Clock Circuits
This chapter contains oscilloscope measurements of the high-speed clock circuits
in a real PCB. The high-speed clock circuits were fabricated in a PCB. The PCB has
a stack up similar to that shown in Figure 2.3. The clock circuits were specified to be
layed out according to the physical parameters shown in Figures 2.4 through 2.7.
Measurements were taken of these high-speed clock circuits using a digital
oscilloscope. The waveform shapes and propagation delays will be later compared to
the theoretical and simulation results.
The fastest edge rate of the high-speed clock circuits is the 0.3 ns rise time of
CLOCK DRIVER C. To accurately view this fast edge rate, an oscilloscope and
probe should have the bandwidth to measure a rise time of 0.3 ns. The probes used to
measure the high-speed clock signals were active probes from Tektronix (P6245).
The digital oscilloscope used to measure the clock signals was also from Tektronix
(TDS 684B). When the P6245 probes are used with a TDS 684B oscilloscope, the
whole system has a bandwidth of 1.0 GHz [9], [11]. The instrument rise time (RTj) is
calculated as shown in equation 5.1 when using the TDS 684B oscilloscope and a
P6245 probe [11]. The measured rise time (RTm) of a signal when using an
oscilloscope is a function of RT* and the actual signal rise time (RTa) as shown in
equation 5.2 [11]. For example, the TDS 684B will measure a rise time of 0.541 ns if
the actual rise time of the signal is 0.3 ns.
RT;. (ns)
450
bandwidth (MHz)
(5.1)
RT2 = RT2 + RTa2 (5.2)
The TDS 684B has a maximum delay between channels of 100 ps [11].
Therefore, when using 2 probes to measure the delay between the source and the load,
the measurement has an accuracy of within 100 ps.
5.1 Oscilloscope Setup
The two P6245 probes that were used to take the clock measurements were
calibrated on July 3, 1999 and August 23, 1999. They are both due for recalibration
35


on July 3, 2000 and August 23, 2000. The TDS 684B oscilloscope that was used to
take the clock measurements was calibrated on July 20, 1999 and is due for
recalibration on July 20,2000. All of the clock measurements were taken within the
calibration periods of the probes and oscilloscope. A probe calibration test from the
TDS 684B was run for each scope probe before the measurements were taken. This
probe calibration test improves the gain and offset accuracy of the probe based on the
channel it is connected to [12].
The P6245 probes and TDS 684B had a warm-up period of at least 20 minutes
before any clock measurements were taken. The ground wires on each scope probe
were as short as possible when taking measurements. Each probe had a ground wire
that was 3 inches long.
The trigger was set to 1.5 volts when capturing each clock waveform. The vertical
cursors were used to measure the rise and fall time in seconds per volt. These
measurements were taken at amplitudes between 1.0 and 2.0 volts. The TDS 684B
has a built in function to measure the rise and fall times. This function was also used,
and it was setup to measure the rise and fall times between the 10 % and 90 % points
of the peak-to-peak waveforms. The vertical cursors were also used to measure the
clock trace delays and skew between clocks. These delays were measured at an
amplitude of 2.0 volts. The TDS 684B has a built in function to measure the delay
between two signals. This function was also used, and it was setup to measure the
delay at the 50 % point of the peak-to-peak waveforms.
5.2 Oscilloscope Results
This section contains the oscilloscope measurements of the high-speed clock
circuits. Waveforms were captured at the source and load of each clock circuit. The
maximum and minimum voltages were recorded, as well as the rise and fall times for
each waveform. The load and source waveforms are shown on separate figures to
show the overshoot, undershoot, and ringing of each signal. The load and source
waveforms of each clock were then captured at the same time to measure the delay of
the trace. The skew between the clocks was also measured. To measure the skew
between the 106.25 MHz clocks (CLK106_1, CLK106_2), the source waveforms of
both clocks were captured at the same time. The load waveforms were too difficult to
capture at the same time because of the placement of the probes. To measure the
skew of the 53.125 MHz clocks (CLK53_1, CLK53_2), the load waveforms of both
clocks were captured at the same time.
36


The waveform measured by the oscilloscope at the source of CLK106_1 is shown
in Figure 5.1. This signal is driven from a CDC319 clock driver. The maximum
voltage of this clock signal is 3.7 volts and the minimum voltage is -180 millivolts
(mV). The rise time measured between 1 and 2 volts is 280 ps/volt and the rise time
between the 10 % and 90 % points is 752 ps. The fall time measured between 1 and 2
volts is 240 ps/volt and the fall time between the 10 % and 90 % points is 624 ps.
Tek gEMjjlj 5.00GS/S 5Acqs
!T--------E-----4-----------1
A: 3.30 V
3.30 V
Cl Freq
106.2644MHZ
C1 Rise
752ps
Cl Fall
624ps
Figure 5.1: CLK106_1 Source Waveform
37


The waveform measured by the oscilloscope at the load of CLK106_1 is shown in
Figure 5.2. This signal is received by a S2067 high-speed backplane transceiver. The
maximum voltage of this clock signal is 3.42 volts and the minimum voltage is -120
mV. The rise time measured between 1 and 2 volts is 360 ps/volt and the rise time
between the 10 % and 90 % points is 1.34 ns. The fall time measured between 1 and
2 volts is 320 ps/volt and the fall time between the 10 % and 90 % points is 1.112 ns.
Tek MMUJ 5.00GS/S 3 Acqs
h-T-------{-----}
A: 3.30 V
3.30 V
Cl Freq
106.2264MHZ
C1 Rise
1.340ns
Cl Fall
1.112ns
Figure 5.2: CLK106_1 Load Waveform
38


The waveform measured by the oscilloscope at the source of CLK106_2 is shown
in Figure 5.3. This signal is driven from a CDC319 clock driver. The maximum
voltage of this clock signal is 3.68 volts and the minimum voltage is -60 mV. The
rise time measured between 1 and 2 volts is 280 ps/volt and the rise time between the
10 % and 90 % points is 812 ps. The fall time measured between 1 and 2 volts is 240
ps/volt and the fall time between the 10 % and 90 % points is 684 ps.
Tek 3SHB 5.oogs/s
-T-
3 Acqs
f----1
Figure 5.3: CLK106_2 Source Waveform
39


The waveform measured by the oscilloscope at the load of CLK106_2 is shown in
Figure 5.4. This signal is received by a Virtex FPGA. The maximum voltage of this
clock signal is 3.52 volts and the minimum voltage is -20 mV. The rise time
measured between 1 and 2 volts is 440 ps/volt and the rise time between the 10 % and
90 % points is 1.188 ns. The fall time measured between 1 and 2 volts is 440 ps/volt
and the fall time between the 10 % and 90 % points is 1.260 ns.
Tek 3£]3 5.00GS/S 2 Acqs
Figure 5.4: CLK106_2 Load Waveform
40


The waveform measured by the oscilloscope at the source of CLK53_1 is shown
in Figure 5.5. This signal is driven from a QS5LV919 clock driver. The maximum
voltage of this clock signal is 3.6 volts and the minimum voltage is -280 mV. The
rise time measured between 1 and 2 volts is 500 ps/volt and the rise time between the
10 % and 90 % points is 1.27 ns. The fall time measured between 1 and 2 volts is 400
ps/volt and the fall time between the 10 % and 90 % points is 990 ps.
Tek 3233 5.00GS/s 2 Acqs
h~T-------[-----}
A: 3.30 V
3.30 V
C1 Freq
53.1304MHz
Cl Rise
1.27ns
C1 Fall
990ps
Figure 5.5: CLK53_1 Source Waveform
41


The waveform measured by the oscilloscope at the load of CLK53_1 is shown in
Figure 5.6. This signal is received by a Virtex FPGA. The maximum voltage of this
clock signal is 3.66 volts and the minimum voltage is -480 mV. The rise time
measured between 1 and 2 volts is 500 ps/volt and the rise time between the 10 % and
90 % points is 1.23 ns. The fall time measured between 1 and 2 volts is 400 ps/volt
and the fall time between the 10 % and 90 % points is 1.11 ns.
Tek MMH 5.00GS/S 2 Acqs
i-F-------1------}
a: 3.30 V
>: 3.30 V
C1 Freq
53.1219MHZ
Cl Rise
1.23ns
Cl Fall
1.11ns
Figure 5.6: CLK53_1 Load Waveform
42


The waveform measured by the oscilloscope at the source of CLK53_2 is shown
in Figure 5.7. This signal is driven from a QS5LV919 clock driver. The maximum
voltage of this clock signal is 3.48 volts and the minimum voltage is -200 mV. The
rise time measured between 1 and 2 volts is 500 ps/volt and the rise time between the
10 % and 90 % points is 1.35 ns. The fall time measured between 1 and 2 volts is 400
ps/volt and the fall time between the 10 % and 90 % points is 1.12 ns.
Tek gmyj s.oocs/s ^ 2 Acqs^
Figure 5.7: CLK53_2 Source Waveform
43


The waveform measured by the oscilloscope at the load of CLK53_2 is shown in
Figure 5.8. This signal is received by a SN74LVTH374 flip-flop. The maximum
voltage of this clock signal is 3.64 volts and the minimum voltage is -540 mV. The
rise time measured between 1 and 2 volts is 500 ps/volt and the rise time between the
10 % and 90 % points is 1.33 ns. The fall time measured between 1 and 2 volts is 400
ps/volt and the fall time between the 10 % and 90 % points is 1.11 ns.
Tek^UJm 5.00GS/S ^__________5 Acqs^
3.30 V
Cl Freq
53.1192MHz
Cl Rise
1.33ns
Cl Fall
1.11 ns
Figure 5.8: CLK53_2 Load Waveform
44


The source and load waveforms measured by the oscilloscope for CLK106_1 are
shown in Figure 5.9. The trace delay of CLK106_1 measured at 2 volts is 800 ps and
the delay measured at the 50 % point is 778 ps.
45


The source and load waveforms measured by the oscilloscope for CLK106_2 are
shown in Figure 5.10. The trace delay of CLK106_2 measured at 2 volts is 1.02 ns
and the delay measured at the 50 % point is 980 ps.
MfaliM 5.00GS/S 3539 Acqs
h-T------Hf-4
A: 1.02ns
18.82ns
C1+C2 Dly
980ps
Figure 5.10: CLK106_2 Trace Delay
46


The source waveforms measured by the oscilloscope for CLK106_1 and
CLK106_2 are shown in Figure 5.11. CLK106_1 leads CLK106_2. The skew
between the source waveforms of CLK106_1 and CLK106_2 measured at 2 volts is
90 ps and the delay measured at the 50 % point is 59 ps.
BHiim 5.OOGS/s 96 Acqs
-------[{4
A: 90ps
9.39ns
C1-*C2 Dly
59ps
Figure 5.11: CLK106_1 and CLK106_2 Source Skew
The average skew between CLK106_1 and CLK106_2 at their sources from the
two measurements in Figure 5.11 is 74.5 ps. The average trace delay of the two
measurements from Figure 5.9 for CLK106_1 is 789 ps. The average trace delay of
the two measurements from Figure 5.10 for CLK106_2 is 1.0 ns. Using these
average delays and skew, the average skew between CLK106_1 and CLK106_2 at
their loads is 285.5 ps.
47


The source and load waveforms measured by the oscilloscope for CLK53_1 are
shown in Figure 5.12. The trace delay of CLK53_1 measured at 2 volts is 1.34 ns and
the delay measured at the 50 % point is 1.36 ns.
EH3BI 5-OOGS/s 151 Acqs^
A: 1.34ns
18.88ns
C1+C2 Dly
1.360ns
Figure 5.12: CLK53_1 Trace Delay
48


The source and load waveforms measured by the oscilloscope for CLK53_2 are
shown in Figure 5.13. The trace delay of CLK53_2 measured at 2 volts is 1.2 ns and
the delay measured at the 50 % point is 1.312 ns.
49


The load waveforms measured by the oscilloscope for CLK53_1 and CLK53_2
are shown in Figure 5.14. CLK53_1 leads CLK53_2. The skew between the load
waveforms of CLK53_1 and CLK53_2 measured at 2 volts is 120 ps and the delay
measured at the 50 % point is 48 ps. The average skew between CLK53_1 and
CLK53_2 at their loads is 84 ps.
A: 120ps
18.86ns
C1-C2 Dly
48ps
Figure 5.14: CLK53_1 and CLK53_2 Load Skew
gnilfH 5.00GS/S 370 Acqs
IT-------{-f--}
50


6. Analysis of Results
This chapter discusses the results of the theoretical analysis, simulation, and
oscilloscope measurements of the high-speed clock circuits. The calculated results
using the microstrip and stripline equations from chapter 3 will be compared to the
simulation and oscilloscope results. The waveforms and propagation delays from the
LineSim simulator will be compared to the oscilloscope waveforms and propagation
delay measurements.
The clock signals (CLK106_1, CLK106_2, CLK53_1, and CLK53_2) are
considered to be transmission line signals. The source to destination propagation
delays of CLK106_1, CLK106_2, CLK53_1, and CLK53_2, as calculated from the
theoretical equations, are 546.28 ps, 582.73 ps, 1.153 ns, and 1.126 ns, respectively.
These calculations do not include the delay through the source termination resistor.
The clock driver for CLK106_1 and CLK106_2 has a minimum rise time of 0.5 ns.
The clock driver for CLK53_1 and CLK53_2 has a minimum rise time of 0.3 ns.
Therefore, CLK106_1, CLK106_2, CLK53_1, and CLK53_2 are considered to be
electrically long traces since their round trip propagation delays are longer than their
minimum edge rates. Careful attention to transmission line effects must be
considered for these traces, and they should all be properly terminated. The
propagation delay calculations from LineSim and the oscilloscope measurements
have similar results showing that these clock signals should be considered as
electrically long transmission line signals.
A clock skew of less than 1 ns was specified for the loads at CLK106_1 and
CLK106_2, and for the loads at CLK53_1 and CLK53_2. To find the clock skew of
the 106.25 MHz clocks, the oscilloscope waveforms in Figures 5.9 through 5.11 were
used, because the clock signals could not be measured directly at the loads. As stated
previously, the average skew between CLK106_1 and CLK106_2 at their loads is
285.5 ps. To find the clock skew of the 53.125 MHz clocks, the oscilloscope
waveforms in Figure 5.14 were used. As stated previously, the average skew between
CLK53_1 and CLK53_2 is 84 ps. Since the TDS 684B has a maximum delay
between channels of 100 ps, the actual skew between the clocks may be smaller. The
target skew of 1 ns was met for both the 106.25 MHz clock circuits and the 53.125
MHz clock circuits.
The oscilloscope waveforms at the clock loads are cleaner signals than the
waveforms at the clock sources. Source termination has reduced the overshoot,
undershoot, and reflections at the clock loads from that of the clock sources. The
51


load waveforms of CLK106_1 and CLK106_2 have reduced overshoot and
undershoot from that of their source waveforms. The 106.25 MHz load waveforms
also have slower edge rates from that of their source waveforms. The load
waveforms of CLK53_1 and CLK53_2 have less ringing than that of their source
waveforms, however, the edge rates are about the same.
The source termination resistors do not match the calculated characteristic
impedances of the clock traces. As stated in chapter 2, these resistors were selected
because the signal quality at the loads was best when these values are used. The
106.25 MHz clock signals have termination resistors of 56.2 ohms and the 53.125
MHz clock signals have termination resistors of 36.5 ohms. Each clock trace has a
characteristic impedance of approximately 44 ohms between its source termination
and load. For proper termination, the source termination should match the
characteristic impedance of the trace. Since the clock drivers are not ideal, they have
non-zero output impedance. The output impedance of the clock drivers is not
available in their data sheets. The source termination impedance that is matched for
the 53.125 MHz clocks is equal to the 36.5 ohms source termination resistor plus the
output impedance of the QS5LV919 clock driver. The source termination impedance
of the 106.25 MHz clocks is equal to the 56.2 ohms source termination resistor plus
the output impedance of the CDC319 clock driver. Since the source impedance is
greater than the characteristic impedance of the transmission line, CLK106_1 and
CLK106_2 will have some characteristics of high source impedance traces. The load
waveforms have a slight curve, which resemble the response of a RC filter. Using the
rise time calculation in equation 3.8, Zsource equal to 56.2 ohms, and Ctot including the
1 pF probe load, CLK106_1 and CLK106_2 should have a rise time of 1.58 ns and
1.57 ns, respectively. Since the output impedance of the clock driver is unknown,
56.2 ohms was used for the source impedance. Using equations 5.1 and 5.2, the
actual rise time measured by the oscilloscope for CLK106_1 and CLK106_2 are 1.26
ns and 1.10 ns, respectively. The differences in rise time calculations are from the
106.25 MHz clocks not behaving exactly like high source impedance traces. The
source impedances of the 106.25 MHz clocks are not magnitudes greater than their
transmission line characteristic impedances.
6.1 Theoretical and Simulation Comparisons
The characteristic impedance of the microstrip and stripline routed traces were
calculated from equations 3.13 and 3.24, respectively. The calculated characteristic
impedance for the microstrip routed traces is 48.99 ohms, and the calculated
52


characteristic impedance for the stripline routed traces is 44.07 ohms. The LineSim
simulator calculated 47.9 ohms as the characteristic impedance for the microstrip
routed traces and 44.3 ohms for the stripline routed traces. The result from the
microstrip characteristic impedance equation is accurate to within 2.3 % of the
LineSim result. The result from the stripline characteristic impedance equation is
accurate to within 0.5 % of the LineSim result.
Calculations for propagation delay, inductance, and capacitance for microstrip and
stripline routed traces were computed from equations 3.17 through 3.19 and 3.25
through 3.29. Tables 6.1 through 6.3 contain the theoretical and simulation
calculations for the propagation delay, inductance, and capacitance for the high-speed
clock traces. These same results are stated previously, but are shown again for ease
of comparison. The theoretical propagation delay, inductance, and capacitance
calculations for the microstrip traces are accurate to within 2.3 %, 2.3 % and 6.7 %,
respectively, of the LineSim results. The theoretical propagation delay, inductance,
and capacitance calculations for the stripline traces are accurate to within 0.009 %,
1.0 % and 0.7 %, respectively, of the LineSim results.
Table 6.1: Theoretical and Simulation Propagation Delay
Results
Clock Name Trace Length (inches) Theoretical Propagation Delay (ps) Simulation Propagation Delay (ps) Difference (%)
CLK106.1 0.185 27.15 27.78 2.3
1.727 303.40 303.42 0.007
1.228 215.73 215.75 0.009
CLK106.2 0.468 68.69 70.27 2.2
2.926 514.04 514.07 0.006
CLK53.1 0.626 109.98 109.98 0
3.942 692.53 692.57 0.006
1.993 350.13 350.15 0.006
CLK53_2 0.505 88.72 88.72 0
5.902 1037.0 1037.0 0
53


Table 6.2: Theoretical and Simulation Inductance Results
Clock Name Trace Length (inches) Theoretical Inductance (nH) Simulation Inductance (nH) Difference (%)
CLK106_1 0.185 1.33 1.3 2.3
1.727 13.37 13.4 0.2
1.228 9.51 9.6 0.9
CLK106_2 0.468 3.37 3.4 0.9
2.926 22.66 22.8 0.6
CLK53_1 0.626 4.85 4.9 1.0
3.942 30.52 30.7 0.6
1.993 15.43 15.5 0.5
CLK53_2 0.505 3.91 3.9 0.3
5.902 45.70 45.9 0.4
Table 6.3: Theoretical and Simulation Capacitance Results
Clock Name Trace Length (inches) Theoretical Capacitance (pF) Simulation Capacitance (pF) Difference (%)
CLK106_1 0.185 0.55 0.58 5.2
1.727 6.88 6.9 0.3
1.228 4.89 4.9 0.2
CLK106_2 0.468 1.4 1.5 6.7
2.926 11.66 11.6 0.5
CLK53_1 0.626 2.5 2.5 0
3.942 15.71 15.6 0.7
1.993 7.94 7.9 0.5
CLK53_2 0.505 2.01 2.0 0.5
5.902 23.53 23.4 0.6
54


The theoretical and simulator results are very similar, but there are some
differences. The results from the stripline equations compare very well to the
simulator results. The results using the stripline equations have an accuracy of 1 % or
less when compared to the simulator results. The results from the microstrip
equations do not compare as well. The results from the microstrip equations have an
accuracy between 0.9 % and 6.7 % when compared to the simulator results. This
large inaccuracy could be from the microstrip traces being small and the theoretical
microstrip equations do not give good results when using small trace length numbers.
The difference in the results could also be from the precision of the numbers used in
the calculations of the simulator and microstrip equations. Both methods may use
slightly different equation constants which would cause different results.
6.2 Theoretical and Oscilloscope Measurement
Comparisons
The total trace propagation delays calculated from equations 3.17 and 3.25 for
CLK106_1, CLK106_2, CLK53_1, and CLK53_2 are 546.28 ps, 582.73 ps, 1.153 ns,
and 1.126 ris, respectively. Taking the average of the two propagation delays
measured from the oscilloscope, the 50 % point and at 2 volts, the propagation delays
are 789 ps, 1.0 ns, 1.35 ns, and 1.26 ns for CLK106_1, CLK106_2, CLK53_1, and
CLK53_2, respectively. The oscilloscope has an accuracy of within 100 ps when
measuring delay between two channels. Using this 100 ps range, the actual delay for
CLK106_1 is between 689 ps and 789 ps, and the actual delay for CLK106_2 is
between 900 ps and 1.0 ns. The actual delay for CLK53_1 is between 1.25 ns and
1.35 ns, and the actual delay for CLK53_2 is between 1.16 ns and 1.26 ns. Using the
smallest delay of the oscilloscope ranges, the theoretical results have an accuracy of
21%, 35 %, 8 %, and 3 % for CLK106_1, CLK106_2, CLK53_1, and CLK53_2,
respectively. This large discrepancy in calculated propagation delays can be
attributable to the delays for the series resistor and the vias were not calculated in the
theoretical case. The theoretical equations also do not model the loads that the
drivers, receivers, and scope probes add to the circuit.
6.3 Simulation and Oscilloscope Measurement
Comparisons
The total propagation delays obtained from the LineSim simulator, as measured
from the waveforms, for CLK106_1, CLK106_2, CLK53_1, and CLK53_2 are 778
55


ps, 981 ps, 1.39 ns, and 1.32 ns, respectively. The actual delays the oscilloscope
measured are stated in the previous paragraph. The LineSim calculated propagation
delays for CLK106_1 and CLK106_2 are within the oscilloscope measured ranges.
However, the LineSim calculated propagation delays for CLK53_1 and CLK53_2 are
higher than the oscilloscope measured ranges by 40 ps and 60 ps, respectively. This
is an accuracy of within 3.0 % and 4.8 % for CLK53_1 and CLK53_2, respectively,
when compared to the oscilloscope measurements. The discrepancies between the
LineSim calculated propagation delays and the oscilloscope measured propagation
delays can be attributable to LineSim not simulating the vias in the clock traces and
the accuracy of the IC models used in LineSim [13].
The waveforms of the LineSim simulator do not exactly compare with the
waveforms of the oscilloscope. The LineSim source waveforms for CLK106_1 and
CLK106_2 are basically flat waveforms with no overshoot and a rise time of
approximately 1.5 ns. The oscilloscope source waveforms for CLK106_1 and
CLK106_2 are not flat. They have an overshoot that rises to approximately 3.7 volts
and a small undershoot below ground. The actual rise times of CLK106_1 and
CLK106_2, using equations 5.1 and 5.2 and the 10 % and 90 % points, are 602 ps and
676 ps, respectively. The LineSim load waveforms for CLK106_1 and CLK106_2
are also basically flat waveforms with no overshoot. The rise time of the waveform at
the load of CLK106_1 is approximately 2.0 ns and the rise time of the waveform at
the load of CLK106_2 is approximately 2.5 ns. The oscilloscope load waveform for
CLK106_1 is basically flat with some ringing or reflections, and has an actual rise
time of 1.26 ns. These reflections are not shown in the LineSim waveform. The
oscilloscope load waveform for CLK106_2 has a small overshoot that rises to 3.5
volts and some ringing during the low state. The actual rise time measured by the
oscilloscope for the load waveform of CLK106_2 is 1.10 ns. The ringing during the
low state is not shown in the LineSim waveform. The rise time of the clock driver
from table 2.5 is between 0.5 ns and 1.3 ns. Therefore, LineSim models a maximum
rise time for the clock driver and the real clock driver has a rise time near the
minimum rise time. A slow rise time at the driver will produce clean signals at the
load if the trace is not electrically long. LineSim calculated a total propagation delay
of 778 ps and 981 ps for CLK106_1 and CLK106_2, respectively. When simulating
a maximum rise time of 1.3 ns, CLK106_1 is on the verge of no longer being an
electrically long transmission line, which will cause differences when comparing to
the oscilloscope waveform results.
The LineSim source waveforms for CLK53_1 and CLK53_2 exhibit overshoot,
undershoot, and reflections, and the rise times are approximately 1 ns. The
56


oscilloscope source waveforms for CLK53_1 and CLK53_2 also exhibit overshoot,
undershoot, and reflections. The actual rise times of CLK53_1 and CLK53_2, as
measured by the oscilloscope, are 1.19 ns and 1.27 ns, respectively. The LineSim and
oscilloscope source waveforms do not compare exactly, but they do show similar
characteristics. The LineSim load waveforms for CLK53_1 and CLK53_2 also
contain overshoot, undershoot, and reflections. The rise times are approximately 1.2
ns. The oscilloscope load waveform for CLK53_1 contains overshoot, undershoot,
and reflections. The actual rise time measured for the load waveform of CLK53_1 is
1.14 ns. The oscilloscope load waveform for CLK53_2 also has overshoot,
undershoot, and reflections. The actual rise time measured for the load waveform of
CLK53_2 is 1.25 ns. The LineSim and oscilloscope load waveforms do not compare
exactly, but they do show similar characteristics.
The LineSim results and oscilloscope measurements have differences and
similarities. The differences between the LineSim and oscilloscope waveforms could
be from the oscilloscope measuring noise that has entered the clock circuits through
the power supply, or the ground lead of the probe not being a true ground. The
LineSim simulation models used for the IC devices may not be accurate enough to
show the level of overshoot, undershoot, and reflections that a real circuit exhibits.
The similarities between the LineSim results and the oscilloscope measurements are
shown at the load waveforms. The LineSim and oscilloscope measurements of the
CLK106_1 and CLK106_2 load waveforms agree in that they both show well-
behaved signals for the source termination that is used. The LineSim and
oscilloscope measurements of the CLK53_1 and CLK53_2 load waveforms also
agree in that they both show overshoot, undershoot, and ringing for the source
termination that is used.
57


7. Conclusions
The main objectives of this thesis were to find the accuracy of the theoretical
equations and the accuracy of the LineSim simulator in predicting the parameters and
waveforms of high-speed clock circuits fabricated in a PCB. The results from the
theoretical stripline equations compare very well with the simulator results. The
stripline equations are accurate to within 1 % of the LineSim results. The results
from the microstrip equations do not compare as well. The microstrip equations are
accurate to within 6.7 % of the LineSim results when calculating capacitance. The
other microstrip equations are accurate to within 2.3 % of the LineSim results. When
calculating characteristic impedance, propagation delay, inductance, and capacitance
for stripline routed traces, the theoretical equations are as accurate as a professional
simulator used in industry. When calculating these parameters for microstrip routed
traces, the theoretical equations are not as accurate, but they still give good
approximate results.
Calculating the propagation delay using the theoretical equations did not compare
well with the oscilloscope results. The theoretical calculations varied between 35 %
and 3 % when compared to the oscilloscope measurements. The main reason for this
difference is that the theoretical equations calculate propagation delays for traces
only. The propagation delay through the series resistor and behavior of the driver,
receiver, and scope probe did not factor into the theoretical propagation delay
equations.
The LineSim calculated propagation delays compare well with the oscilloscope
measurements for the 106.25 MHz clocks. The propagation delays calculated by
LineSim are within the 100 ps accuracy of the TDS 684B measurements. However,
the LineSim calculated propagation delays for the 53.125 MHz clocks have an
accuracy between 3.0 % and 4.8 % when compared to the oscilloscope
measurements. The difference in these measurements could be from the simulator
models used for the driver and receiver devices. These models may not precisely
simulate the real ICs.
The LineSim waveforms are a rough estimate of the actual waveforms when
compared to the oscilloscope. The LineSim simulator modeled a maximum rise time
for the clock driver of the 106.25 MHz clocks, and the oscilloscope measured a rise
time near the minimum specified for the clock driver. This will change the
characteristics of the source and load waveforms. The LineSim simulator is on the
verge of not modeling an electrically long transmission line for CLK106_1 because
58


the rise time from the clock driver is almost equal to the round-trip propagation delay.
The LineSim simulator modeled a similar rise time for the clock driver of the 53.125
MHz clocks as the oscilloscope measured. The waveforms compare better between
LineSim and the oscillosope measurements for the 53.125 MHz clocks than for the
106.25 MHz clocks.
The Ins skew requirements placed on the 106.25 MHz clocks and the 53.125 MHz
clocks were met. The average skew measured by the oscilloscope between
CLK106_1 and CLK160J2 is 285.5 ps. The average skew measured by the
oscilloscope between CLK53_1 and CLK53_2 is 84 ps.
The theoretical equations for stripline traces are very accurate and compare very
well with a professional simulator used in industry. The theoretical equations for
microstrip traces produce marginal results, but give good approximations. The
theoretical equations should only be used for pure trace calculations, because they do
not factor in the behavior of driver or receiver devices.
The LineSim simulator reports good propagation delays for microstrip and
stripline routed traces. Accurate results can be obtained if vias are simulated and high
quality IC device models are used. The waveforms simulated by LineSim are
moderate as far as showing how the signal behaves in a real circuit. The main issue
with simulators is obtaining accurate simulation models of ICs and discrete
components. All of the models used in simulation were obtained from the
manufacturer or the LineSim library, but they are still not guaranteed to be precise
representations of the actual ICs. LineSim does not simulate the exact waveforms
that an oscilloscope will measure, but the simulation waveforms do show
characteristics of real circuit behavior. LineSim should be used for pure trace
calculations and for simulation when high quality IC device models and discrete
component models are used.
To improve upon this thesis and to obtain better results, longer microstrip and
stripline traces, such as 6 to 12 inches, could be simulated and fabricated. These
longer traces may show more similarities between the microstrip theoretical results
and simulation results, as well as between the simulator results and oscilloscope
measurements. The longer traces would create definite electrically long transmission
lines for the 106.25 MHz clocks. Clock traces with no vias in the traces will produce
better comparison results as well. Higher quality simulation models of the drivers
and receivers will produce more accurate simulation results. Measurements of a PCB
with only a single clock circuit may compare better to theoretical and simulation
59


results, because there are less clocks and signals switching at the same time and less
noise on the board.
60


Appendix A. Matlab Programs
The following program was used to calculate parameters for the microstrip routed
traces.
function [EEFF,WE,ZMSTRIP,PMSTRIP,PTOT,LMSTRIP,CMSTRIP] =
microstrip(h,w,t,er,L)
%microstrip Equations For Microstrip Routed Traces
% microstrip Uses equations from Johnson and Graham to calculate:
% Effective relative permittivity, Effective electrical
% trace width, Microstip char, impedance. Microstrip
% prop, delay. Microstrip trace inductance, and
% Microstrip trace capacitance.
% INPUT: h Trace height above ground (inches)
% w Trace width (inches)
% t Trace thickness (inches)
% er relative permittivity of material between trace and
% ground plane
% (dimensionless)
% L Trace length (inches)
% OUTPUTS: EEFF Effective relative permittivity
% WE Effective electrical trace width
% ZMSTRIP - Microstrip characteristic impedance
% PMSTRIP - Microstrip propagation delay (secs/inch)
% PTOT - Total propagaton delay (seconds)
% LMSTRIP - Microstrip trace inductance
% CMSTRIP - Microstrip trace capacitance
%
%Mike McDonnell, Master Thesis, Spring 2000
%Effective relative permittivity
% Skinny Trace (w a=(er + l)/2;
b=(er 1)/2;
c=(((12*h)/w) + 1)A((-1)*(0.5));
d=((1 (w/h))~2) 0.04;
E_skny = a + b*(c + d) ;
% Wide Trace (w>h)
E_wide = a + (b*c);
if (w>h)
E_temp = E_wide;
else
E_temp = E_skny;
end
61


%EEFF calculation
e = (er-1)*(t/h);
f = 4.6 sqrt(w/h);
EEFF = E_temp (e/f);
%Effective trace width
% Skinny traces (2 pi w < h)
a=(1+log(((4*pi*w)/t)));
b = (1.25 t)/pi;
WE_skny = w + (b*a);
% Wide traces (2 pi w > h)
c=(1+log(((2 *h)/1)));
WE_wide = w + (b*c);
%WE calculation
d=h/(2*pi);
if (w>d)
WE = WE_wide;
else
WE = WE_skny;
end
%Characteristic Impedance
% Skinny traces (w a=(8*h)/WE;
b=WE/(4*h);
ZMS_skny=60 log(a+b);
% Wide traces (w>h)
a=0.667 log((WE/h) + 1.444)
b=(WE/h)+1.393 + a;
ZMS_wide = (120*pi)/b;
if (w>h)
ZMS_temp = ZMS_wide;
else
ZMS_temp = ZMS_skny;
end
%ZMSTRIP calculation
ZMSTRIP = ZMS_temp/sqrt(EEFF)
%Propagation Delay (sec/inch)
PMSTRIP = 84.72*(10A(-12)) *
sqrt(EEFF)
62


%Total Propagtion Delay
PTOT = PMSTRIP L;
%Inductance
LMSTRIP = PMSTRIP ZMSTRIP L;
%Capacitance
CMSTRIP = PMSTRIP/ZMSTRIP L;
The following programs were used to calculate parameters for the stripline routed
traces.
function [ZS] = zstrip(b,w,t,er)
%zstrip Equations Characteristic Impedance of Stripline Routed
% Traces
% zstrip Uses equations from Johnson and Graham.
% INPUTS: b Separation between ground planes (inches)
% w Trace width (inches)
% t Trace thickness (inches)
% er relative permittivity of material between ground
% planes (dimensionless)
% OUTPUT: ZS Stripline characteristic impedance
%
%Mike McDonnell, Master Thesis, Spring 2000
%Characteristic Impedance
% Skinny traces (w/b < 0.35)
a = t/(pi*w);
c = a*(l + log((4*pi*w)/t));
d = 0.255*((t/w)A2);
ZSTR_K1 = (w/2)*(1+c+d);
temp = (4*b)/(pi*ZSTR_Kl);
ZSTR_skny = (60/sqrt(er)) log(temp);
% Wide traces (w/b > 0.35)
a = 1 (t/b);
c = log((1/(aA2))-1);
ZSTR_K2 = ((2/a)*log((l/a)+l)) ((l/a)-l)*c;
d = {(w/b)/a) + (ZSTR_K2/pi);
ZSTR_wide = (94.15/d)*(l/sqrt(er));
if (w > (0.35*b))
63


ZS = ZSTR_wide;
else
ZS = ZSTR_skny;
end
function [ ZS, ZOFFSET,PSTRIP,PTOT,LSTRIP,LOSTRIP,CSTRIP,COSTRIP] =
stripline(hi, h2, b, w, t, er, L)
%stripline Equations For Stripline Routed Traces
stripline Uses equations from Johnson and Graham to calculate:
Stripline char, impedance, Offset stripline char,
imp.. Stripline propagation delay. Total prop delay.
Stripline trace inductance, Offset stripline
inductance. Stripline trace capacitance. Offset
stripline capacitance
The function ZSTRIP is called from this function
INPUT:
hi
h2
b
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%
%Mike McDonnell, Master Thesis, Spring 2000
OUTPUTS:
- Trace height above lower ground plane (inches)
- Trace height below upper ground plane (inches)
- Separation between ground planes (inches)
w Trace width (inches)
t Trace thickness (inches)
er relative permittivity of material between ground
planes (dimensionless)
L Trace length (inches)
Stripline characteristic impedance
Offset Stripline characteristic Impedance
Stripline propagation delay (secs/inch)
Total propagation delay (seconds)
Stripline trace inductance
Offset Stripline inductance
Stripline trace capacitance
Offset stripline capacitance
ZSTRIP
ZOFFSET
PSTRIP
PTOT
LSTRIP
LOSTRIP
CSTRIP
COSTRIP
%Get Stripline Characteristic Impedance
[ZS] = ZSTRIP(b,w,t,er);
%Offset Characteristic Impedance
paraml = (2*hl) + t;
param2 = (2*h2) + t;
[ZS1] = ZSTRIP(paraml,w,t,er);
[ZS2] = ZSTRIP(param2,w,t,er);
64


ZOFFSET
(2*ZS1*ZS2)/(ZS1 + ZS2);
%Propagation Delay (sec/inch)
PSTRIP = 84.72*(10A(-12)) sqrt(er);
%Total Propagtion Delay
PTOT = PSTRIP L;
%Inductance
LSTRIP = PSTRIP ZS L;
LOSTRIP = PSTRIP ZOFFSET L;
%Capac i tance
CSTRIP = (PSTRIP/ZS) L;
COSTRIP = (PSTRIP/ZOFFSET) L;
65


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