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On-wafer measurement and characterization of p-mosfets

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On-wafer measurement and characterization of p-mosfets
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Farhoodi, Farnaz
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English
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xi, 67 leaves : illustrations ; 28 cm

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LabVIEW ( lcsh )
LabVIEW ( fast )
Metal oxide semiconductor field-effect transistors ( lcsh )
Semiconductor wafers ( lcsh )
Metal oxide semiconductor field-effect transistors ( fast )
Semiconductor wafers ( fast )
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bibliography ( marcgt )
theses ( marcgt )
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Includes bibliographical references (leaves 66-67).
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Department of Electrical Engineering
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by Farnaz Farhoodi.

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|University of Colorado Denver
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Auraria Library
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Full Text
ON-WAFER MEASUREMENT AND CHARACTERIZATION OF
P-MOSFETS
by
Farnaz Farhoodi
B.S., University of Colorado Denver, 2006
A thesis submitted to the
University of Colorado Denver
in partial fulfillment
of the requirements for the degree of
Master of Science in Electrical Engineering
2009


This thesis for the Master of Science
degree by
Famaz Farhoodi
has been approved
by
Dr. Hamid Fardi
Dr. Miloje Radenkovic

Dr. Titsa Papantoni

Date


Farhoodi, Famaz (M.S., Electrical Engineering)
On-Wafer Measurements and Characterization of a P-MOSFET
Thesis directed by Professor Hamid Fardi
ABSTRACT
The DC and AC measurements and characterization of p-channel
Metal Oxide Semiconductor Field Effect Transistor (P-MOSFET) are
executed through LabView (Laboratory Virtual Instrumentation
Engineering Workbench) code design and instrumentation, where
experimental results exhibit close agreement with the basic theoretical
model of MOS transistors. The objective of this thesis is the understanding
of the physics and the operation of MOSFETs as well as the extraction of
their characterization parameters via current-voltage (I-V) and
capacitance-voltage (C-V) on-wafer microprobe measurements. Three
different instrumentation setups were deployed, to determine Id-Vsg, Id-
Vsd and C-V characterization of an in-house fabricated P-MOSFET. The
LabView codes created for each measurement setup allowed for remote
controlled equipments and data collection. The MOSFET parameters
analyzed were: threshold voltage, source-drain resistance,
transconductance, depletion thickness representing the source-drain
doping depth and oxide thickness. These parameters are major
characterization features of the P-MOS transistor. The measurement
results obtained via the LabView code design and the micro probe station
were in agreement with the results predicted by the basic theoretical
MOSFET model.


This abstract accurately represents the content of the candidates thesis. I
recommend its publication.
Signed
Dr. Hamid Fardi


DEDICATION
I dedicate this thesis to the most loved person in my life, Ashkan, who
taught me love and pain go hand in hand. His love made me to touch the
sky.


ACKNOWLEDGMENT
Finally, I must express my thanks to my mom, my brother and my dearest
uncle Abbas. Thank you for believing in me and supporting me. I also
would like to thank Dr. Hamid Fardi for advising, teaching and leading me
through each step of this project. Without his guidance I would have never
finished this thesis. In addition, I want to thank Teresa Osminer for all her
help and support.


TABLE OF CONTENTS
Figures......................................................................ix
Chapter
1. Introduction...........................................................1
2. Physical Background...................................................10
2.1. Semiconductor.........................................................10
2.2. Transistors...........................................................11
2.3. Functionality and Physical Operation of P-MOSFET......................12
2.3.1. MOSFET Structure......................................................12
2.3.2. MOSFET Operation......................................................13
2.3.3. P-MOSFET Bias.........................................................15
2.3.4. P-MOSFET Capacitance..................................................19
3. Experimental Procedure................................................21
3.1. Instrumentation.......................................................21
3.1.1. I-V Instrumentation Setup.............................................22
3.1.2. C-V Instrumentation Setup.............................................27
3.2. Fabrication of P-MOS Transistor.......................................29
4. Lab View Programming and Development..................................32
vii


4.1. I-V LabView Code..................................................34
4.2. C-V LabView Code..................................................44
5. Result and Discussion.............................................50
5.1. I-V Analysis......................................................51
5.2. C-V Analysis......................................................55
6. Conclusion........................................................64
References...............................................................66
viii


FIGURES
Figure
1-1: Schematic of Intrinsic Gate to Source Capacitance Measurement of a SOI
MOSFET [1]............................................................3
1-2: Test structure and Operation of the Proposed Novel CBCM Technique for
Intrinsic Gate to Source Capacitance Extraction [2]...................4
1-3: Gate-Body Capacitance Measurement Setup [6]............................5
1-4: Test Equipment and Circuit Setup to Measure I-V Characteristic of the MOSFET
Device [7].............................................................6
1- 5: Measurement Apparatus for Measurement without Self-heating [8]........7
2- 1: Schematic Diagram of a P-Channel Enhancement Mode MOSFET............13
2-2: The Cross Section after a Hole Inversion Layer Created................14
2-3: The P-Channel Enhancement Mode MOSFET with a Gate Voltage Less than the
Threshold Voltage (with respect to the sign)..........................15
2-4: P-Channel Enhancement Mode MOSFET with an Applied Gate Voltage Greater
than Threshold Voltage Causing Current Flow...........................16
2-5: iD versus vSD with Saturation and Triode Regions......................17
2-6: P-MOSFET Symbol.......................................................19
2-7: Simplified P-MOSFET Symbol............................................19
2- 8: Bulk Capacitance Model for P-MOSFET.................................20
3- 1: Schematic of a P-MOSFET Showing the Biasing for ID versus VSg.......22
3-2: Schematic of Instrumentation Setup Id versus VSg Measurement..........24
IX


3-3: Wafer with Test Structures
25
3-4: Schematic of the Instrumentation Setup for ID versus Vsd Measurement.....25
3-5: Schematic of the Instrumentation and Setup for Id versus Vsd.............26
3- 6: Schematic of the Instruments and Setup for Capacitance Voltage Measurement
(CGS).....................................................................28
4- 1: Flat Sequence Structure.................................................34
4-2: GPIB Write Function for Address 5........................................35
4-3 GPIB Write Function for Address 6.........................................35
4-4: GPIB Write Function for Address 22.......................................35
4-5: Number to String Function to Set the Value for Address 5.................36
4-6: For Loop to Increment and with Flat Sequence Structure Inside to Measure the
Current...................................................................37
4-7: Write to Spreadsheet Function to Save Data................................39
4-8: GPIB Write Function to Turn off Address 6.................................40
4-9: Front Panel...............................................................41
4-10: Flat Sequence Structure for Id-Vds.......................................42
4-11: Front Panel for Id-Vds...................................................43
4-12: Flat Sequence Structure for C-V.........................................44
4-13: GPIB Write for Address 9.................................................45
4-14: GPIB Write for Address 17................................................45
4-15: For Loop with a Flat Sequence Structure..................................46
x


4-16: Write to Spread Sheet Function to Save Data...........................47
4- 17: Front Panel for C-V..................................................48
5- 1: Source to Drain Current versus Source to Drain Voltage...............51
5-2: Source to Drain Current versus Source to Gate Voltage..................53
5-3: Square Root of Source-Drain Current versus Source-Gate Voltage.........54
5-4: Measured Characteristics of a Drain-Bulk/Source Diode..................55
5-5: Gate-Source Capacitance versus Gate to Source Voltage (High Frequency).56
5-6: On-Wafer P-MOSFET (SEM Microscope Picture..............................57
5-7: On-Wafer Large Capacitor (Large MID CAP)...............................60
5-8: Capacitance versus Voltage on the Large MID CAP........................60
5-9: Drain-Bulk/Source Capacitance..........................................61
5-10: Measured Drain to Bulk/Source Capacitance versus Drain to Bulk/Source
Voltage................................................................62
xi


1. Introduction
Compared to some other transistors such as Bipolar Junction Transistors,
metal oxide semiconductor field effect transistors (MOSFETs) can be made thin film
and microscopic/nanoscopic, occupying a very small thin surface portion on an
integrated circuit (IC) chip. In the 1970s and 80s, MOSFETs were the leading source
of another electronics revolution, in which the microprocessors and memories have
been used to make powerful personal computers as well as advanced calculators. The
basic components of current digital circuits are MOSFETs with, eliminating the
requirement for resistors or diodes, where in such circuits the MOSFETs act as on
and off switches. In analog circuits MOSFETs are used to amplify or control with
continuous range of inputs and outputs. It should be noted that the MOSFETs
technology is based on an improved bipolar transistors technology. As a result,
MOSFETs are one of the most commonly used semiconductor devices today. The
most widely used type of a MOSFET is a complementary MOSFET (C-MOSFET),
made of a n-channel MOSFET and a p-channel MOSFET. In the use of a p-channel
MOSFET device its characteristics based on instrumentations and measurements
become significant. The specific construction of an IC made of MOSFETs depends
on its application, such as medical, military, domestic, etc. As a result, the
1


characterization of MOSFET parameters such as resistance, transconductance, and
parasitic capacitances become critical.
The capacitance measurements of MOSFETs play an important role in the
modeling and the designing of MOSFET circuits and ICs that deal with time variant
signals. Scientists have been interested in such measurements for a long time. There
are many parameters influencing the capacitance characteristics of MOSFETs, such
as type of materials, size, shape and technology. Referring to previous works,
different methods have been undertaken to extract capacitance versus voltage
characteristic of different MOSFETs. Both terminal current versus voltage (I-V)
characteristics and capacitance versus voltage (C-V) measurements are major parts of
this thesis project.
The intrinsic gate capacitance of Silicon On Insulator (SOI) MOSFETs in the
nonsaturation region is measured in [1], where observations show that there are
differences in conventional bulk characteristics, which is clarified in strong inversion
and sub-threshold operation. As a result, the source and drain junction capacitances
should be considered in small and large signal models, triggering the inversion
properties of MOSFETs. Figure 1-1 shows the schematic of the gate-source
capacitance measurement method, referenced in 11].
9


r---------------------
Figure 1-1: Schematic of Intrinsic Gate to Source Capacitance Measurement of a SOI MOSFET
Ml
There are other approaches for measuring C-V. A charge-based capacitance
measurement (CBCM) method is applied to extract the intrinsic gate-source
capacitance of MOSFET devices [2], Also, the split C-V method is used in [3]-[5] to
extract the mobility of devices with different channel thicknesses. Figure 1-2
represents the test structure to extract the gate-source capacitance of a device.
3


V =0 4V
Figure 1-2: Test structure and Operation of the Proposed Novel CBCM Technique for Intrinsic
Gate to Source Capacitance Extraction |2|
Based on the instrumentation of Figure 1-3, using an AC signal at the gate, the
AC current is measured at grounded substrate by LCR meter [6]. Therefore, the gate-
source and the gate-drain capacitance cause a no current flow through the source and
drain; hence the capacitance between gate and the body is measured.
4


Figure 1-3: Gate-Body Capacitance Measurement Setup |6|
Other important characterizations of a MOSFET are I-V measurements and
the threshold voltage measurement which deals with the functionality of the
transistors working region. There are several measurement techniques that are used
in the past for I-V characterization of MOSFETs. Figure 1-4 presents the test platform
to measure I-V characteristic of the MOSFET device. This method shows an
improved ultra fast version of the measurement method for threshold voltage in a
5


MOSFET. It captures gate voltage versus drain current within 1 ps to obtain the
threshold voltage [7],
Pulse
Generator
Figure 1-4: Test Equipment and Circuit Setup to Measure I-V Characteristic of the MOSFET
Device |7|
In order to increase the measurement accuracy, self-heating effects must be
eliminated, since, typically, power MOSFETs tend to heat up while performing the
measurement. Figure 1-5 shows the measurement system used to get rid of self-
heating effect [8], In this method, a short voltage pulse is transmitted through the gate
of the MOSFET and the resultant voltage drop at the drain is measured. In addition,
to eliminate self-heating, short time scaled measurements and long relaxation
between each of the measurements are needed; this is done with a pulsed I-V system.
6


OSCIU.OSCOM
Figure 1-5: Measurement Apparatus for Measurement without Self-heating [8|
Most of the discussed measurement techniques are used for discrete devices,
where only a single transistor is characterized. There are other approaches that utilize
a variety of device measurement techniques, right at the fabrication site, using die and
wafers. Furthermore, on-wafer measurements are very important for fabricating and
testing, since they provide a rapid and readily available measurement approach for
key device parameters and initial design objective.
This thesis focuses on a Laboratory Virtual Instrument Engineering
Workbench (LabView) code and instrumentation, to extract the MOSFET device
characteristics and parameters on wafer, using a micro probe station. The code mainly
7


controls the instruments remotely such as the power supplies and reads off the Amp
and Capacitance meters. For the I-V characterization, there is a bias between drain
and source, a voltage is swept at the gate of the transistor and the current at the drain
terminal is measured. Additionally, the different terminals of the MOSFET are biased
in order to obtain the junction capacitances accordingly. Finally, the characteristic
parameters based on the measured values such as threshold voltage, drain-source on-
state resistance, gate-source capacitance, drain-source capacitance and drain-gate
capacitance are acquired, to fully realize device design and processing.
The physics and operation of MOSFET are discussed in chapter 2. The
schema of the measurement setup and the details of the measurements are discussed
in chapter 3. This thesis project mainly concentrates on the I-V and C-V
measurements used to acquire characterizations of MOSFETs. The experimental
procedure of the measurements, including the LabView code development, is
discussed in chapter 4. Results and discussion of the data as well as the analysis are
discussed in chapter 5. Chapter 6 concludes the work performed in this thesis report.
Results from this study provide a simple instrumentation approach to the
characterization on an on-wafer transistor. Additionally, experimental and theoretical
information is presented regarding the measurements of significant key electrical
parameters of a MOSFET, using on-wafer micro probe station. This work
8


demonstrates procedures for obtaining data and device information through setups
and instrumentations, using LabView and the probes under microscope.
9


2. Physical Background
2.1. Semiconductor
The materials used in electronic devices are classified according to their
resistivity. Materials that have a resistivity less than 10' O-cm are considered as
conductors, while materials with resistivities greater than 105 Q-cm are called
insulators. Materials whose resitivity falls in the middle region are classified as
semiconductors, where resistivity can be altered via the introduction of dopants.
Semiconductor devices, such as MOSFETs, are characterized by the same electronic
properties as of the semiconductor materials. Mainly silicon, gallium arsenide, and
germanium are the primary semiconductor materials used in semiconductor devices,
for instance such as the ICs. Silicon is the semiconductor material of choice,
primarily used for MOSFETs. The technology of MOSFET is so evolved and
perfected that can have up to more than a million devices fabricated and coupled on a
small size semiconductor substrate [9],
In section 2.2, an introductory remark is presented on the state of the art
transistors, and in section 2.3 the physical operation and functionality of MOSFETs
are explained in details.
10


2.2. Transistors
By referring to semiconductor devices, mainly transistors are referenced. They
may be used as: current, voltage and power switches, time variant signal amplifiers
and digital logic circuits. Over the time, transistors went through geometry, structure,
and performance changes and are categorized by their conduction type, related to
their structure and material. Commonly used devices which differ in their structures
are the Bipolar Junction Transistor (BJT), the Junction Field Effect Transistor (JFET)
and the Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Many
textbooks and device literatures address their importance in the semiconductor
industry [9],
Field Effect Transistors are composed of three terminals called source, drain
and gate. The current flow between the drain and the source is controlled by the
voltage between the gate and the source and the bias between the source and the
drain. The appropriate biasing of gate and source creates an electric field that affects
the size and shape of the conductive channel between the source and the drain. The
presence of the oxide layer provides an electric field that ideally produces no current
emission through the gate. In addition, in MOSFETs, above the threshold voltage, an
inversion layer is formed under the oxide layer that conducts mobile carriers (holes in
a p-channel MOSFET and electrons in a n-channel MOSFET) from source to drain.
11


As mentioned above, the conductivity of the inversion layer is controlled by the
voltage applied to the gate with respect to the source [9], The focus of this thesis
project is on p-channel MOSFETs with minimal processing steps and the availability
of an in-house device fabrication.
2.3. Functionality and Physical Operation of P-MOSFET
2.3.1. MOSFET Structure
A MOSFET is constructed from three major parts: source, drain, and gate.
The cross section schema of a simplified p-channel enhancement mode MOSFET is
shown in Figure 2-1, where a negative gate voltage bias creates an inversion p-
channel layer above threshold voltage. Besides processing parameters such as type of
semiconductor, doping density of substrate, type of metal gate, the key structural
parameters controlling the performance of a P-MOSFET device are channel length
(L), channel width (W), and the thickness of oxide (tox). The body is made of n-type
silicon substrate. Heavily doped p^ source and p+ drain region provide less resistivity
and a minimum amount of series resistance to the metal electrodes. The device under
12


the test is fabricated using four masks; and processing steps taken are diffusion,
oxidation, vias, and metallization.
Source VSG vsd
Figure 2-1: Schematic Diagram of a P-Channel Enhancement Mode MOSFET
2.3.2. MOSFET Operation
Metal-Oxide-Semiconductors act like capacitors with a dielectric oxide (Si02)
sandwiched between conduction metal gate and conducting n-type substrate. At zero
bias, no charge is established. As a result, there is no current flow form source to
drain. In order to turn on the transistor a gate voltage needs to be applied to create an
inversion layer, charging the capacitance for a current flow between source and drain.
13


In addition, the isolation under the oxide layer in substrate prevents the current flow
from the body region to the source and drain regions, minimizing the leakage effect.
Gate bias controls the density of the holes which are collected and formed under the
oxide layer. Figure 2-2 shows a schema of a P-MOSFET device where the hole
inversion layer is formed by an applied bias to the gate, creating an electric field. The
new formed p-type layer in n-type substrate creates a p-channel between source and
drain under the influence of gate electric field. This satisfies the functionality of P-
MOSFETs. By adjusting the voltage between source and drain terminals, it is possible
to conduct holes through the p-channel to provide current flow between source and
drain.
G
Figure 2-2: The Cross Section after a Hole Inversion Layer Created
14


2.3.3. P-MOSFET Bias
A MOSFET requires a certain gate voltage (VTp) to create an inversion
charge. Unlike N-MOSFET, for the P-MOSFET enhancement- mode, the
threshold voltage has to have negative polarity with respect to the bulk/source,
to create the inversion charge layer. If the gate voltage is less than VTp with
respect to the sign, there is no current flow in the device, therefore the
transistor is off, Figure 2-3. By increasing the gate voltage in the negative
direction, a hole inversion layer is created. Figure 2-4 illustrates the gate
voltage being greater than the threshold voltage (with respect to the sign)
causing, a current flow from source to drain [10].
Figure 2-3: The P-Channel Enhancement Mode MOSFET with a Gate Voltage Less than the
S
Space-
charge regions
n
Threshold Voltage (with respect to the sign)
15


Figure 2-4: P-Channel Enhancement Mode MOSFET with an Applied Gate Voltage Greater
than Threshold Voltage Causing Current Flow
The density of holes in the inversion layer is controlled by the gate voltage and this
adjusts the amount of current flow available from source to drain. Figure 2-5. As the
density of hole carriers in the inversion layer increases, the source-drain current
increases up to a saturation point and stays constant beyond. Using a simple KVL for
a MOSFET:
vSD vsa = VTP , (2.1)
where, in an ideal P-MOSFET, increasing the source-drain voltage (VSd) in the
negative direction causes the source-drain current (in) to reach a constant value for
16


VsD>VSD(Sat) (with respect to sign). This specific characteristic region of iD versus vSD
is called the saturation region, Figure 2-5.
Figure 2-5: iD versus vSD with Saturation and Triode Regions
In the case of VSd < VSD The ideal relationship between source-drain current and voltage in triode region is
given by
17


h> = KP [2(v,v; + Vn, )vsn v2sl) ] (2.2)
Also, the current-voltage relationship in the saturation region (where Vsg > Vjp) is:
h> ~ Kp(vSG + Vrp) (2.3)
In the above equations, the parameter Kp is called the conduction parameter for the
device and is given by
II w 1^- (2.4)
where kp = Cox /up and (2.5)
C SOX ^ OX ~ 1 OX (2.6)
where Cox is the oxide capacitance per unit area, where tox is the oxide thickness, and
£ox is the dielectric permittivity. In equation 2.5, pp is the mobility of the holes in the
inversion layer. The conventional symbolic representation of a p-channel MOSFET is
shown in Figure 2-6, while Figure 2-7 shows the simplified P-MOSFET model where
the body terminal is connected to source terminal.
18


s
o
S
o
VSG
GoI +
f-*--O B vSD
i
iD
Go
+
VSG
+
J'D
6
D
6
D
Figure 2-6: P-MOSFET Symbol Figure 2-7: Simplified P-MOSFET Symbol
2.3.4. P-MOSFET Capacitance
MOSFETs are also characterized by their bulk lumped capacitances between
the terminals, such as Cos, Cgd, Cgb. Cdb and Cos- These capacitances show different
behaviors, once biasing and AC small signal condition are applied, Figure 2-8 [11].
The AC capacitance measurement of MOSFETs provides valuable insight into the
electrical characteristics and the understanding of the oxide-silicon interface and the
process technology of MOSFET used. C-V measurement is a well developed and
standard practice for monitoring fabrication processes, both at research laboratories
and the industry. The instrumentation procedure and analysis of C-V measurements
are discussed in chapter 3 and 4.
19


D
G
B
Figure 2-8: Bulk Capacitance Model for P-MOSFET
20


3. Experimental Procedure
This chapter reports the development of the instrumentation for measuring
both DC and AC characteristics of P-MOSFET on probe station, using LabView
(Laboratory Virtual Instrument Engineering Workbench) software codes. The detail
of the LabView instrumentation code and the program development are discussed in
chapter 4. The fabrication of the P-MOSFET is discussed below, in section 3.2.
3.1. Instrumentation
For measuring and characterizing a P-MOSFET (enhancement mode) on
wafer, basic instruments such as power supplies, multi meters and a probe station are
required. The instruments were controlled remotely via LabView codes and GPIBs
(General Purpose Interface Bus). The characterization requires three major
measurement setups such as Id versus VSg, Id versus Vsd, and capacitance versus
voltage. Each of these measurements needs different instrumentation and a detailed
LabView programming setup.
21


3.1.1. I-V Instrumentation Setup
Id versus Vsg measurement necessitates a controlled negative bias between
the drain and the source, where the source terminal is grounded. Furthermore, with an
Amp meter in series, the current Id can be measured. This is done, while the voltage
between the gate and the source terminals is swept, Figure 3-1. All measured data are
averaged over a number of cycles assigned by the code, where the user is taking the
measurements.
Figure 3-1: Schematic of a P-MOSFET Showing the Biasing for ID versus VSG
Furthermore, the LabView code written for Id versus Vsg sets the power supply
(address 5) to a constant voltage that can be chosen manually and is applied to the
drain terminal of the transistor. In addition, the LabView code also controls the other
power supply (address 6) incrementing from 0 up to -8 Volts, to supply bias voltage
to the gate terminal of the FET. Likewise, the multi-meter (address 22) is controlled
22


remotely by the LabView, and measures the negative current flowing between the
source and the drain terminals. The outputs of address 5, address 6, and address 22
are connected to the probes that go directly on the test wafer, Figure 3-2. The wafer is
a test structure fabricated in-house with components such as capacitor and different
size MOSFETS of different aspect ratios, Figure 3-3. All these design components
help in improving the fabrication process and reducing the design difficulties. The
obtained data from the probes (Id versus Vsg) are graphed and collected in a post
processing program, such as MS Excel spread sheet.
23


Figure 3-2: Schematic of Instrumentation Setup ID versus VSG Measurement
24


Figure 3-3: Wafer with Test Structures
Figure 3-4 shows the Id versus VDs measurement, similarly to Id versus Vos
measurement, as explained earlier in this chapter. The same instruments are used with
the differences being that the gate gets a constant negative voltage and the voltage
between the drain and the source terminals are negatively swept. Likewise, the
current flow between the drain and the source terminals is measured through a multi-
meter.
Figure 3-4: Schematic of the Instrumentation Setup for ID versus VSD Measurement
25


The instruments are also controlled remotely by the LabView code, which is here
only slightly changed as compared to the Id-Vsg code. Figure 3-5 shows, that by
sweeping the voltage between the source and the drain terminals, only the wiring
connected to the power supplies, to the probes and to the P-MOSFET on the wafer
changes.
Figure 3-5: Schematic of the Instrumentation and Setup for ID versus VSD
26


3.1.2. C-V Instrumentation Setup
The Capacitance Voltage measurement is one of the major parts of
characterizing MOSFETs. The approach for this measurement setup requires a power
supply that would sweep the voltage and a capacitance meter that would measure the
capacitance between the two assigned terminals. In addition to the capacitance meter,
a 40Vdc External Voltage Bias Adapter was used to interface between DC and AC
voltage and to also enable the meter to sweep large DC biases by enhancing the
limited bias function capability of the Agilent 4288 capacitance meter. The power
supply is connected to the side of the adapter and the 4 terminals pair test fixtures to
the back of the adapter, Figure 3-6. Furthermore, the four coaxial connectors Lcur
(low current), Lpot (low potential), Hpot (high potential), Hcur (high current) coming
out of the adapter are for the device under test, where Lcur and Lpot are connected
together and go to one probe. Also, Hcur and Hpot are connected and go to the other
probe on the probe station. Depending which two MOSFET terminals the capacitance
is measured, one probe with high side goes to one MOSFET terminal and the other
probe with low side goes to the other terminal. Through the specific C-V LabView
code controls the power supply remotely to sweep the voltage, and measures the
capacitance through the capacitance meter which is connected to a computer. For
different C-V measurements, only the probes change their positions at the MOSFET
27


terminals. For instance, measuring the capacitance between the gate and the source,
the gate obtained the high and the source received the low, while measured data are
used to produce the graph which is computed by the computer through the code.
Figure 3-6: Schematic of the Instruments and Setup for Capacitance Voltage Measurement (CGs)
28


3.2. Fabrication of P-MOS Transistor
P-MOSFETs are usually fabricated at research universities, due to the
simplicity of the design requiring a minimum number of physical processing steps. In
P-MOSFET design and fabrication. Aluminum metal is used for both gate and
source/drain contacts, where in the semiconductor industry, a poly gate is used for
gate contact towards the control of the threshold voltage; additional poly mask steps
are then required, however, resulting in increased processing complexity.
The P-MOSFET characterized in this thesis report is an in-house wafer
fabricated at CU Boulder laboratories. Fabrication of different steps such as
oxidation, field oxide etch, prediposition, deglaze, low temperature oxidation (LTO),
gate oxide etch, gate oxidation, vial hole etch, metal deposition, metal etch, and metal
anneal were all used to achieve a working transistor.
The following outlines an overview of the processing steps in fabrication of a
P-MOS transistor. An n-type silicon wafer with a low resistivity of 2 to 5 ohm-cm is
used that has been oxidized in a steam atmosphere. For the field oxide etch, a positive
resist is spinned on the back of the wafer and gets prebaked on the hotplate. Unlike
the back of the wafer, the front of the wafer is spinned on with negative resist and
also prebaked on a hotplate with different temperature setting. Following the
softbake, the diffusion mask is used to expose the resist. Additionally, the resist is
29


postbaked and developed. Thereafter, the oxide is etched in buffered oxide etch
(BOE) HF, where the etch time is estimated based on the etch rate and the ratio of
BOE. The resist is stripped off and diffusion of Boron is introduced for deposition
using Boron Nitride (BN) source wafer as dopant source in a diffusion furnace.
Afterward, Fluoroboric Acid (HBF4) is used to deglaze the wafer due to the formation
of glass in diffusion furnace. In order to break up the silica glass, LTO is performed
before etch. Subsequently, with the second mask, negative resist is spinned on,
prebaked, the gate oxide mask aligned, exposed and developed. For the gate oxide
pattern, the oxide is etched in BOE, rinsed and the resist stripped off in acetone
followed by gate oxidation. This device has a gate oxide thickness of about 100 nm.
To make physical contact to the source and the drain Via hole etch was also required.
Following the normal steps of spinning on negative resist, prebake and exposure, Via
patterns on wafer are made with Via mask followed by postbaking and developing.
The wafer is further processed with BOE etch and stripping off the resist. Finally, the
wafer is ready for a metal deposition to produce both contacts to the source and the
drain terminals as well as the gate contact. Vias are filled with metal at this stage and
the gate contact is patterned at the same time using metal mask. Thermal evaporation
is used for Aluminum metal deposition. This time, positive resist is spinned on,
prebaked, the metal pattern on the wafer is exposed using metal mask, and developed.
Unlike negative resist, the exposed regions on wafer remain as hardened areas after
30


the resist is developed. Therefore, the areas exposed will remain after Aluminum
etch, making the source, drain, and gate, where Aluminum metal patterns are realized.
For the completion of the fabrication a metal anneal is performed in forming gas
(N2/H2). All in all, 4 masks were used to fabricate the transistor. A photograph of the
fabricated wafer is shown in Figure 3-2 [12].
Results from this study provide instrumentation technique using Lab View
programming and code design in order to measure MOSFET at DC and AC to obtain
electrical parameters making the characterization of MOSFET on a probe station a
realization. The LabView design code is discussed in the following chapter 4.
31


4. LabView Programming and Development
The Laboratory Virtual Instrumentation Engineering Workbench
(LabView) created by National Instruments, is a graphical programming
language that is used as instrument control software and for data acquisition.
It is the procedure used for measuring signals (for example voltage,
temperature, etc.) and for sending the measurement results to the computer for
analyzing or processing. As compared to the classical programming languages
such C, C++, Pascal, or BASIC, this software allows users to create programs
with graphics. It is mainly used to gather data from an external source [13].
Hewlett Packard developed a General Purpose Interface Bus (GPIB) to
build a communication interface between the computer and the instruments providing
computer control over the test and measurement instruments. GPIB is also used for
computer to computer communications, and using a wider range of instruments that
are GPIB capable. A computer needs to have a GPIB board connected through a
GPIB cable allowing LabView to communicate with the GPIB capable instruments.
Each instrument has a uniquely assigned address, which is usually a number from 0 to
30 [13].
32


Each visual instrument (VI) file is a created program that is or has been
created in LabView software. By clicking on New VI or Open VI, two window
screens open.
One of the windows is called the Front Panel. It consists of controls and indicators.
The controls are the user inputs and the indicators are the outputs of the program [13],
The Front Panel has also a controls palette that makes the useful icons available for
this window. This window has different menus with various input and output controls
such as graph, string, array, Boolean and numeric controls that can be placed
anywhere on this screen. The other window is called Block Diagram and has the
function palette with the appropriate icons useful for that window. The Block
Diagram allows the user to create a program graphically using the functions on the
functions palette. The function palette also provides many menus and submenus with
various functions for as complex and complicated as a program/ code can be.
For the P-MOSFET measurements three different VI codes were considered.
The first code considered is a program that measures source to drain dc current versus
source to gate voltage. The second code is a similar code that measures source to
drain dc current versus source to drain voltage. Using almost the same concept, the
latter code measures the capacitance versus voltage between the terminals at AC
level.
33


4.1. I-V LabView Code
The first VI code created is for source-drain current versus source-gate
voltage ( Id-Vgs*) and is programmed to control the two power supplies and one Amp
meter to read the current. On the Block Diagram window for this code a Flat
Sequence Structure is used to execute and control the instruments sequentially, Figure
4-1.
The first frame contains a GPIB Write function that writes data to the identified
device address 5 to turn the device on. This starts to remote controls the power supply
with address 5, Figure 4-2.
* The bias parameter VGs is the same as VSg with respect to sign due to the limitation and functionality of the instruments used
in this project.
34


B]
data GPIB V Vrite
OUTPUT ON ol
Figure 4-2: GPIB Write Function for Address 5
The following frame commands the same function to the other power supply with
address 6 to accomplish the same with this power supply as well, Figure 4-3.
Ioutput ON
Eh
GPIB Write
data

Figure 4-3 GPIB Write Function for Address 6
Next, the Amp meter gets the same GPIB Write function, but with a command
assigned to reset the meter with and a string address 22 that identifies the Amp meter,
Figure 4-4.
Figure 4-4: GPIB Write Function for Address 22
35


For the next following frame, a control icon is used to set a constant number (value)
that goes to Number-To-Fractional-String function and outputs a string that goes to
Concatenate Strings function with data string named VOLT. The Concatenate Strings
function, concatenates input strings and arrays of strings into only one output string.
This output string goes to GPIB Write function with address 5 and an indicator that
reads the value set to address 5, Figure 4-5.
ItoLtH Concatenate Strings 1
" * ......j. JX- >
yds
M gS
23C P M;^
Iwidth (-)
Number To Fractional String I
f i
Ipredsion (6)1
Figure 4-5: Number to String Function to Set the Value for Address 5
The above described part of the program assigns a constant value to the power supply
with the address 5. Therefore, the value for the voltage between the source and the
drain (VDs) can be set before the program starts to run.
36


For the next part a For Loop generates increments controlled by a number to
pick, Figure 4-6.
Figure 4-6: For Loop to Increment and with Flat Sequence Structure Inside to Measure the
Current
Inside of the For Loop the integers are divided by 100 to create increments of 0.01.
The values go to the Number-To-Fractional-String function that builds a string from
the input values. This string goes to the Concatenate Strings function. The output is
37


read by an indicator and written to address 6 with a GPIB Write function. In addition,
the numbers coming out of the Divider go also to a function called Build Array that
concatenates multiple arrays to 1-D array. The output goes to the Shift Register that
transfers the values from one loop iteration to the next, and feeds back to the same
Build Array function. As a result, this part of the code increments Voltage between
source and the drain (Vgs)-
Another Flat Sequence Structure is created inside the For Loop. The first
frame has a Write GPIB function where the amp meters string address 22 is assigned
to, and a command that tells the meter to measure the current. The next frame is only
delayed by 500 ms, to give the device enough time to determine the value before it
reads it off. The following frame includes a GBIP Read function that reads the byte
count number of 16 bytes from the GPIB device with the address string 22 and a
timeout of 450 ms. The computed output of the GPIB Read goes to the next frame,
where the Frac/Exp String To Number function is used that interprets the characters
in the input string and returns them in numbers. The output value is then read through
an indicator, as the current from (Id) is fed into a Build Array function outside of the
sequence. The output of this function goes to a Shift Register that transfers the values
from one loop iteration to the next iteration and goes back to the same Build Array
function. Additionally, a XY-Graph function needs to be considered, to graph the
incremented Vgs versus the Id at each incremented Vgs value. Therefore, a Bundle
38


function is used with the inputs coming out of the first Build Array function for the
incremented Vgs and the output of the measured Id- Both arrays go into the Bundle
function that assembles a cluster from each element of the arrays, the outcome goes
into and X-Y Graph function. In the next frame, the output array of the Vgs and Id
array go to the another Build Array function, to built a 2-D array and Write To Spread
Sheet function that allows the collected data for these two arrays to be written in an
Excel file, Figure 4-7.
|%12e |
iBuld Array! Write To Spreadsheet Fle.vl
anspose?(no:F)|
Figure 4-7: Write to Spreadsheet Function to Save Data
39


In the last frame, another GPIB Write function is used commanding the power supply
between source and drain to turn off, to save the P-MOS transistor from accidental
short. Figure 4-8.
Ioutput off h
El
GPIB Write
Idatal Lilly
Figure 4-8: GPIB Write Function to Turn off Address 6
The code created allows to set a constant voltage for Vds and to increment
Vgs as well as to concurrently measure the current Id and to finally plot the Id versus
Vos graph and collect the data in an Excel file. The Front Panel for this shows the
plot Id versus Vgs, the incremented values for Vgs, while it concurrently reads the
current. It also allows the user to set a voltage value for VDs, Figure 4-9.
40


Figure 4-9: Front Panel
41


For the Id versus Vds code, the previous code is used with the only difference
being that the GPIB Write function in the first and second frames are switched, to
bias the gate towards saving the transistor from accidental over powering. In addition,
in the Front Panel, the Vos is set to a constant value and Vds is swept. The graph
exhibits Id versus Yds plot, shown in Figure 4-10 and Figure 4-11.
42


mm
Figure 4-11: Front Panel for Id-Vds
43
" || Textlnds Graph Iridcat...
jfelMtf £1^79367033 (F:) ft NA2 79367033 (Fi) j| fl Id Vd on P MOSFCT.vL. j> unfitted Part | flld Vds labvlev* Mkrosof...| B¥^T


4.2. C-V LabView Code
The capacitance versus voltage measurement code created is based on similar
concepts as those in the current versus voltage code, with the difference being that
only two measurement devices are used, such as a capacitance meter and a power
supply, Figure 4-12.
44


This code uses a Flat Sequence Structure function for sequential execution. In
the first sub frame, a GPIB Write function is used with a data string data command to
turn on the power supply with string address 9, Figure 4-13.
laddtess strinal GPIB V Vritel
lor 9
Idata r
lOUTPUTON i
Figure 4-13: GPIB Write for Address 9
The next frame also includes a GPIB Write function with the address string 17 and a
data command to reset the capacitance meter, Figure 4-14.
Figure 4-14: GPIB Write for Address 17
Similarly, the following frame uses the same For Loop function as the current versus
voltage function, to increment voltage at the power supply with the string address 9.
Inside of the loop, there is another Flat Sequence Structure measures the capacitance
at the same time when the voltage is being incremented. It uses the GPIB Write
45


function to tell the capacitance meter to measure the capacitance and wait for 10 ms.
Afterward, a GPIB Read function is used to read byte count number of the bytes form
the address string 17 device ,Figure 4-15.
Figure 4-15: For Loop with a Flat Sequence Structure
The read string data is shown on the Front Panel by an indicator. Additionally, the
sting goes into 3 different Match Pattern functions where each of them searches for
expressions in the data string and in this case splits them into three substrings. The
substrings go the Fract/Exp String To Number function, to return the characters in the
46


string in the form of numbers that is expressed through two indicators, one as the
charge and one as the capacitance. All the data of the incremented voltage and
capacitance read from the meter are mapped onto a XY Graph function, to plot the
graph. After the loop finishes the increments and the measured values from the
capacitance meter, the last frame collects the data of the voltage and the capacitance
in an Excel sheet, Figure 4-16.
|%12e |
Write To
Buid Array 1
m
Itranspose? (no: 13
Figure 4-16: Write to Spread Sheet Function to Save Data
Parallel to Block Diagram window, the Front Panel shows the voltage versus
capacitance in a graph and through indicators the values for voltage, charge, and
capacitance are seen. The number for the voltage-increments can be also set by a
control icon through the number of loops in the Front Panel, to control how far the
Power Supply should sweep, Figure 4-17.
47


Figure 4-17: Front Panel for C-V


The LabView design code and the implementation discussed above, is applied
to the P-MOSFET measurements. The characterization and analysis of the data
obtained is discussed in the next chapter 5.
49


5. Result and Discussion
In previous chapters the physics and the operation of PMOS devices were
introduced. In chapter 3 and 4 the LabView code was developed and the
instrumentation for on-wafer measurement using probe station was designed. This
chapter addresses measurement results obtained using probe station on a test wafer.
The test wafer fabricated at CU Boulder has several PMOS transistors with different
aspect ratio and design geometry. The design of the test wafer itself is aimed at
characterizing the processing and fabrication method.
The DC current versus voltage (I-V) measurement is discussed in section 5.1.
the capacitance versus voltage measurement (C-V) is presented in section 5.2. Results
obtained demonstrate the accuracy of the LabView design code and the precision
used in the instrumentation of the I-V and C-V setup using probe station. Their
comparison with the theoretical model shows that the LabView design code and
instrumentation are in agreement with the measured data.
50


5.1. I-V Analysis
Current-voltage characterization is one of the important parts of a P-MOSFET
analysis. As mentioned in chapter 2, the behavior of current versus voltage
characteristics is divided into two different regions of operation. Both triode and
saturation regions of measured Id-Vsd are shown in Figure 5-1 for 3 different Vsg
values. In a typically long channel the saturation mode tends to reach at much higher
voltage when carriers reach the thermal saturation velocity.
|d-Vsd
Figure 5-1: Source to Drain Current versus Source to Drain Voltage
51


At triode region, RdS(0n) is another parameter for the characteristic of
MOSFETs. RdS(on) is the resistance between source and drain when the transistor is
on. At linear region, for small values of Vsd neglecting higher order Vsd, the current
given by equation 2.2, is approximately equal to:

(5.1)
Furthermore using Ohms Law and substituting equation 5.1, RdS(on) can be obtained:
The Rds(on) data measured for this P-MOSFET shows a value of about 250 kO at Vsg
equal to 8V. The Rds(on) is higher than normal due to the small size of the P-MOSFET
fabricated which results in a low current value controlled by Kp.
The measured behavior of Id-Vsg characteristic is shown in Figure 5-2 for 3 different
Vsd biases. This behavior is modeled by a quadratic current versus voltage equation
discussed in chapter 2, equation 2.3. A turn-on threshold voltage Vtp of about 4.2 V
is extracted using the quadratic model as shown in
Figure 5-3.
(5.2)
(5.3)
52


Id-Vsg
Figure 5-2: Source to Drain Current versus Source to Gate Voltage
The transconductance, gm. of MOSFET is calculated based on the theoretical model
of equation 5.2 as defined by:
di,
gn
dv
= 2 K,(vx,+V),
(5.4)
S(i
where
g.=<5-5>
The data calculating gm is determined from the inverse slope of Id-Vsg at Vsd equal to
5V. The inverse slope of the measured fitted data for the P-MOSFET shows a gm of
3lxlO'3 S as shown in
53


Figure 5-3.
sqrt(lD)-Vsc
Vsg (V)
Figure 5-3: Square Root of Source-Drain Current versus Source-Gate Voltage
The forward bias diode I-V characterization shows the properties of bulk-
drain junction. The effect of isolation in drain-bulk pn junction is also normally
demonstrated in measured C-V data. In the design of MOSFET drain-bulk pn
junction is formed to prevent the leakage of source-drain current to the bulk. The
isolation at pn junction prevents the flow of current from leaking into the bulk,
reducing the series effect. A measured turn-on voltage of about 0.6V can visually be
seen from Figure 5-4 verifying the accuracy of the measurement technique developed
54


and designed. According to the theoretical model a normal silicon diode shows a turn-
on voltage of about 0.6 to 0.7V depending on the conductivity of the doped silicon
substrate in-line with the data measured.
Drain Bulk Diode
Drain Bulk Voltage (V)
Figure 5-4: Measured Characteristics of a Drain-Bulk/Source Diode
5.2. C-V Analysis
Widely used measurement technique for the characterization of MOS system
is C-V measurement, where both high and low frequency small signal techniques are
employed to obtain capacitance versus voltage behavior of transistors. Detail analysis
of a C-V measurement is the characterization and exploration of turn-on voltage
55


(threshold voltage), flat-band voltage, oxide capacitance, thickness of oxide, and the
properties of the inversion layer, and how deep the depletion are at large gate bias.
The measured high frequency on-wafer probe of a P-MOSFET device is
shown in Figure 5-5. The assigned frequency is 1MHz set by the capacitance meter
instrument. Much lower frequency is normally used for the study of interface
characterization.
HF CGS-VG
Voltage (V)
Figure 5-5: Gate-Source Capacitance versus Gate to Source Voltage (High Frequency)
The equivalent gate area of the capacitance measured includes four P-MOS
transistors, Figure 5-6. P-MOS transistors have an aspect ratio (W/L) of equal to 3
with gate lengths of L=20pm, L=15pm, L=10pm, and L=5pm in parallel, Figure 5-6,
where the area of a transistor is defined as:
A = W L (5.6)
56


Based on the above geometry, the total capacitance is obtained from
f \
y area of gate
\4transistor.s )
C
TOTAL

(5.7)
where eox, the dielectric constant of silicon dioxide is
s()X=3.97-£0,
(5.8)
and s0 is the permittivity of air.
Additionally, the oxide thickness, tox of 31 nm is obtained from the graph in
Figure 5-5 where Cox is estimated to be 2.5 pF.
"m
£7*3 7.0KU

Figure 5-6: On-Wafer P-MOSFET (SEM Microscope Picture
Note that the highest measured values of the capacitance shown far right at
flat region (Figure 5-5) are obtained at low gate-source bias and below threshold
57


voltage, where the total capacitance is dominated by the oxide capacitance (Cox)
only. As the gate voltage increases the variation in capacitance is due to the formation
of inversion layer underneath the oxide. The onset of the change in capacitance is
where Vsg is equal to the threshold voltage. A measured threshold voltage about 4.2V
can be observed in Figure 5-5, in agreement with the result obtained by DC current
versus voltage measurement discussed earlier in this chapter. As the gate-source bias
further increased, the P-MOSFET goes through a so called deep depletion and the
total capacitance is the parallel sum of oxide capacitance (Cox) and the depletion
capacitance (Cdep):
1
C
TOTAL
1 1
--------1-------
c c
'-'OX v" DEP
(5.9)
where the depletion capacitance is:
CDEP=A(5-10)
xd
and Xd is the depletion thickness. The value of dielectric constant for silicon sSj is
exl=U.7xs0 (5.11)
From equation 5.9 the following equation is obtained:
C
TOTAL
(
PET
1 +
c
^ PEE
r
(5.12)
58


Equation 5.10 illustrates that the depletion capacitance is inversely proportional to the
depletion thickness. As the gate-bulk voltage increases, it causes the depletion
capacitance to decrease to a point at deep depletion, where the total capacitance is
given by CDep. From measured data shown in Figure 5-5 Cdep is estimated to be equal
to 0.96 pF. Based on this measured data and equation 5.10 the depth of the depletion
thickness can be estimated to:
xd = A-^- = Q247jum (5.13)
y
In the above derivation an effective gate area of 2250 pm representing four P-MOS
transistors is used as discussed earlier. The depletion thickness acquired is a typical
and reasonable value representing the source/drain doping depth into the n-type
substrate.
A similar analysis is performed on a large middle capacitance with an area of
480x220 micro m2, Figure 5-7.
59


Large MID CAP
7. * < tv 103
Figure 5-7: On-Wafer Large Capacitor (Large MID CAP)
Based on the above analysis we have extracted an oxide thickness of about 224 nm
and a threshold voltage of about 5.5V, Figure 5-8.
LARGE MID CAP
Figure 5-8: Capacitance versus Voltage on the Large MID CAP
60


The minor discrepancy in these values (both threshold voltage and oxide thickness) is
due to the fact that the MID CAP capacitance has four different layers of oxide due to
the fabrication processes. Additionally, both interface oxide charge and interface trap
cause the threshold voltage to vary from one transistor to another.
The role of drain-bulk capacitance is mostly in the form of series effect and
parasitics. However, it does affect the performance of electronic devices at the output
terminals. It also has a non-linear voltage-dependent behavior which shows up as a
capacitance between drain and bulk terminals. Drain-bulk capacitance is a pn junction
type capacitance, where the thickness of depletion region between drain and bulk and
the physical area and the physical dimension of the drain contact control the size of
this capacitance, Figure 5-9.
Source
Gate
Drain
1
n-type
Bulk
Figure 5-9: Drain-Bulk/Source Capacitance
61


This capacitance operates normally at reversed bias junction since drain is negative
with respect to the bulk/source. As a result, the size of this capacitance is dominated
by bulk-drain reversed voltage, Figure 5-10.
Cdb-Vdb Drain Bulk PN Junction
Figure 5-10: Measured Drain to Bulk/Source Capacitance versus Drain to Bulk/Source Voltage
62


The analyses presented above are consistent with normal characterization
practiced in semiconductor industry. It is shown that the measured data obtained for
P-MOS transistors are in agreement with the analytical model confirming the
accuracy of both the measurement techniques and the Lab View design code for probe
station.
63


6. Conclusion
The intention of this study is to provide information about the design of
Lab View for the control of the necessary instrumentation used in the computation of
I-V and C-V measurement generated parameters that result in the characterization
of P-MOSFETs on wafer, using micro probe station.
In device electronics, MOSFETs are important, since their use in different
electronic areas and circuit designs is extensive. Therefore, the study of the electrical
characteristics of MOSFETs is both relevant and significant. Different methods
regarding I-V and C-V measurements were studied towards the development of
Lab View codes which control the equipment setups needed for on-wafer
measurement and characterization of P-MOSFETs on a probe station.
The functionality of P-MOSFETs depends on their physical operation
including their structure, biasing (both DC and AC) and the different capacitances
(Cos, Cos, and Cgd) between the transistors terminals (source, drain, and gate).
Both DC and AC on-wafer measurements of the P-MOSFET require Lab View
programming that controls the equipments remotely via GPIB. Three different setups
were built to measure Id-Vsg, Id*Vsd, and C-V of a fabricated P-MOSFET, using on-
wafer probe station. Through Id-Vsg measurements, the threshold voltage was
obtained. The DC I-V measurement shows a threshold voltage of about 4.5 V. C-V
64


data measured show a threshold voltage of about 5.5 V. The difference is attributed to
the oxide thickness variation during the fabrication process of making the transistor.
The Id-Vsd measurement allowed the determination of the on-resistance between the
drain and the source, where a RdS>n) of 250 kQ was obtained for the P-MOSFET
measured. Additionally, the C-V setup designed delivered satisfactory Cos and Cos
measurement results. Through the analysis of the I-V and C-V measurements, it is
concluded that the measured parameters agree with the basic theoretical model.
The on-wafer C-V measurements in this project are based on a high frequency
setup, due to the limited availability of equipments provided. For future works and for
more detailed characterization of a P-MOSFET, the utilization of a Semiconductor
Device Analyzer (Agilent B 1500A) would be an option so that better AC and DC
measurements may be obtained, for on-wafer characteristics. The frequency range
provided through that equipment makes it easier to measure at low frequencies. In
addition, on-wafer C-V measurements should be carried out in darkness, since light
influences the flow of particles in a semiconductor device. Adequate setup is needed
to allow measurement in darkness. Also, power supplies that would sweep at bias
higher than 8V, would deliver more detailed information about the collected data,
especially for the characterization of power MOSFETs, when large current-voltage
are delivered.
65


References
[1] D. Flandre, F. Van De Wiele, P. G. A. Jespers, and M. Haond, Measurement of
Intrinsic Gate Capacitances of SOI MOSFETs, IEEE Electron Device Lett., vol.
11, no. 7., July 1990.
[2] Y. Chang, H. Chang, T. Lu, Y. King, K. Chen, and C. Lu, Combining a Novel
Charge-Based Capacitance Measurement (CBCM) Technique and Split C-V
Method to Specifically Characterize the STI Stress Effect Along the Width
Direction of MOSFET Devices, IEEE Electron Device Lett, vol. 29, no. 6, June
2008.
[3] J. Koomen, Investigation of the MOST channel conductance in weak
inversion, Solid State Electronics, vol. 16, no. 7, pp. 801-810, Jul. 1973.
[4] K. Romanjek. F. Andrieu, T. Ernst, and G. Ghibaudo, Improved split C-V
method for effective mobility extraction in sub-0.1-pm Si MOSFETs, IEEE
Electron Device Lett., vol. 25, no. 8, pp. 583-585, Aug. 2004.
[5] E. San Andres, L. Pantisano, J. Ramos, S. Severi, L. Trojman, S. DeGendt, and G.
Groeseneken. RF split capacitance-voltage measurements of short-channel and
leaky MOSFET devices, IEEE Electron Device Lett., vol. 27, no. 9, pp. 772-
774, Sept. 2006.
[6] M. M. Lau, C. Y. T. Chiang, Y. T. Yeow, and Z. Q. Yao, A New Method of
Threshold Voltage Extraction via MOSFET Gate-to-Substrate Capacitance
Measurement, IEEE Transactions on Electron Devices, vol. 48, no. 8, August
2001.
[7] C. Shen, M.-F. Li, X. P. Wang, Y. Yeo, and D.-L. Kwong, A Fast Measurement
Technique of MOSFET Id-Vg Characteristics, IEEE Electron Device Lett, 2005.
66


[8] K.A. Jenkins, J.Y.-C. Sun, and J.-L. Pelloie, Measurement of SOI MOSFET I-V
Characteristics Without Self-Heating, Proceedings 1994 IEEE International
SOI Conference, Oct. 1994.
[9] Miller, Richard. Kammis I., and Chan, Mansun, Device Electronics for Integrated
Circuits, 3rd Ed., John Wiley & Sons, New York, 2003.
[10] Neamen, Donald A., Electronic Circuit Analysis and Design, 2nd Ed.,
McGrawHill, New York, 2001.
[11] Kang, Sung-Mo, Leblebici, Yusuf, CMOS Digital Integrated Circuits. 3rd Ed.,
McGrawHill, New York, 2003.
[12] Van Zeghbroeck, Bart J., ECEN 4375/5375-Microstructure Laboratory, 2005,
CU Boulder, http://ece-www.colorado.edu/~ecen4375/.
[13] Well, Lisa K., Travis, Jeffrey, LabVIEWFOR EVERYONE, Prentice Hall,
NJ, 1997.
67