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Switching strategies for ac/ac vector switching matrix converters

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Switching strategies for ac/ac vector switching matrix converters
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Bakir, Ahmed Mohamed
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Adaptive control systems ( lcsh )
Electric power systems ( lcsh )
Power electronics ( lcsh )
Switching power supplies ( lcsh )
Adaptive control systems ( fast )
Electric power systems ( fast )
Power electronics ( fast )
Switching power supplies ( fast )
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bibliography ( marcgt )
theses ( marcgt )
non-fiction ( marcgt )

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ABSTRACT: This thesis proposes switching strategies for AC chopper converters which can implement the multiple steps switching technique and convert the AC energy to AC, directly. The switching process in this technique depends on the current direction in the load. The main advantage of the technique is that the load will not be disconnected during switching events. Also, the semi-soft switching topology overcomes the switching problems in the AC chopper converters, without increasing the conduction losses of the devices. In addition, this topology does not require a dead-time, an attribute that is essential in the other topologies for ensuring that there is not a short circuit on the input source. In addition, during the dead-time in the traditional AC chopper, the load current is completely is connected from the power source and drains across the snubber circuits, including increased power losses and a bulky snubber circuit. The advocated semi-soft switching topology achieves the multiple step switching and reduces the switching losses, as compared to the hard switching topology with dead-time. A comprehensive analysis is performed including operating principles and all calculations of the currents and power losses. Finally, computer simulations of the applications are executed to validate the approach.
Bibliography:
Includes bibliographical references.
Statement of Responsibility:
by Ahmed Mohamed Bakir.

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|University of Colorado Denver
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Full Text
SWITCHING STRATEGIES FOR AC/AC VECTOR SWITCHING MATRIX
CONVERTERS
by
Ahmed M. Bakir
B.Sc. Al-Tahadi University, 1999
A thesis submitted to the
University of Colorado Denver
in partial fulfillment
of the requirements for the degree of
Master of Science
Electrical Engineering
2012


This thesis for the Master of Science
degree by
Ahmed M. Bakir
has been approved
by
Fernando Mancilla-David
Titsa P. Papantoni-Kazakos
Daniel A. Connors
May 4, 2012


Bakir, Ahmed M. (M.Sc. Electrical Engineering)
Switching Strategies for AC/AC Vector Switching Matrix Converters
Thesis directed by Assistant Professor Fernando Mancilla-David
ABSTRACT
This thesis proposes switching strategies for AC chopper converters which
can implement the multiple steps switching technique and convert the AC energy
to AC, directly. The switching process in this technique depends on the current
direction in the load.
The main advantage of the technique is that the load will not be discon-
nected during switching events. Also, the semi-soft switching topology over-
comes the switching problems in the AC chopper converters, without increasing
the conduction losses of the devices. In addition, this topology does not require
a dead-time, an attribute that is essential in the other topologies for ensuring
that there is not a short circuit on the input source. In addition, during the
dead-time in the traditional AC chopper, the load current is completely discon-
nected from the power source and drains across the snubber circuits, including
increased power losses and a bulky snubber circuit.
The advocated semi-soft switching topology achieves the multiple step
switching and reduces the switching losses, as compared to the hard switch-
ing topology with dead-time.


A comprehensive analysis is performed including operating principles and
all calculations of the currents and power losses. Finally, computer simulations
of the applications are executed to validate the approach.
This abstract accurately represents the content of the candidates thesis. I
recommend its publication.
Approved: Fernando Mancilla-David


DEDICATION
I lovingly dedicate this thesis to my hardworking family, my late father (may
Allah have mercy on him and grant him Paradise, Aameen), and to my affec-
tionate mother as well. Also, I loyally dedicate this thesis to my wife who has
been a great source of motivation and inspiration.


ACKNOWLEDGMENT
All praises to the Sustainer of the worlds, and grace, honour and salutations
on the Chief of Apostles and Seal of Prophets, Mohamed, his family, compan-
ions and those who followed him in an excellent fashion and invited mankind
towards Allah, until the Day of Resurrection.
Im truly grateful to Allah, for giving me the strength and patience to com-
plete this work. I would also like to thank Allah for giving me good health
throughout the research until I have completed this thesis.
On behalf of my entire family, I would like to extend my sincere gratitude
to my advisor and mentor Dr. Fernando Mancilla-David for his friendliness,
continuous guidance, encouragement, and support during my M.S. study at
University of Colorado Denver; I shall never forget this unique period in my
whole life.
Special thanks go to Dr. Julio Cesar Rosas-Caro from Madero City Tech-
nological Institute, Madero, Mexico for his contributions.
I am very thankful to my thesis examining committee members Dr. Titsa
P. Papantoni-Kazakos and Dr. Daniel A. Connors for their time and effort in
reading this work and providing their suggestions and comments.
Finally, my sincere thanks go to my affectionate parents and my whole
family for their endless support in achieving such an important goal of my life
and career.


CONTENTS
Figures ................................................................ x
Tables................................................................ xii
Chapter
1. Introduction......................................................... 1
2. Multiple Steps Switching Capability.................................. 7
2.1 Examined Topologies................................................ 7
2.2 First Topology with 6 Switches and 6 Diodes ..................... 9
2.3 Second Topology with 12 Switches and 12 Diodes................... 15
2.4 Third Topology with 2 Switches and 14 Diodes ................... 21
3. Average & RMS Currents ............................................. 22
3.1 First Topology [6 switches and 6 diodes]........................ 22
3.1.1 Average Diode Current........................................... 22
3.1.2 RMS Diode Current............................................... 23
3.1.3 Average Transistor Current...................................... 23
3.1.4 RMS Transistor Current.......................................... 23
3.2 Second Topology [12 switches and 12 diodes] ...................... 24
3.2.1 Average Diode Current........................................... 24
3.2.2 RMS Diode Current............................................... 24
3.2.3 Average Transistor Current...................................... 25
3.2.4 RMS Transistor Current.......................................... 25
vii


3.3 Third Topology [2 Switches and 14 Diodes] ..................... 25
3.3.1 Average Diode Current........................................... 25
3.3.2 RMS Diode Current............................................... 26
3.3.3 Average Transistor Current...................................... 26
3.3.4 RMS Transistor Current.......................................... 26
4. Switching Losses Calculations....................................... 28
5. Hard Switching versus Semi-Soft Switching........................ 38
5.1 Evaluation of Hard Switching Converter............................ 38
5.1.1 Switching Losses Calculation ................................... 40
5.1.2 Conduction Losses Calculation .................................. 41
5.2 Evaluation of Semi-Soft Switching Converter...................... 43
5.2.1 Switching Losses Calculation ................................... 44
5.2.2 Conduction Losses Calculation .................................. 45
5.3 Switching Process................................................. 47
5.3.1 Hard Switching.................................................. 47
5.3.2 Semi-Soft Switching............................................. 47
5.4 LOSSES AND EFFICIENCY COMPARISON OF BOTH CON-
VERTERS .......................................................... 50
5.5 Semiconductors Ratings............................................ 52
5.5.1 Hard Switching.................................................. 55
5.5.2 Semi-soft Switching............................................. 55
5.6 Conclusion and Future Work........................................ 57
5.6.1 Conclusion ..................................................... 57
5.6.2 Future Work .................................................... 57
viii


References
58
IX


FIGURES
Figure
1.1 Single-phase Buck-type AC-Chopper ................................. 3
1.2 PWM AC-AC Converter................................................ 4
1.3 AC chopper Combined with Isolation Transformer..................... 4
1.4 Effect of Dead-time on Output Voltage.............................. 5
2.1 Current Direction States........................................... 7
2.2 Generated Signals ................................................. 9
2.3 First Topology.................................................... 10
2.4 Case 1, ia and ic are Positive, ^ is Negative..................... 11
2.5 Switching Process during Case 1 13
2.6 Case 2, ih and ic are Negative ia is Positive .......... 14
2.7 Switching Process when % and ic are Negative and ia is Positive . 16
2.8 Second Topology................................................... 17
2.9 Switching Process when ia and ic are Negative and ib is Positive . 20
2.10 Third Topology.................................................... 21
3.1 Current Waveforms of the Switches................................. 22
3.2 Current Waveforms of the Switches................................. 24
3.3 Current Waveforms of the Switches................................. 26
4.1 First Topology.................................................... 30
4.2 Switching Currents and Blocking Voltage........................... 30
x


4.3 Second Topology................................................... 31
4.4 Switching Currents and Blocking Voltage........................... 32
4.5 Switching Currents and Blocking Voltage........................... 33
4.6 Third Proposed Topology........................................... 33
4.7 Switching Currents and Blocking Voltage........................... 34
4.8 Stem Plot for V\I\ of t\ and i4 in the Topology Fig. 4.1.......... 34
4.9 Stem Plot for VJi of H, i7, t4 and tw in the Topology Fig. 2.8 ... 35
4.10 Stem Plot for Vffi of H in the Topology Fig. 4.6.................. 36
5.1 Buck-type AC Chopper.............................................. 39
5.2 Hard Switching Pulses............................................. 47
5.3 Switching Currents and Voltages................................... 48
5.4 Semi-Soft Switching Pulses........................................ 49
5.5 Semi-Soft Switching Pulses........................................ 50
5.6 The Switches with Hard Switching.................................. 53
5.7 The Switches with Soft Switching.................................. 53
5.8 Conduction and Switching Losses .................................. 54
5.9 Efficiency and Power Semiconductor................................ 56
xi


TABLES
Table
2.1 Six-Pulse Cases................................................... 8
3.1 Average and RMS currents for the three topologies............. 27
5.1 Average and RMS currents for the hard switching topology .... 42
5.2 Average and RMS currents for the semi-soft switching topology . . 46
5.3 Prototype Parameters............................................. 51
5.4 Loss Calculation................................................. 52
xii


1. Introduction
The control of power flow in AC transmission systems is complex and is
established by good management of power flow between nodes and intercon-
necting branches [1]. Although AC power systems have a strong connectivity,
the control of power systems remained limited until the recent developments of
controllers that use the power electronic devices. These controllers have greatly
enhanced the capability to control AC transmission systems [2, 3]. The tech-
nique of switching power flow-control was presented by using a DC switching
converter. However, more recently this technique was developed to three phase
Vector Switching Matrix Converter (VeSMC). Vector Switching Matrix Con-
verters have the ability to control and modulate power flow between multiple
power lines in a complex system [16]. The matrix converters have attracted
great attention recently. Moreover, compared to the conventional AC/DC/AC
converters, the matrix converter has the following virtues [19, 20, 4]:
1. Both input current and output voltage are sinusoidal waveforms with slight
harmonics around the switching frequency.
2. No large components, such as large DC smoothing capacitors or smoothing
inductors, are needed for energy storage except a small size AC filter.
3. ery simple to construct and has powerful controllability.
In addition, devices based on AC link power converters have been presented
in [8, 10, 11], which have a functional capability that is equivalent to DC link
1


devices. Theses DC link devices store twice as much energy as AC links. There-
fore, they need more power semiconductor which increase the cost of the power
components in the DC link power converters. On the other hand, the power
semiconductors loss in the AC link is approximately 15% more [9]. Due to the
relatively large physical volume of the DC link energy storage element, com-
pared with the entire converter volume, the lifetime of the converter may be
reduced [6]. An overview of the DC link converter topologies used to implement
a three-phase Pulse Width Modulation (PWM) AC-AC converter system has
been presented in [6]. The topology of the Indirect Matrix Converter (IMG) is
developed from the DC link back-to-back by neglecting the DC link capacitor,
and the three-phase AC-AC Buck-type chopper is considered as a special case
of Matrix Converter (MC). In general, the three-phase AC-AC Buck converters
can only control the amplitude of the output voltage to be less than or equal
to the input voltage, and the control system in these converters is based on
PWM with a constant duty cycle [15]. AC choppers are not designed to change
the frequency. Accordingly, the fundamental output frequency will be equal to
the frequency of the input source. These converters are usually used as voltage
regulators and voltage sag compensators in the distribution system as well as
a power flow controller in the transmission power systems. In other words, the
main applications of the AC chopper are power conditioning in the distribution
systems and power flow in the transmission lines. There are two applications
in the power conditioning where the AC chopper can be implemented. Firstly,
in the full power condition, the fixed AC voltage will be as an input of the AC
chopper and the variable AC voltage will be achieved as an output from the AC
2


chopper which depends on the duty ratio. Secondly, in the partial power condi-
tion, the input of the AC chopper is the grid voltage and the output is connected
to the grid via a series transformer. Consequently, in the series connected AC
chopper, the switches rating can be reduced. In the first application as shown
in Fig. 1.1 the total power of the load is flowing through the converter, resulting
in large switches rating and high cost [5]. This type of AC chopper can be used
to control the voltage at sensitive loads directly, as shown in Fig. 1.1. However,
in other applications, the AC chopper is used in the mid-point of a transmission
line with an isolation transformer as shown in Fig. 1.2 [8, 17].
Furthermore, the AC chopper can be combined with a series injection trans-
former for power flow control in the transmission lines as it shown in Fig. 1.3. In
this case, the power rating of the converter is smaller than the power rating of
the load. Ultimately, the AC choppers are used where there is a need to change
the magnitude of the AC voltage, such as soft starting of induction motor, speed
controllers, and heating systems.
Sensitive
load
Figure 1.1: Singl^phase Buck-type AC-Chopper
3


X/2
Series injection
transformer
X/2
Figure 1.2: PWM AC-AC Converter
Shunt Series injection^ Sensitive
transformer transformer 'a load
Figure 1.3: AC chopper Combined with Isolation Transformer.
4


Recently, the research on the applications and the topologies of the AC-AC
converters has gained attention. However, very little interest has been paid to
the challenges in the AC choppers switching process. Consequently, most of the
offered AC choppers deploy hard switching PWM converters which, in the high
power applications, induce high switching loss and low efficiency. Thus, via the
use of either Zero-Voltage Switching (ZVS) for the transistors or Zero-Current
Switching (ZCS) for the diodes, soft switching techniques for the converters
may be deployed to obtain minimal switching loss and higher efficiency as well
[13]. In addition, the soft-switching topology exhibits better efficiency than the
hard-switching topology [13].
Dead time
s____
cj"
r
Figure 1.4: Effect of Dead-time on Output Voltage
In addition, all the hard switching topologies with dead-time increase the
losses, one of the main resulting difficulties being the snubber design in the AC
choppers. Fig. 1.4 shows the dead-time effect in the VSC. Assuming that the
output current flows out from the phase-leg as shown in Fig. 1.4, the current
flows through the upper transistor Tb; when the latter is on, while the lower
diode Z4l induces a free-wheeling when the upper transistor Tu is off. In this
5


situation, the direction of the draining current is positive. Thus, only the upper
transistor Tu and the lower diode Dl are active, which ensures there is a path
for the load current to flow. When the current flows in a negative direction, only
the lower transistor Tl is on and freewheels through the upper diode D\j. Both
transistors can not be on nor off simultaneously; they switch complementarily
[7]. During the dead-time, both switches S\j and are off. For instance, in the
inductive load, the output voltage depends on the direction of the output current
which is conducted during the dead-time by either the upper or the lower diode
and voltage gain or loss will occur as a result. Therefore, the positive pulses and
the negative pulses in Fig. 1.4 correspond to the gain and loss of the voltage,
respectively [21],
A comparative evaluation of AC-AC vector switching matrix converters, in
order to evaluate loss and efficiency, has been presented for different topologies
feeding the same load. The semi-soft switching technique and hard switching
technique have been implemented and detailed using computer-matlab simula-
tion to prove the operation principle of each technique.
6


2. Multiple Steps Switching Capability
2.1 Examined Topologies
In this chapter, all the switches are considered ideal and no dead-time is
taken into account in all the examined topologies.
The switching process in the topologies depends on the current direction in
the load. Therefore, according to the current direction there are six different
cases or operation modes; each case is 60 as it shown in Fig. 2.1.
Figure 2.1: Current Direction States
So, finding the direction of the load current requires digital indicators as
shown in Fig. 2.2(a), which give zero when the load current is negative or one
when the load current is positive. Consequently, comparing the value of load
current with zero at each phase generates the six-pulse cases as it is shown in
Table 2.1
7


Currents Case 1 Case 2 Case 3 Case 4 Case 5 Case 6
ia 1 1 1 0 0 0
ib 0 0 1 1 1 0
ic 1 0 0 0 1 1
Table 2.1: Six-Pulse Cases
In general, the multiple steps switching strategy can be summarized as fol-
lows [14]:
1. Detect the direction of the current load.
2. Switch off the transistor that is not draining any current at present.
3. Switch on the transistor which will drain the load current in the same
direction.
4. Switch off the transistor which is presently draining the load current; this
will make a new path for the current.
5. Switch on the other transistors in the active switch.
When the current is zero, it is not important if the output signal is zero or
one. Therefore, the current can be considered as a negative current or a positive
current in the switching process (/a = 1 is positive and /a = 0 is negative). This
chapter describes the topologies and the switching strategies for each.
8


ABC
101 case 1
100 case 2
110 case 3
010 case 4
011 case 5
001 case 6
(a) Current Direction Signals
(b) Control Signals for Multiple Steps Switching
Figure 2.2: Generated Signals
2.2 First Topology with 6 Switches and 6 Diodes
The first topology is shown in Fig. 2.3 with two three-phase switches using
the multiple steps switched Buck-type AC chopper half of the time. Turning
the switches on and off in this topology needs eight control signals that are
shown in Fig. 2.2(b). This topology implements the multiple steps switching
technique in a half power period of time and a hard switching technique for the
other half power period. In other words, it is not possible to do soft switching
for all switches during the entire power period.
Note that the two three-phase switches can not be closed at the same time
in this topology because this causes a short circuit on the three phase voltage
source. Similarly, both three-phase switches can not be open at the same time
in this topology because the load will be disconnected and remain in an open cir-
cuit, which may generate voltage spikes [4]. In the case of doing hard switching,
one of the three-phase switches should be closed while the other switch is open
9



1:1
T

?[ s,
1 Itil1 S2
T S3
o
&

i L r
Figure 2.3: First Topology
and vice versa. However, the switching technique in this topology is applied by
the following two procedures:
1. The cases 1, 3 and 5 in Fig. 2.1 use the signals X5,X6,X7 and X8, which
are shown in Fig. 2.2(b) to control the two switches that drain the current
at the same time and the hard switching technique can be achieved through
the following procedure:
(a) Switch off the transistor that is not draining any current in the active
three-phase switch.
(b) Switch on the two transistors which will be finally draining the cur-
rent in the non-active three-phase switch and switch off the two
transistors that are draining the current in the active three-phase
switch at the same time (this is a hard switching).
(c) Switch on the other switch in the three-phase switch that is finally
10


draining the current.
Precisely, this procedure is implemented when the current is positive in
two phases and negative in the other phase. For example, when the current
in both phases A and C is positive and negative in phase B (this is case
1) as shown in Fig. 2.4.
Figure 2.4: Case 1, ia and ic are Positive, % is Negative
Fig. 2.5 shows the switching process for case 1 when the current in phases
A and C is positive and is negative in phase B. In this case, the load is
connected to the input voltage source with the switches Si,S2 & S3 while
the other switches are off. Following the first procedure mentioned above,
the transistor that is not draining any current is S2. Thus, Fig. 2.5(b)
shows the direction of the currents after switching off S2 which remained
constant and flowing through Si & S3 keeping the load connected to the
voltage source. In state 3, after switching on S4 & Se simultaneously with
1:1
11


switching off Si & S3 (this is a hard switching), the input voltage source
will be disconnected and the load will be shorted in a new path through
S4, S5 & Se to keep the load currents flowing in the same directions as
can be seen in Fig. 2.5(c). Finally, switch on S5 in Fig. 2.5(d) which is
not draining any current in this case. It is important to mention that
the switching technique in this case is only hard switching. However, the
soft switching will be applied in the next case by following the second
procedure:
2. In the cases 2, 4 and 6 in Fig. 2.1, there is only one transistor that drains
a positive current all the time and the other two negative currents will be
flowing through the diodes. So, according to the current direction in the
load, these cases use the signals Xi,X2,X3 and X4, which are shown in
Fig. 2.2(b) to control the switches and to implement the multiple steps
switching technique by following the next procedure:
(a) Switch off the two transistors that are not draining any current in
the two phases that have a negative current in the active three-phase
switch.
(b) Switch on the transistor that will be draining the positive current in
the other phase in the non-active three-phase switch.
(c) Switch off the transistor that is draining the positive current in the
active three-phase switch so the other three-phase switch will be
activated as a result.
(d) Switch on the other two transistors in the active three-phase switch.
12


(a) State 1, Si &S3 are draining a positive
current
(c) State 3, S4 SzSq are draining a positive
current
(b) State 2, turn-off S2 while the currents are
still flowing through S\ &S3
(d) State 4, turn-on S5 which is not draining
any current
Figure 2.5: Switching Process during Case 1
13


Previous cases occur when the current is negative in two phases and is
positive in the other phase. For example, case 2 is when the current in phases
B and C is negative, and the current in phase A is negative, Fig. 2.6.
Fig. 2.7 shows the switching process for case 2 when the current in the phases
B and C is negative and the current in the phase A is positive. In this case,
the load is connected to the input voltage source with the switches S\, S2 & S3
while the other switches are off. Following the second procedure mentioned
above, the two transistors that are not draining any current in this case are
S2 & S3. Therefore, State 1 in Fig. 2.7(a) shows the load connected to the input
voltage source with the switches S\, S2 & S3 while the other switches are off and
as it can be seen, in the same figure, the transistors in the switches S2 & S3
are not draining any current. However, in State 2 Fig. 2.7(b) after switching off
(S2 & S3), S1 is the only transistor that drains current. To keep the current
flowing in the same direction, it should switch on S4 before disconnecting the
1:1
Figure 2.6: Case 2, and ic are Negative *a is Positive
14


input voltage source from the load as in State 3 Fig. 2.7(c). In State 4, Fig. 2.7(d)
switching off the transistor that is draining the positive current which is Si,
will immediately change the current path and keep the currents flowing in the
same directions in the load. It can be noted that the switch Si in this case is
the only switch that can control the current path. Finally, switch on the other
two transistors S5 & S6 in the three-phase switch that is eventually draining
the current as shown in State 5, Fig. 2.7(e).
2.3 Second Topology with 12 Switches and 12 Diodes
This topology is shown in Fig. 2.8; each phase in the three-phase voltage
source has four switches to perform multiple steps switching technique in a Buck-
type AC chopper all the time, while the first topology has only two switches.
Therefore, the number of switches has been increased in this topology. Conse-
quently, turning the switches on and off in this topology requires four control
signals only, unlike the previous topology. This topology implements the multi-
ple steps switching technique throughout the entire power period. However, one
of the two three-phase switches is on for half of the time and is off the other
half of the time. As mentioned above only one of the twelve transistors drains
a current at a particular time in the six cases.
This topology is slightly different from the first topology because the load
can be connected to the voltage source by the switches Si, A2 & S3 or by the
switches S7, Sg & Sg while the switches A4 to Se & Sw to S12 are off. However,
the input voltage source will be disconnected and the load will be shorted by
the switches A4, S5 & A6 or the switches S'io, An & S\2 while the switches Si to
S1 & Sj to Sg are off. On the other hand, when the current is positive in one
15



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--W'wsil-i1
ic L R
> 4
r(SHfe£5

4&
i, L r
-^WWVi
-*-Wwv-h'
ic L r
-Wv1
(a) State 1, Si is draining a positive current (b) State 2, turn-off S2 &S3, the current is

4S)MIi-^55-

4 L R
jM'WVi
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wv-1
flowing through Si
1:1
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wv.
-WWVh'
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(c) State 3, turn-on S4 the transistor Si is (d) State 4, turn-off Si, the current path
still draining a positive current changed and 64 is draining the current
(e) State 5, turn-on S$ SzSg, the transistor
S4 is still draining a positive current
Figure 2.7: Switching Process when ih and ic are Negative and ia is Positive
16


phase and is negative in the other two phases, the switches Si to Se will conduct
the current while the other six switches are off during this case. In the other
case, when the current is positive in two phases and negative in the other phase,
the switches SY to Su will conduct the currents while the other six switches are
off during this case. This pattern guarantees that only one transistor will drain
current at a specific time and applies the multiple steps switching technique.
Similar to the previous topology, the switching process depends on the cur-
rent direction in the load. This topology uses the signals X1; X2, X3 and X4 that
are shown in Fig. 2.2(b) to control the switches and implements the multiple
steps switching technique by following the next procedure:
1. Switch off the two transistors that are connecting the input voltage source
to the load and are not draining any current in the active three-phase
1:1
Figure 2.8: Second Topology
17


switch at present.
2. Switch on the transistor that will disconnect the input voltage source from
the load by shorting the load. Also, this switch is in the non-active three-
phase switch and it will drain the current in the same direction.
3. Switch off the transistor that is currently draining the current in the active
three-phase switch. So, the other three-phase switch will be activated as
a result and the current will start flowing through the transistor that is
already on and through the anti-parallel diodes of the other switches.
4. Switch on the other two transistors in the active three-phase switch.
Taking case 4 Fig. 2.1 as an example of this topology, Fig. 2.9 shows the
switching process when the current in phases A and C is negative and the cur-
rent in phase B is positive. In this case, the load is connected to the input
voltage source with the switches S\, S2 & S3 while all the other switches are
off. Following the procedure mentioned above, the two transistors that are not
draining any current in this case are S1 & S3. Thus, State 1 in Fig. 2.9(a) shows
the load connected to the input voltage source with the switches S\,S2 & S3
while the other switches are off. Although S1 & S3 are on, the transistors are
not draining any current. However, in State 2 Fig. 2.9(b) after switching off
Si & S3, S2 is the only transistor draining current. To keep the current flowing
in the same direction, S5 should be switched on before disconnecting the input
voltage source from the load as in State 3 Fig. 2.9(c). In State 4, Fig. 2.9(d)
switching off the transistor that is presently draining the current which is S2,
will immediately change the current path by making a short on the load and
18


keeping the currents flowing in the same directions in the load. It can be noted
that the switch S2, in this case, is the only switch that can control the current
path. Finally, switch on the other two transistors S5 & Se in the three-phase
switch that is eventually draining the current as shown in State 5, Fig. 2.9(e).
Significantly, in all the States there is only one transistor draining current.
19


(a) State 1, Sy is draining a positive (b) State 2, turn-off S\ &S3, the cur-
current rent is flowing through S2
(c) State 3, turn-on S5 the transistor (d) State 4, turn-off S2, the current
S2 is still draining a positive current path changed and S5 is draining the
current
(e) State 5, turn-on S4 &zSe, S$ is still
draining a positive current
Figure 2.9: Switching Process when *a and ic are Negative and % is Positive
20


2.4 Third Topology with 2 Switches and 14 Diodes
The topology is shown in Fig. 2.10. This topology uses only two driving
switches Si and S2 which makes the switching strategy easy. These two switches
are used to connect the load to the three-phase source and disconnect it as well.
So, when one of the two switches is on, the other one should be off and vice
versa. In addition, both switches can not be closed at the same time, because
this will short the input voltage source. Also, they can not be open at the same
time, because the inductors current path should not be open.
Figure 2.10: Third Topology
Also, there is no multiple steps switching technique that can be applied in
this topology but each of the switches Si and S2 is realized using a Diode-Bridge
and only one active switch.
21


3. Average & RMS Currents
In this chapter the average and RMS currents for the switches beside the AC
source will be presented in general formulas for the three topologies as follows:
3.1 First Topology [6 switches and 6 diodes]
The shapes of the waveforms in this topology are shown in Fig. 3.1.
n is Switching Frequency /Fewer Frequency
d is Duty Ratio
pole
? Switching Frequency /Power Frequency
y Duty Ratio
(a) Current through the Diode
(b) Current through the Transistor
Figure 3.1: Current Waveforms of the Switches.
3.1.1 Average Diode Current
Where
< h >--
, Tp xd Tp ,
(^W+*ob) 2vr
sin{ x t) dt
J-P
n
cos(ai)
i=0
sm(|(n+ 1)) x cos(|n)
siniji/n)
(3.1)
(3.2)
n
sin(cd)
i=0
sm(f(n+ 1)) x sm(|n)
sinijt/n)
(3.3)
22


< Id >=
3.1.2 RMS Diode Current
rpole
sin(-) x cos()
n 1_______'n'
sin(-)
'n'
f2 n!2 f 9
4 = ^£ " Bin2(- xt)-dt
Id
I
Pole
d d 1 47rd
- H------------szn(-----)
4 2n 8jt n
11/2
Note that the shape of the switch current in this topology is the
the shape of diode current .
3.1.3 Average Transistor Current
f ra/2 f r(S^+i/P)
< Imrd >= | f sm(^- xt)-dt
Tp (J^ Tp
< Id > -
'Pole
sin() x cosm
sm(-)
3.1.4 RMS Transistor Current
72 ^ 97T
^ Pole / 2/Z7F
Zdrn
'Pole
Tp
j=o C
sin2( x t) dt
Ip
11 fpnlp
Llrms 1 Ole
d d 1 47rd
- 4---------sm(-----
4 2n 8n n
11/2
(3.4)
(3.5)
(3.6)
same as
(3.7)
(3.8)
(3.9)
(3.10)
23


3.2 Second Topology [12 switches and 12 diodes]
The shapes of the waveforms in this topology are shown in Fig. 3.2.
y\
/I
/I
IN,
N
N
n 0
(a) Current through the Diode
(b) Current through the Transistor
Figure 3.2: Current Waveforms of the Switches.
3.2.1 Average Diode Current
< Id >--
f n/6 ( /T-p xd TP s
j -p i I /v n. ' n. '
'Pole
Tp 4^ 1 .LTp
7=0
f /6
'Pole
. 2tt
sin{ x t) at
Ip
TP ^
7=0
( 27r I ^ ^ I ^~p \
r(w++*vr) 2tt
/ smi x t) at
Tp
< Id > -
'Pole
2tr
sm(f + -) x sin()
sin(-)
V 71 /
3.2.2 RMS Diode Current
/dr
f2
iPole
Tp
n/6
E
,TpXd pp-,
^ n n '
7=0
sin2( x t) dt
Ip
p
-'Pole
Tp
n/6
E
7=0
/ sm ( x t) dt
(3.11)
(3.12)
(3.13)
24



drn
h
Pole
d d 1 sm(§ + v) x sin(^r)
6 n 87r
3.2.3 Average Transistor Current
sin(-)
' n >
1/2
(3.14)
< It > -
h
Pole
n/6
E

Tp I J(^+iH-)
1=0 l (3+ n >
. .27r
sin{ x t) dt
tp
(3-15)
< /t >=
^ Pole
"27
sm(^) x sm(£ + ^
sin(-)
(3.16)
3.2.4 RMS Transistor Current
(3.17)
(3.18)
3.3 Third Topology [2 Switches and 14 Diodes]
The shapes of the waveforms in this topology are shown in Fig. 3.3.
3.3.1 Average Diode Current

(f+^)
o 2ir
sin ( x t) dt
VTP ;
1 Pole
d_
12
d
1 sin{\ + ^) x sm(^)
\ 3 1 n / V 7?, /
2n 87r
sin()
V n /
1/2
< in >=
f n/2
Pole
tT ^
r i=0
,TpXd ;Tp'
^ r>, ^ n t
. 27T
sm\ x t) dt
tp
(3.19)
< 7f > =
1 Pole
&T
sin{) x cos()
sin(-)
''n/
(3.20)
25


3.3.2 RMS Diode Current
/i
2 n/2 r (T-p-xd | .T-p ^
Pole
Zdrn
TP
E
i=0
sin2( x t) dt
J- p
^drms -^Pole
3.3.3 Average Transistor Current
d d 1 . .47rci
I------------sm(------)
4 2n 8tt v n J
11/2
< It >--
dPole
7r/3
ra/6
E
Tpxd
' 3 n n ' 2-7T
i=0 ^3+*-^;
svn{ x t) dt
ip
< A >=
dPole
7r/3
sin( ) x sin(^ + -)
1 n / V O 77, /
sm(-)
V n /
3.3.4 RMS Transistor Current
/2 f r(f+^+^) 2tt
/2 = .Pgle V- J / S*n2( Xt)-dt
Tp/n
Xl
XI
0 Tpxdjn
IN
IN
Lfv
Tr/2
(a) Current through the Diode
(b) Current through the Transistor
Figure 3.3: Current Waveforms of the Switches
(3/21)
(3.22)
(3.23)
(3.24)
(3.25)
26


Veil
Pole
_d_
12
A_
2 n
1 sm(f + ^) x sin(^)
A 3 ra ' ' n '
1/2
87T
sin(-)
v n '
(3.26)
Table 3.1: Average and RMS currents for the three topologies
Topology
Device
Current
Formula
' sin(^).cos(^)'
v n J______v n '
sin(-)
K n J
1
Diode
Diode
Transistor
Transistor
Jpole
2tt
Aims
Arms
T \d d______1 (4ird\~\ V2
tPole |_4 + 2ri 8TTSln\ n 'J
rm(^).c68(^)'
5m(-)
v n ' J
T \d d 1 /47rd\1 V2
'Pole [4 + ^ ~ 8iFSm(TT)J
Jpole
2tt
A,
sm(f--)xsm()
^6 re 2__v re '
7r \
Diode
Diode
Transistor
Transistor
Arms
Arms
Apole
Apole
Pole
2tt
1 I d
sin(-)
K n '
Jpole
2tt
.J J
1 sm(|+^)xsm(^) l1/2
_ ___v 3 n ^v re J
87T sin(-)
K n '
sOT(^)xsm(|+i)l
v re 1_v 6 1 reJ
sin(-)
K n '
d
12
d_ 1 1 sm(f + ^
2n 8-7T sin
^)xstn( )1
re yv re y
sin( )
v n ' J
Diode
Diode
Transistor
Transistor
-^Pole
2?r
sm()xcos(-)
v re ' K re 1
sini1
' r
-^rms
471^^1 1/2
W [! + /;- £sin(isS)]
sinf^T xsin(7 + -)
K n / K6 1 re 7
-fpole
7t/3
VQI]
Pole
_a___I__d____I___J_ J-'-v 3
p T 2b +
sin{D
1 (f+Af)x--(vr)
87T
sin(^)
v re '
1/2
The formulas in the Table 3.1 present the average and RMS currents for the
devices that connect the load to the source. However, the other devices use the
same formulas after changing (d) to (1-d).
27


4. Switching Losses Calculations
The switching loss depends on the energy dissipated at every switching
event for both transistor and diode semiconductors, so the switching energy in
semiconductors is usually assumed to be proportional to the conducting current
and the blocking voltage at each switching event as follows [12],
blocking voltage, and the conducting current respectively. These values are
usually on the manufacturers datasheets. Therefore, the total power loss over
one power period is as follows:
In both topologies that are shown in Fig. 4.1 and Fig. 4.3, the blocking volt-
age is line-line voltage and the conducting current is the pole current multiplied
by the duty ratio.
Before calculating the losses there are some considerations which have to be
taken into account. These considerations concern the switching losses for the
diodes at turn-on and turn-off events. First of all, the diodes have no turn-on
switching losses, because when the transistor is on (carrying the current), the
current through the diode is zero. Therefore, at turn-on there is no switching
loss. More accurately, the diode blocks the current when it is reverse biased. In
(4.1)
where ER, VR and IR represent the reference values of the energy loss, the
(4.2)
28


the case of a silicon diode, for example, when it is forward biased, it does not
drain any current until 0.7V is applied across it, so when the diode is turned
on it will drain a current; however, the voltage across the diode will not drop
more than 0.7V, even though the input voltage of the converter is greater. Con-
sequently, the switching losses for the diodes are negligible.
Secondly, the diodes have switching losses at the turn-off event, but this is
a function of the voltage they are blocking and the reverse recovery current (not
the load current). Precisely, the reverse recovery in the diode occurs when a
negative voltage is applied across the diode. In other words, when the diode is
in a forward conduction (load current), it will stop conducting at the moment
when a negative voltage is applied across the terminals of the diode forcing
the diode to turn off. Hence, in comparison with the transistor switching losses
which are a function of the line-line voltage and the load current, turn-off losses
in the diodes represent a small amount of power. Finally, in this chapter, the
dead time is not considered for the switch that has hard switching and there are
no switching losses for the diodes in the three examined topologies.
In the topology shown in Fig. 4.1, the transistors ti, t2 and 13 have a hard
switching for half of the power period (^ = 7r), whenever the current is positive
as shown in Fig. 4.2. On the other hand, the transistors f4, t5 and te have hard
switching only for a sixth of the power period (^ = |).
In the topology shown in Fig. 4.3, the transistors t\, t2, t3, t7, tg, and
tg, by the voltage source, have hard switching for a sixth of the power period
(-j£ = |), as shown in Fig. 4.4 and Fig. 4.5. However, the other transistors have
29


Figure 4.1: First Topology
^Sl *S4
jfllllllMk .,11111111 'WWWW
wsi ill Ik. A . VS4: JiflHHhkr
S2 *S5 -.illllllh.,. ^
S2 ^illlfek. Bk S5 AM
*S3 *S6 Kkhlhlhllllllhll HIP"
S3 lllllk .ill 1 111 111 Jill 1 1 S6 Ilk
Time Time
Figure 4.2: Switching Currents and Blocking Voltage
30


soft switching as shown in Fig. 4.4 and Fig. 4.5.
In the topology shown in Fig. 4.6, the transistors t\, and t-2 have hard switch-
ing during the entire power period.
The devices connected to phase A in the topology shown in Fig. 4.1 are t\
and tii. The stem plot for the product of the current and the voltage for the
transistors t\ and t4 at the turn-on and turn-off events is shown in Fig. 4.8.
Also, the product of the current and the voltage in the other phases B and C
will be the same.
The topology shown in Fig. 4.3 has four transistors which are connected to
phase A. Fig. 4.9 shows the stem plot for the product of the current and the
voltage for the transistors t\, t4, t7 and tw at the turn-on and turn-off events.
Also, the product of the current and the voltage in the other phases B and C
1:1
Figure 4.3: Second Topology
31


*si isi
n>- H "nil pr"
S1 fe. A\ . VS4 iHIHIk
*S2 pr ^ ^ pr *S5
VS2 At Ilk. Ilk VS5 Jill ll
*S3 ^illpr - h* *S6 111 pr
^S3 ^ i m a rse iihk
Time Time
Figure 4.4: Switching Currents and Blocking Voltage
32


'"lllilpr w *
VS7 Am k * ^SlO ik il
*S8 ^ '"111 J/T ^ *su '*1pr'
VS8 II Ilk ill ill 0311 IIl.
*S9 PIT n *S12 r V, i
S9 .ill 1 1 Illllk- llllk S12 aa
Time Time
Figure 4.5: Switching Currents and Blocking Voltage
Figure 4.6: Third Proposed Topology


&S1
Time
Figure 4.7: Switching Currents and Blocking Voltage
Figure 4.8: Stem Plot for VJi of t\ and t4 in the Topology Fig. 4.1
34


Figure 4.9: Stem Plot for VJi of t\, tj, f4 and tw in the Topology Fig. 2.8
will be the same.
In the topology shown in Fig. 4.6 there are two transistors in the converter.
Fig. 4.10 shows the stem plot for the product of the current and the voltage for
only one transistor t\ at the turn-on and turn-off events. Also, the product of
the current and the voltage for the other transistor t2 will be the same.
Finally, it can be seen from the stem plots in Fig. 4.8 and Fig. 4.9 of the
topologies in Fig. 4.1 and Fig. 4.3, respectively, that the shapes are not similar.
However, the sum of the product at turn-on and turn-off of the transistors
in both topologies is equal. Significantly, the total switching losses in both
topologies in Fig. 4.1 and Fig. 4.3 are three times the sum of the stem plot
in Fig. 4.8 and Fig. 4.9, respectively, which are equal. For the third topology
Fig. 4.6, the total switching losses are twice the sum of the stem plot in Fig. 4.10
35


xl
*V
max
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Time
Figure 4.10: Stem Plot for Vih of t\ in the Topology Fig. 4.6.
because it has only two transistors. Therefore, the total switching losses in the
third topology are doubled compared to the total switching losses in the other
two topologies.
As mentioned above, it can be seen from (4.1) that the topologies will have
the same switching losses only if they are built by similar devices. Actually, the
devices are not conducting the same amount of current in the topologies, but
they are blocking line-line voltage, so the size of the device will be different in
the two topologies which makes the reference values for the energy loss and the
conducting current in (4.1) have different values.
Therefore, taking into account the switching losses for each device in the
first and second topologies at the turn-on and turn-off events, the analytical
formula that expresses the losses has been developed as follows:
36


Ps
Fpy/l2VinVc
out
IZi
Load
n
2sin(f)
2tt 2tv
cos((2d-l)) + cos()
n n
Er
yRjii
(4.3)
However, the analytical formula that expresses the losses for the third topol-
ogy is as follows:
Ps
a FPV^2VinVout
o-

Load |
71
V3
2 3(!)
/ 2ti , .. , 2ir.
cos((2d 1)) + cos()
n n
Er "
VRIR
(4.4)
where,
d : duty ratio (0 < d < 1) Idn : rms voltage source
Fp : power frequency
PJ\ .< >;u l R I L
Fsw : switching frequency n :
Kut : output voltage of the converter which is:
Kut = v; Vd.
(4.5)
In comparison, the devices in the topology shown in Fig 4.3 with 12 switches
and 12 diodes are conducting less amount of current than the devices in the
topology shown in Fig 4.1.
37


5. Hard Switching versus SemiSoft Switching
This chapter compares the first two topologies after taking into account the
dead-time for the switches that have hard switching and the fact that there are
no switching losses for the diodes in both topologies.
In both topologies shown in Fig. 5.1 and Fig. 2.8, the blocking voltage is
line-line voltage and the conducting current is the pole current multiplied by
the duty ratio.
The conduction loss for the diodes as well as for the transistors is usually
modeled by the product of the current through the device and the voltage drop
across this device [12]. When the voltage drop across the device is approximated
by a linear function depends on the current as in (5.1),
Wn(^) bon + T cm'i (5.1)
therefore, the average power loss can be determined in (5.2) as follows:
Pc = + bn (Cs)2 (5.2)
where Von and ron are usually available on the manufacturers datasheets.
5.1 Evaluation of Hard Switching Converter
The topology with hard switching is shown in Fig. 5.1. This topology has
six switches that are divided into two driving three-phase switches Sa and Sp.
These two switches Sa and Sp are used to connect the load to the three-phase
source and disconnect it as well. Note that the two three-phase switches can not
38


1 : 1
Figure 5.1: Buck-type AC Chopper.
be closed at the same time in this topology because this causes a short circuit on
the three phase voltage source. Also, both three-phase switches can not be open
at the same time because the load will be disconnected and remains in an open
circuit, which may generate voltage spikes [4], Therefore, in the case of doing
hard switching, one of the three-phase switches should be closed while the other
switch is open and vice versa. In other words, Sa and Sp switch complementarily
as in the DC-DC converters. Consequently, this topology has to have a dead-
time and during this time the load current will flow through the snubber circuits
and increase the losses especially for the high power converters. In addition, each
device needs its own snubber to avoid the voltage spikes during the switching
process. This snubber circuit is used to carry the load current during turning
off the switch. Therefore, when the switch is turned off the conduction current
39


will start charging the capacitor in the snubber circuit and the voltage will raise
as a result. However, the AC input voltage is chopped by the converter and
then filtered to give the output voltage waveform that has the same shape and
frequency but a different amplitude which depends on the duty ratio.
Indeed, during the dead-time, which is essential to ensure that there is no
short circuit on the source, the load current has no path to go; meanwhile, the
load current can not be interrupted. On the other hand, the dead-time must
be as narrow as possible to minimize the losses due to voltage spikes at turn-on
and turn-off events [18]. Nevertheless, the load current will drain across the
snubber circuits increasing the power losses as a result and the snubber circuit
will be bulky for such topology.
5.1.1 Switching Losses Calculation
The energy stored in the snubber capacitor Cs transfers to the snubber
resistor Rs and the switch every time it turns on. Also, the inductive load cur-
rent cannot be changed instantly during turn-off. However, this current diverts
through the snubber resistor Rs causing voltage spikes as shown in the Fig. 5.3.
In general, the loss of the converter mainly includes the power devices conduction
loss and switching loss. Since the device data sheet from the manufacturer pro-
vides the reference values of the energy loss in (4.1), the power devices switching
loss of the converter can be calculated by the following expression:
40


Ps
3-Pp^out
| ZLoad|
12Kn
n
3
2 sin(|)
27T 27T
cos((2d l)) + cos( )
n n
2(Dt/Cs + Rs)Vc
out
IZ,
Load
n
3
2 sm(^)
cos((2d- 1)) + ^
n 3
where,
cl : duty ratio (0 < d < 1) Ln : rms voltage source
FP'- power frequency CB : snubber capacitor
F switching frequency Rs : snubber resistor
n : f3W Z\ .< >ad R + JXl
Dt : dead-time Lut output voltage
tout Ln
£R
yRjii
(5.3)
(5.4)
5.1.2 Conduction Losses Calculation
Depending on the Equation(5.2), the power devices conduction losses of the
converter can be calculated as follows:
1- Conduction loss for the diodes that are connected to phase A is:
CondLossDl(d) = Vond < I >Dl(d) +Rnd (^pd))
CondLossD4(d) = Vond < I >o4(d) +Rnd (Id|)
2- Conduction losses for the transistors that are connected to phase A is:
CondLossTl (d) = Vont < I >Td(d) +R-ont (I;rpd))
CondLossT4(d) = Vont < I >T4(d) +Rnt (jxp!))
Therefore, the total conduction losses for the hard switching topology is:
41


Total
3 x {CondLosso^d) + CondLossTx (d)
CondLossD4(d) + CondLossT4(d)}
HS
where,
Vond, Rond, Vont and Ront are available on the manufacturers datasheets.
d is the duty cycle.
d = 1 d.
Table 5.1: Average and RMS currents for the hard switching topology
Topology Device Current Formula
Diode Diode Transistor Transistor lave Irms lave Irms Voht r sinC^).cos(^) 1 v n. J y n '
Hard Switching 27T|ZLoad| Lout \d | c I^Loadl L4 2 Voht sin(-) L v n' J 7^-sin( i o7T ^ n r sinl^).cos(^) 1 v n x n J )]1/2
27f|^Load| Lout \d | c I^Loadl A 2 sin(-) L v n ' J L sin(^ % o7T ^ n )],/2
Therefore,
3 x (Vond + Vont)
, ^ut cos(-)cos(-(2d 1)) +
7T L^T,oH Tl Tl
3 X (Rond + Ront)
V,
7Load|
2
out
IZ,
Load
- + --- sm()cos((2d 1)) (5.5)
4 2n 4tt n V 2 v >> y >
42


5.2 Evaluation of SemiSoft Switching Converter
The converter shown in Fig. 2.8 presents a new topology of AC chopper
with a capability to perform semi-soft switching in multiple steps. Also, the
switching technique in this topology is very similar to the four-step semi-soft
commutation that has been used in the Matrix Converter (MC) [20]. The advan-
tage of using this technique in the MC is that the switching losses are reduced
by 50% compared to the hard switching [20]. On the other hand, the four-step
semi-soft commutation in the MC significantly increases the conduction losses.
However, the semi-soft topology overcomes the switching problems in the AC
chopper converters without increasing the conduction losses of the devices. The
switching process in the topology depends on the current direction in the load.
Therefore, according to the current direction, there are six different cases or
operation modes; each case is 60 as shown in Fig. 2.1.
This topology has four switches in each phase to do a multiple steps switch-
ing technique in a Buck-type AC chopper all the time, while the first topology
has only two switches in each phase. Therefore, the number of the switches has
been increased in this topology. Consequently, turning the switches on and off in
this topology needs four control signals. This topology implements the multiple
steps switching technique throughout the entire power period. However, one of
the two three-phase switches is on for half of the time and is off the other half
of the time. Accordingly, only one of the twelve transistors drains current at a
particular time in the six cases.
43


This topology is slightly different from the first topology because the load
can be connected to the voltage source by the switches Si, S? & S3 or the
switches S7, Sg & Sg while the switches S4 to S3 & Sio to Sfr are off. However,
the input voltage source will be disconnected and the load will be shorted by the
switches S4, S5 & S3 or the switches Sw, Sn & Sfr while the switches Si to Si
& Sj to Sg are off. On the other hand, when the current is positive in one phase
and negative in the other two phases, the switches Si to S6 will conduct the
currents while the other six switches are off during this case. In the other case,
when the current is positive in two phases and is negative in the other phase,
the switches S7 to S12 will conduct the currents while the other six switches are
off during this case. This pattern guarantees that only one transistor will drain
current at a specific time and applies the multiple steps switching technique.
The switching process that depends on the current direction in this converter
has been explained in Chapter 2
5.2.1 Switching Losses Calculation
There is no snubber circuit in the semi-soft topology that is shown in Fig 2.8.
Following the multiple steps switching technique, creates a path for the current.
This current flows during the switching events as it shown in Fig 2.9 Chapter
2. Then, taking into account the same considerations that applied in the hard
switching topology, the analytical formula that expresses the switching losses in
the semi-soft topology can be developed as follows:
Ps
2 FpVl2ViriVout
IZi
Load
"v 3 / 27r , > s / 2tt .
-----y cos((2dl)) + cos()
2sin{) [ v n V " v n !
- - er "
_ VRIR
(5.6)
44


where
cl : duty ratio (0 < d < 1)
Fp : power frequency
Fsw : switching frequency
Kut : output voltage of the converter which is:
V\n : rms voltage source
A,
Load
n :
R + jXL
f3W
Vr
out
Vd
(5.7)
5.2.2 Conduction Losses Calculation
Depending on the Equation(5.2), the power devices conduction losses of the
converter can be calculated as follows:
1- Conduction loss for the diodes that are connected to phase A is:
CondLoSSDl+D7(d) = Vond < I >Dx(d) +Rond (^d))
+ Vond < I >D7(d) +Rond (inqd))
= 2 x [vond < I >D(d) +Rond (iggf)'
CondLoSSD4+D10(d) = Vond < I >D4(d) +Rond (l^f|))
+ Vond < I >Dio(d) +Rond (^(d))
2 X
Vond < I >D(d) +R.
trmsV
ond \ iD(d) J
2- Conduction losses for the transistors that are connected to phase A is:
CondLossTl+T7(d) = Vont < I >Tx(d) +Ront (I;rqd))
+ Vont < I >T7(d) +Ront (ixqd3))2
CondLossT4+Txo (d)
2 x
V,
v, < I >T(d) +R.
ont < I >T4(d) +R.
tRMS \'
ont 1 T4(d) J
Vont < I >Txo(d) +Rot(IRMS
2 x
Vont <1 >TCd) +R
T(d)
Txo(d)
tRMs\ 2
ont l iT(d) J
45


Therefore, the total conduction losses for the semi-soft switching topology is:
Totalsmeis = 3 x {CondLossDi+D? (d) + CondLossT1+T7(d)
where,
CondLossD4+Dio(d) + CondLossT4+Ti0(d)}
Vond, R0nd, Vont and Ront are available on the manufacturers datasheets.
d is the duty cycle.
d = 1 d.
Table 5.2: Average and RMS currents for the semi-soft switching topology
Topology
Device
Current
Formula
sinl f ) X ( )
6 n f________v n '
Semi-Soft
Switching
Diode
Diode
Transistor
Transistor
Rut
* OUi
2tt\ZLc
Rut
joad I
d
sm(^)
j_fR(iw)
Therefore,
Pc
3 X (VQnd
+ Vont) |^Ut ,cos(-)cos(-(2d 1)) +
ti" | Ai < )ar[ | n n
3 X (R0nd + Ront)
Pout
^Load
1 1
4 2n
1
47T
sin()cos( (2d 1))
n 2
(5.8)
46


5.3 Switching Process
5.3.1 Hard Switching
Fig. 5.2 shows the switching signals for the hard switching topology and the
dead-time. It can been seen from the figure that all the switches are off during
the dead-time and the load current will flow through the snubber circuit causing
voltage spikes as shown in Fig. 5.3
Switching Signals
Figure 5.2: Hard Switching Pulses
5.3.2 SemiSoft Switching
Fig. 5.4 shows the switching signals for the semi-soft switching topology
with the pulses of the current directions. Although there are twelve switches in
47


Time Time
(a) Phase A
(b) Phase B
ss
Time
(c) Phase C
Figure 5.3: Switching Currents and Voltages
48


the semi-soft switching topology shown in Fig 2.8, there are only three switches
which are on all the time as can be seen in Fig. 5.5 by zooming in on Fig. 5.4
Switching Signals
SB
57
58
59
Sio
Su
Sis
Time
Figure 5.4: Semi-Soft Switching Pulses
49


Switching Signals
ta
*b

51
52
53
s4
55
56
Sr
S8
Sq
Sio
Sn
S12
Time
Figure 5.5: Semi-Soft Switching Pulses
5.4 LOSSES AND EFFICIENCY COMPARISON OF BOTH
CONVERTERS
A complete list of parameters is presented in Table 5.3 for both topologies.
Table 5.4 shows the result of the analytical calculations compared against
matlab simulations. It can be seen that the results from both methods are ap-
proximately consistent. During one switching period in the semi-soft switching
topology, there is only one switch that has hard switching and the other switches
have soft switching. In general, all the switches that connect the load to the
source have hard switching as shown in Fig. 5.6. However, the other six switches
have soft switching all the time as shown in Fig. 5.7. Consequently, the switch-
50


Table 5.3: Prototype Parameters
System Parameters
Mains 14 = 208(V), Fp = 60(Hz)
Isolation transformer n = 1:1
Load R = 100(D) L = 100(mH), SL = 405(VA)
Hard Switching Converter Parameters
MOSFETs FDD6N50 Vbs = 500(V), Id = 6(A)
Snubber Circuit Rs = 700(D), CB = 0.2(nF)
Duty Cycle 50%
Switching frequency 1.2(kHz)
Dead-Time 2 (jisec)
Semi-Soft Switching Converter Parameters
MOSFETs FDP5N50F yDS = 500(V), ID = 4(A)
Switching frequency 1.2(kHz)
Duty Cycle 50%
51


ing losses are distributed in the six switches beside the voltage source, while the
other six switches have no switching losses at all.
Table 5.4: Loss Calculation
Hard Switching
Analytical Solution Computer Simulation
Switching Losses 4.9 (W) 4.61 (W)
Conduction Losses 3.26 (W) 3.27 (W)
Semi-Soft Switching
Analytical Solution Computer Simulation
Switching Losses 2.72 (W) 2.46 (W)
Conduction Losses 3.26 (W) 3.24 (W)
The main advantage of hard switching is that there is no need to measure the
load current, while the disadvantage is the design of the snubber circuit which
is necessary to do hard switching. However, the main disadvantage of semi-soft
switching is the need to know the current direction. Also, measuring devices are
expensive in high power applications. In general, semi-soft switching is more
efficient than hard switching as shown in Fig. 5.9(a), and the switch in semi-
soft switching topology overcame the AC choppers switching problems without
increasing the conduction losses as shown in Fig. 5.8(a) and Fig. 5.8(b).
5.5 Semiconductors Ratings
Power semiconductor of the device can be specified by the maximum voltage
the device can block and the average current the device conducts. The analytical
52


Figure 5.6: The Switches with Hard Switching
S4 *S10
^S4 Jk M ^SIO Ik Jk ,
*S5 *S11
^S5 l Ai ^Sll Jk m
N f 1 *S12
VS6 Jk Jk ^S12 i Jk Jf
Time Time
Figure 5.7: The Switches with Soft Switching


Conduction Losses (w)
(a) Conduction Losses
Switching Losses (w)
Duty Cycle
(b) Switching Losses
Figure 5.8: Conduction and Switching Losses
54


formulas that express the ratings can be developed as follows:
5.5.1 Hard Switching
Si(VA) = - 3 X Vof[ {< I >Ti(d) + < I >Di(d) + < I >T4(d) + < I >D4(d) } = 3 x Kff27r|^ad| \4cs(l)cs(l(2d 1))]
5.5.2 Semisoft Switching
Si(VA) = - 3 X 14ff{< I >Ti(d) + < I >Di(d) + < I >T7(d + < I >D7(d) + < I >T4(d) + < I >D4(d) + < I >Tio(d) + < I >Dio(d)} = 3 x Vo^2^L\ [^os(l)cosCn(2d 1))]
Although the number of the devices has been increased in the semi-soft
switching, the total semiconductor (VA) for both topologies is the same as shown
in Fig. 5.9(b).
55


Efficiency %
Duty Cycle
(a) Efficiency
Si (VA)
Duty Cycle
(b) Power Semiconductor
Figure 5.9: Efficiency and Power Semiconductor
56


5.6 Conclusion and Future Work
5.6.1 Conclusion
There are various topologies for implementing an AC chopper in distribution
systems, as well as in transmission systems. Therefore, the semi-soft switching
topology can be used in applications such as voltage control at sensitive loads,
voltage sag compensators in the distribution system, and power flow control
transmission power systems.
For reducing turn-on and turn-off losses in the power switching devices,
the semi-soft switching topology shows better efficiency than the hard switching
topology. All the formulas in both topologies may be used for estimating losses
and in the design of such converters. Finally, after considering the effects of
dead time in the hard switching topology, the result deviates from the ideal one.
Although the number of switches in the semi-soft switching topology was
increased, the total of conduction losses did not increase.
5.6.2 Future Work
The work in this research may be extended to experimental implementation
in the lab, in order to compare the simulation results with the experimental
results. Also, a closed loop controller may be designed to deal with unbalanced
issues by changing the duty cycle.
57


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controlled AC-to-AC converters. IEEE Transactions on Industrial Elec-
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phase PWM AC-AC converter topologies. IEEE Transactions on Indus-
trial Electronics, 58(ll):4988-5006, Nov 2011.
[7] C. Lihua and P. Fang-Zheng. Dead-Time elimination for voltage source
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pensator. IEE Proceedings Generation, Transmission and Distribution,
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kVA three-phase PWM AC line conditioner. In IEEE International Sym-
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[19] L. Wei and T.A. Lipo. A novel matrix converter topology with simple
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60


Full Text

PAGE 1

SWITCHINGSTRATEGIESFORAC/ACVECTORSWITCHINGMATRIXCONVERTERSbyAhmedM.BakirB.Sc.Al{TahadiUniversity,1999AthesissubmittedtotheUniversityofColoradoDenverinpartialfulllmentoftherequirementsforthedegreeofMasterofScienceElectricalEngineering2012

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ThisthesisfortheMasterofSciencedegreebyAhmedM.BakirhasbeenapprovedbyFernandoMancilla{DavidTitsaP.Papantoni{KazakosDanielA.ConnorsMay4,2012

PAGE 3

Bakir,AhmedM.(M.Sc.ElectricalEngineering)SwitchingStrategiesforAC/ACVectorSwitchingMatrixConvertersThesisdirectedbyAssistantProfessorFernandoMancilla{DavidABSTRACT ThisthesisproposesswitchingstrategiesforACchopperconverterswhichcanimplementthemultiplestepsswitchingtechniqueandconverttheACenergytoAC,directly.Theswitchingprocessinthistechniquedependsonthecurrentdirectionintheload. Themainadvantageofthetechniqueisthattheloadwillnotbediscon-nectedduringswitchingevents.Also,thesemi{softswitchingtopologyover-comestheswitchingproblemsintheACchopperconverters,withoutincreasingtheconductionlossesofthedevices.Inaddition,thistopologydoesnotrequireadead{time,anattributethatisessentialintheothertopologiesforensuringthatthereisnotashortcircuitontheinputsource.Inaddition,duringthedead{timeinthetraditionalACchopper,theloadcurrentiscompletelydiscon-nectedfromthepowersourceanddrainsacrossthesnubbercircuits,includingincreasedpowerlossesandabulkysnubbercircuit. Theadvocatedsemi{softswitchingtopologyachievesthemultiplestepswitchingandreducestheswitchinglosses,ascomparedtothehardswitch-ingtopologywithdead{time.

PAGE 4

Acomprehensiveanalysisisperformedincludingoperatingprinciplesandallcalculationsofthecurrentsandpowerlosses.Finally,computersimulationsoftheapplicationsareexecutedtovalidatetheapproach. Thisabstractaccuratelyrepresentsthecontentofthecandidate'sthesis.Irecommenditspublication.Approved:FernandoMancilla{David

PAGE 5

DEDICATION Ilovinglydedicatethisthesistomyhardworkingfamily,mylatefather(mayAllahhavemercyonhimandgranthimParadise,Aameen),andtomyaec-tionatemotheraswell.Also,Iloyallydedicatethisthesistomywifewhohasbeenagreatsourceofmotivationandinspiration.

PAGE 6

ACKNOWLEDGMENT AllpraisestotheSustaineroftheworlds,andgrace,honourandsalutationsontheChiefofApostlesandSealofProphets,Mohamed,hisfamily,compan-ionsandthosewhofollowedhiminanexcellentfashionandinvitedmankindtowardsAllah,untiltheDayofResurrection. I'mtrulygratefultoAllah,forgivingmethestrengthandpatiencetocom-pletethiswork.IwouldalsoliketothankAllahforgivingmegoodhealththroughouttheresearchuntilIhavecompletedthisthesis. Onbehalfofmyentirefamily,IwouldliketoextendmysinceregratitudetomyadvisorandmentorDr.FernandoMancilla{Davidforhisfriendliness,continuousguidance,encouragement,andsupportduringmyM.S.studyatUniversityofColoradoDenver;Ishallneverforgetthisuniqueperiodinmywholelife. SpecialthanksgotoDr.JulioCesarRosas{CarofromMaderoCityTech-nologicalInstitute,Madero,Mexicoforhiscontributions. IamverythankfultomythesisexaminingcommitteemembersDr.TitsaP.Papantoni{KazakosandDr.DanielA.Connorsfortheirtimeandeortinreadingthisworkandprovidingtheirsuggestionsandcomments. Finally,mysincerethanksgotomyaectionateparentsandmywholefamilyfortheirendlesssupportinachievingsuchanimportantgoalofmylifeandcareer.

PAGE 7

CONTENTS Figures....................................x Tables.....................................xii Chapter 1.Introduction................................1 2.MultipleStepsSwitchingCapability...................7 2.1ExaminedTopologies..........................7 2.2FirstTopologywith6Switchesand6Diodes............9 2.3SecondTopologywith12Switchesand12Diodes..........15 2.4ThirdTopologywith2Switchesand14Diodes...........21 3.Average&RMSCurrents........................22 3.1FirstTopology[6switchesand6diodes]...............22 3.1.1AverageDiodeCurrent........................22 3.1.2RMSDiodeCurrent.........................23 3.1.3AverageTransistorCurrent.....................23 3.1.4RMSTransistorCurrent.......................23 3.2SecondTopology[12switchesand12diodes]............24 3.2.1AverageDiodeCurrent........................24 3.2.2RMSDiodeCurrent.........................24 3.2.3AverageTransistorCurrent.....................25 3.2.4RMSTransistorCurrent.......................25vii

PAGE 8

3.3ThirdTopology[2Switchesand14Diodes].............25 3.3.1AverageDiodeCurrent........................25 3.3.2RMSDiodeCurrent.........................26 3.3.3AverageTransistorCurrent.....................26 3.3.4RMSTransistorCurrent.......................26 4.SwitchingLossesCalculations......................28 5.HardSwitchingversusSemi{SoftSwitching...............38 5.1EvaluationofHardSwitchingConverter...............38 5.1.1SwitchingLossesCalculation....................40 5.1.2ConductionLossesCalculation...................41 5.2EvaluationofSemi{SoftSwitchingConverter.............43 5.2.1SwitchingLossesCalculation....................44 5.2.2ConductionLossesCalculation...................45 5.3SwitchingProcess............................47 5.3.1HardSwitching............................47 5.3.2Semi{SoftSwitching.........................47 5.4LOSSESANDEFFICIENCYCOMPARISONOFBOTHCON-VERTERS................................50 5.5SemiconductorsRatings........................52 5.5.1HardSwitching............................55 5.5.2Semi{softSwitching.........................55 5.6ConclusionandFutureWork......................57 5.6.1Conclusion..............................57 5.6.2FutureWork.............................57viii

PAGE 9

References ...................................58ix

PAGE 10

FIGURES Figure 1.1Single{phaseBuck{typeAC{Chopper................3 1.2PWMAC{ACConverter........................4 1.3ACchopperCombinedwithIsolationTransformer..........4 1.4EectofDead{timeonOutputVoltage................5 2.1CurrentDirectionStates........................7 2.2GeneratedSignals...........................9 2.3FirstTopology.............................10 2.4Case1,iaandicarePositive,ibisNegative.............11 2.5SwitchingProcessduringCase1...................13 2.6Case2,ibandicareNegative,iaisPositive............14 2.7SwitchingProcesswhenibandicareNegativeandiaisPositive.16 2.8SecondTopology............................17 2.9SwitchingProcesswheniaandicareNegativeandibisPositive.20 2.10ThirdTopology.............................21 3.1CurrentWaveformsoftheSwitches..................22 3.2CurrentWaveformsoftheSwitches..................24 3.3CurrentWaveformsoftheSwitches..................26 4.1FirstTopology.............................30 4.2SwitchingCurrentsandBlockingVoltage...............30x

PAGE 11

4.3SecondTopology............................31 4.4SwitchingCurrentsandBlockingVoltage...............32 4.5SwitchingCurrentsandBlockingVoltage...............33 4.6ThirdProposedTopology.......................33 4.7SwitchingCurrentsandBlockingVoltage...............34 4.8StemPlotforViIioft1andt4intheTopologyFig.4.1.......34 4.9StemPlotforViIioft1,t7,t4andt10intheTopologyFig.2.8...35 4.10StemPlotforViIioft1intheTopologyFig.4.6...........36 5.1Buck{typeACChopper.........................39 5.2HardSwitchingPulses.........................47 5.3SwitchingCurrentsandVoltages...................48 5.4Semi{SoftSwitchingPulses......................49 5.5Semi{SoftSwitchingPulses......................50 5.6TheSwitcheswithHardSwitching..................53 5.7TheSwitcheswithSoftSwitching...................53 5.8ConductionandSwitchingLosses..................54 5.9EciencyandPowerSemiconductor.................56xi

PAGE 12

TABLES Table 2.1Six{PulseCases.............................8 3.1AverageandRMScurrentsforthethreetopologies.........27 5.1AverageandRMScurrentsforthehardswitchingtopology....42 5.2AverageandRMScurrentsforthesemi{softswitchingtopology..46 5.3PrototypeParameters.........................51 5.4LossCalculation............................52xii

PAGE 13

1.Introduction ThecontrolofpowerowinACtransmissionsystemsiscomplexandisestablishedbygoodmanagementofpowerowbetweennodesandintercon-nectingbranches[1].AlthoughACpowersystemshaveastrongconnectivity,thecontrolofpowersystemsremainedlimiteduntiltherecentdevelopmentsofcontrollersthatusethepowerelectronicdevices.ThesecontrollershavegreatlyenhancedthecapabilitytocontrolACtransmissionsystems[2,3].Thetech-niqueofswitchingpowerow{controlwaspresentedbyusingaDCswitchingconverter.However,morerecentlythistechniquewasdevelopedtothreephaseVectorSwitchingMatrixConverter(VeSMC).VectorSwitchingMatrixCon-vertershavetheabilitytocontrolandmodulatepowerowbetweenmultiplepowerlinesinacomplexsystem[16].Thematrixconvertershaveattractedgreatattentionrecently.Moreover,comparedtotheconventionalAC/DC/ACconverters,thematrixconverterhasthefollowingvirtues[19,20,4]:1. Bothinputcurrentandoutputvoltagearesinusoidalwaveformswithslightharmonicsaroundtheswitchingfrequency.2. Nolargecomponents,suchaslargeDCsmoothingcapacitorsorsmoothinginductors,areneededforenergystorageexceptasmallsizeAClter.3. erysimpletoconstructandhaspowerfulcontrollability. Inaddition,devicesbasedonAClinkpowerconvertershavebeenpresentedin[8,10,11],whichhaveafunctionalcapabilitythatisequivalenttoDClink1

PAGE 14

devices.ThesesDClinkdevicesstoretwiceasmuchenergyasAClinks.There-fore,theyneedmorepowersemiconductorwhichincreasethecostofthepowercomponentsintheDClinkpowerconverters.Ontheotherhand,thepowersemiconductorslossintheAClinkisapproximately15%more[9].DuetotherelativelylargephysicalvolumeoftheDClinkenergystorageelement,com-paredwiththeentireconvertervolume,thelifetimeoftheconvertermaybereduced[6].AnoverviewoftheDClinkconvertertopologiesusedtoimplementathree{phasePulseWidthModulation(PWM)AC{ACconvertersystemhasbeenpresentedin[6].ThetopologyoftheIndirectMatrixConverter(IMC)isdevelopedfromtheDClinkback{to{backbyneglectingtheDClinkcapacitor,andthethree{phaseAC{ACBuck{typechopperisconsideredasaspecialcaseofMatrixConverter(MC).Ingeneral,thethree{phaseAC{ACBuckconverterscanonlycontroltheamplitudeoftheoutputvoltagetobelessthanorequaltotheinputvoltage,andthecontrolsystemintheseconvertersisbasedonPWMwithaconstantdutycycle[15].ACchoppersarenotdesignedtochangethefrequency.Accordingly,thefundamentaloutputfrequencywillbeequaltothefrequencyoftheinputsource.Theseconvertersareusuallyusedasvoltageregulatorsandvoltagesagcompensatorsinthedistributionsystemaswellasapowerowcontrollerinthetransmissionpowersystems.Inotherwords,themainapplicationsoftheACchopperarepowerconditioninginthedistributionsystemsandpowerowinthetransmissionlines.TherearetwoapplicationsinthepowerconditioningwheretheACchoppercanbeimplemented.Firstly,inthefullpowercondition,thexedACvoltagewillbeasaninputoftheACchopperandthevariableACvoltagewillbeachievedasanoutputfromtheAC2

PAGE 15

chopperwhichdependsonthedutyratio.Secondly,inthepartialpowercondi-tion,theinputoftheACchopperisthegridvoltageandtheoutputisconnectedtothegridviaaseriestransformer.Consequently,intheseriesconnectedACchopper,theswitchesratingcanbereduced.IntherstapplicationasshowninFig.1.1thetotalpoweroftheloadisowingthroughtheconverter,resultinginlargeswitchesratingandhighcost[5].ThistypeofACchoppercanbeusedtocontrolthevoltageatsensitiveloadsdirectly,asshowninFig.1.1.However,inotherapplications,theACchopperisusedinthemid{pointofatransmissionlinewithanisolationtransformerasshowninFig.1.2[8,17]. Figure1.1:Single{phaseBuck{typeAC{Chopper Furthermore,theACchoppercanbecombinedwithaseriesinjectiontrans-formerforpowerowcontrolinthetransmissionlinesasitshowninFig.1.3.Inthiscase,thepowerratingoftheconverterissmallerthanthepowerratingoftheload.Ultimately,theACchoppersareusedwherethereisaneedtochangethemagnitudeoftheACvoltage,suchassoftstartingofinductionmotor,speedcontrollers,andheatingsystems.3

PAGE 16

Figure1.2:PWMAC{ACConverter Figure1.3:ACchopperCombinedwithIsolationTransformer.4

PAGE 17

Recently,theresearchontheapplicationsandthetopologiesoftheAC{ACconvertershasgainedattention.However,verylittleinteresthasbeenpaidtothechallengesintheACchoppersswitchingprocess.Consequently,mostoftheoeredACchoppersdeployhardswitchingPWMconverterswhich,inthehighpowerapplications,inducehighswitchinglossandloweciency.Thus,viatheuseofeitherZero{VoltageSwitching(ZVS)forthetransistorsorZero{CurrentSwitching(ZCS)forthediodes,softswitchingtechniquesfortheconvertersmaybedeployedtoobtainminimalswitchinglossandhighereciencyaswell[13].Inaddition,thesoft{switchingtopologyexhibitsbettereciencythanthehard{switchingtopology[13]. Figure1.4:EectofDead{timeonOutputVoltage Inaddition,allthehardswitchingtopologieswithdead{timeincreasethelosses,oneofthemainresultingdicultiesbeingthesnubberdesignintheACchoppers.Fig.1.4showsthedead{timeeectintheVSC.Assumingthattheoutputcurrentowsoutfromthephase{legasshowninFig.1.4,thecurrentowsthroughtheuppertransistorTU;whenthelatterison,whilethelowerdiodeDLinducesafree{wheelingwhentheuppertransistorTUiso.Inthis5

PAGE 18

situation,thedirectionofthedrainingcurrentispositive.Thus,onlytheuppertransistorTUandthelowerdiodeDLareactive,whichensuresthereisapathfortheloadcurrenttoow.Whenthecurrentowsinanegativedirection,onlythelowertransistorTLisonandfreewheelsthroughtheupperdiodeDU.Bothtransistorscannotbeonnorosimultaneously;theyswitchcomplementarily[7].Duringthedead{time,bothswitchesSUandSLareo.Forinstance,intheinductiveload,theoutputvoltagedependsonthedirectionoftheoutputcurrentwhichisconductedduringthedead{timebyeithertheupperorthelowerdiodeandvoltagegainorlosswilloccurasaresult.Therefore,thepositivepulsesandthenegativepulsesinFig.1.4correspondtothegainandlossofthevoltage,respectively[21]. AcomparativeevaluationofAC{ACvectorswitchingmatrixconverters,inordertoevaluatelossandeciency,hasbeenpresentedfordierenttopologiesfeedingthesameload.Thesemi{softswitchingtechniqueandhardswitchingtechniquehavebeenimplementedanddetailedusingcomputer{matlabsimula-tiontoprovetheoperationprincipleofeachtechnique.6

PAGE 19

2.MultipleStepsSwitchingCapability 2.1ExaminedTopologies Inthischapter,alltheswitchesareconsideredidealandnodead{timeistakenintoaccountinalltheexaminedtopologies. Theswitchingprocessinthetopologiesdependsonthecurrentdirectionintheload.Therefore,accordingtothecurrentdirectiontherearesixdierentcasesoroperationmodes;eachcaseis60asitshowninFig.2.1. Figure2.1:CurrentDirectionStates So,ndingthedirectionoftheloadcurrentrequiresdigitalindicatorsasshowninFig.2.2(a),whichgivezerowhentheloadcurrentisnegativeoronewhentheloadcurrentispositive.Consequently,comparingthevalueofloadcurrentwithzeroateachphasegeneratesthesix{pulsecasesasitisshowninTable2.17

PAGE 20

Currents Case1 Case2 Case3 Case4 Case5 Case6 ia 1 1 1 0 0 0 ib 0 0 1 1 1 0 ic 1 0 0 0 1 1 Table2.1:Six{PulseCases Ingeneral,themultiplestepsswitchingstrategycanbesummarizedasfol-lows[14]:1. Detectthedirectionofthecurrentload.2. Switchothetransistorthatisnotdraininganycurrentatpresent.3. Switchonthetransistorwhichwilldraintheloadcurrentinthesamedirection.4. Switchothetransistorwhichispresentlydrainingtheloadcurrent;thiswillmakeanewpathforthecurrent.5. Switchontheothertransistorsintheactiveswitch. Whenthecurrentiszero,itisnotimportantiftheoutputsignaliszeroorone.Therefore,thecurrentcanbeconsideredasanegativecurrentorapositivecurrentintheswitchingprocess(Ia=1ispositiveandIa=0isnegative).Thischapterdescribesthetopologiesandtheswitchingstrategiesforeach.8

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(a)CurrentDirectionSignals (b)ControlSignalsforMultipleStepsSwitching Figure2.2:GeneratedSignals 2.2FirstTopologywith6Switchesand6Diodes ThersttopologyisshowninFig.2.3withtwothree{phaseswitchesusingthemultiplestepsswitchedBuck{typeACchopperhalfofthetime.TurningtheswitchesonandointhistopologyneedseightcontrolsignalsthatareshowninFig.2.2(b).Thistopologyimplementsthemultiplestepsswitchingtechniqueinahalfpowerperiodoftimeandahardswitchingtechniquefortheotherhalfpowerperiod.Inotherwords,itisnotpossibletodosoftswitchingforallswitchesduringtheentirepowerperiod. Notethatthetwothree{phaseswitchescannotbeclosedatthesametimeinthistopologybecausethiscausesashortcircuitonthethreephasevoltagesource.Similarly,boththree{phaseswitchescannotbeopenatthesametimeinthistopologybecausetheloadwillbedisconnectedandremaininanopencir-cuit,whichmaygeneratevoltagespikes[4].Inthecaseofdoinghardswitching,oneofthethree{phaseswitchesshouldbeclosedwhiletheotherswitchisopen9

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Figure2.3:FirstTopologyandviceversa.However,theswitchingtechniqueinthistopologyisappliedbythefollowingtwoprocedures:1. Thecases1,3and5inFig.2.1usethesignalsX5;X6;X7andX8,whichareshowninFig.2.2(b)tocontrolthetwoswitchesthatdrainthecurrentatthesametimeandthehardswitchingtechniquecanbeachievedthroughthefollowingprocedure:(a) Switchothetransistorthatisnotdraininganycurrentintheactivethree{phaseswitch.(b) Switchonthetwotransistorswhichwillbenallydrainingthecur-rentinthenon{activethree{phaseswitchandswitchothetwotransistorsthataredrainingthecurrentintheactivethree{phaseswitchatthesametime(thisisahardswitching).(c) Switchontheotherswitchinthethree{phaseswitchthatisnally10

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drainingthecurrent. Precisely,thisprocedureisimplementedwhenthecurrentispositiveintwophasesandnegativeintheotherphase.Forexample,whenthecurrentinbothphasesAandCispositiveandnegativeinphaseB(thisiscase1)asshowninFig.2.4. Figure2.4:Case1,iaandicarePositive,ibisNegative Fig.2.5showstheswitchingprocessforcase1whenthecurrentinphasesAandCispositiveandisnegativeinphaseB.Inthiscase,theloadisconnectedtotheinputvoltagesourcewiththeswitchesS1;S2&S3whiletheotherswitchesareo.Followingtherstprocedurementionedabove,thetransistorthatisnotdraininganycurrentisS2.Thus,Fig.2.5(b)showsthedirectionofthecurrentsafterswitchingoS2whichremainedconstantandowingthroughS1&S3keepingtheloadconnectedtothevoltagesource.Instate3,afterswitchingonS4&S6simultaneouslywith11

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switchingoS1&S3(thisisahardswitching),theinputvoltagesourcewillbedisconnectedandtheloadwillbeshortedinanewpaththroughS4;S5&S6tokeeptheloadcurrentsowinginthesamedirectionsascanbeseeninFig.2.5(c).Finally,switchonS5inFig.2.5(d)whichisnotdraininganycurrentinthiscase.Itisimportanttomentionthattheswitchingtechniqueinthiscaseisonlyhardswitching.However,thesoftswitchingwillbeappliedinthenextcasebyfollowingthesecondprocedure:2. Inthecases2,4and6inFig.2.1,thereisonlyonetransistorthatdrainsapositivecurrentallthetimeandtheothertwonegativecurrentswillbeowingthroughthediodes.So,accordingtothecurrentdirectionintheload,thesecasesusethesignalsX1;X2;X3andX4,whichareshowninFig.2.2(b)tocontroltheswitchesandtoimplementthemultiplestepsswitchingtechniquebyfollowingthenextprocedure:(a) Switchothetwotransistorsthatarenotdraininganycurrentinthetwophasesthathaveanegativecurrentintheactivethree{phaseswitch.(b) Switchonthetransistorthatwillbedrainingthepositivecurrentintheotherphaseinthenon{activethree{phaseswitch.(c) Switchothetransistorthatisdrainingthepositivecurrentintheactivethree{phaseswitchsotheotherthree{phaseswitchwillbeactivatedasaresult.(d) Switchontheothertwotransistorsintheactivethree{phaseswitch.12

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(a)State1,S1&S3aredrainingapositivecurrent (b)State2,turn{oS2whilethecurrentsarestillowingthroughS1&S3 (c)State3,S4&S6aredrainingapositivecurrent (d)State4,turn{onS5whichisnotdraininganycurrent Figure2.5:SwitchingProcessduringCase113

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Previouscasesoccurwhenthecurrentisnegativeintwophasesandispositiveintheotherphase.Forexample,case2iswhenthecurrentinphasesBandCisnegative,andthecurrentinphaseAisnegative,Fig.2.6. Figure2.6:Case2,ibandicareNegative,iaisPositive Fig.2.7showstheswitchingprocessforcase2whenthecurrentinthephasesBandCisnegativeandthecurrentinthephaseAispositive.Inthiscase,theloadisconnectedtotheinputvoltagesourcewiththeswitchesS1;S2&S3whiletheotherswitchesareo.Followingthesecondprocedurementionedabove,thetwotransistorsthatarenotdraininganycurrentinthiscaseareS2&S3.Therefore,State1inFig.2.7(a)showstheloadconnectedtotheinputvoltagesourcewiththeswitchesS1;S2&S3whiletheotherswitchesareoandasitcanbeseen,inthesamegure,thetransistorsintheswitchesS2&S3arenotdraininganycurrent.However,inState2Fig.2.7(b)afterswitchingo(S2&S3),S1istheonlytransistorthatdrainscurrent.Tokeepthecurrentowinginthesamedirection,itshouldswitchonS4beforedisconnectingthe14

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inputvoltagesourcefromtheloadasinState3Fig.2.7(c).InState4,Fig.2.7(d)switchingothetransistorthatisdrainingthepositivecurrentwhichisS1,willimmediatelychangethecurrentpathandkeepthecurrentsowinginthesamedirectionsintheload.ItcanbenotedthattheswitchS1inthiscaseistheonlyswitchthatcancontrolthecurrentpath.Finally,switchontheothertwotransistorsS5&S6inthethree{phaseswitchthatiseventuallydrainingthecurrentasshowninState5,Fig.2.7(e). 2.3SecondTopologywith12Switchesand12Diodes ThistopologyisshowninFig.2.8;eachphaseinthethree{phasevoltagesourcehasfourswitchestoperformmultiplestepsswitchingtechniqueinaBuck{typeACchopperallthetime,whilethersttopologyhasonlytwoswitches.Therefore,thenumberofswitcheshasbeenincreasedinthistopology.Conse-quently,turningtheswitchesonandointhistopologyrequiresfourcontrolsignalsonly,unliketheprevioustopology.Thistopologyimplementsthemulti-plestepsswitchingtechniquethroughouttheentirepowerperiod.However,oneofthetwothree{phaseswitchesisonforhalfofthetimeandisotheotherhalfofthetime.Asmentionedaboveonlyoneofthetwelvetransistorsdrainsacurrentataparticulartimeinthesixcases. ThistopologyisslightlydierentfromthersttopologybecausetheloadcanbeconnectedtothevoltagesourcebytheswitchesS1;S2&S3orbytheswitchesS7;S8&S9whiletheswitchesS4toS6&S10toS12areo.However,theinputvoltagesourcewillbedisconnectedandtheloadwillbeshortedbytheswitchesS4;S5&S6ortheswitchesS10;S11&S12whiletheswitchesS1toS1&S7toS9areo.Ontheotherhand,whenthecurrentispositiveinone15

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(a)State1,S1isdrainingapositivecurrent (b)State2,turn{oS2&S3,thecurrentisowingthroughS1 (c)State3,turn{onS4thetransistorS1isstilldrainingapositivecurrent (d)State4,turn{oS1,thecurrentpathchangedandS4isdrainingthecurrent (e)State5,turn{onS5&S6,thetransistorS4isstilldrainingapositivecurrent Figure2.7:SwitchingProcesswhenibandicareNegativeandiaisPositive16

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phaseandisnegativeintheothertwophases,theswitchesS1toS6willconductthecurrentwhiletheothersixswitchesareoduringthiscase.Intheothercase,whenthecurrentispositiveintwophasesandnegativeintheotherphase,theswitchesS7toS12willconductthecurrentswhiletheothersixswitchesareoduringthiscase.Thispatternguaranteesthatonlyonetransistorwilldraincurrentataspecictimeandappliesthemultiplestepsswitchingtechnique. Similartotheprevioustopology,theswitchingprocessdependsonthecur-rentdirectionintheload.ThistopologyusesthesignalsX1;X2;X3andX4thatareshowninFig.2.2(b)tocontroltheswitchesandimplementsthemultiplestepsswitchingtechniquebyfollowingthenextprocedure:1. Switchothetwotransistorsthatareconnectingtheinputvoltagesourcetotheloadandarenotdraininganycurrentintheactivethree{phase Figure2.8:SecondTopology17

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switchatpresent.2. Switchonthetransistorthatwilldisconnecttheinputvoltagesourcefromtheloadbyshortingtheload.Also,thisswitchisinthenon{activethree{phaseswitchanditwilldrainthecurrentinthesamedirection.3. Switchothetransistorthatiscurrentlydrainingthecurrentintheactivethree{phaseswitch.So,theotherthree{phaseswitchwillbeactivatedasaresultandthecurrentwillstartowingthroughthetransistorthatisalreadyonandthroughtheanti{paralleldiodesoftheotherswitches.4. Switchontheothertwotransistorsintheactivethree{phaseswitch. Takingcase4Fig.2.1asanexampleofthistopology,Fig.2.9showstheswitchingprocesswhenthecurrentinphasesAandCisnegativeandthecur-rentinphaseBispositive.Inthiscase,theloadisconnectedtotheinputvoltagesourcewiththeswitchesS1;S2&S3whilealltheotherswitchesareo.Followingtheprocedurementionedabove,thetwotransistorsthatarenotdraininganycurrentinthiscaseareS1&S3.Thus,State1inFig.2.9(a)showstheloadconnectedtotheinputvoltagesourcewiththeswitchesS1;S2&S3whiletheotherswitchesareo.AlthoughS1&S3areon,thetransistorsarenotdraininganycurrent.However,inState2Fig.2.9(b)afterswitchingoS1&S3,S2istheonlytransistordrainingcurrent.Tokeepthecurrentowinginthesamedirection,S5shouldbeswitchedonbeforedisconnectingtheinputvoltagesourcefromtheloadasinState3Fig.2.9(c).InState4,Fig.2.9(d)switchingothetransistorthatispresentlydrainingthecurrentwhichisS2,willimmediatelychangethecurrentpathbymakingashortontheloadand18

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keepingthecurrentsowinginthesamedirectionsintheload.ItcanbenotedthattheswitchS2,inthiscase,istheonlyswitchthatcancontrolthecurrentpath.Finally,switchontheothertwotransistorsS5&S6inthethree{phaseswitchthatiseventuallydrainingthecurrentasshowninState5,Fig.2.9(e).Signicantly,inalltheStatesthereisonlyonetransistordrainingcurrent.19

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(a)State1,S2isdrainingapositivecurrent (b)State2,turn{oS1&S3,thecur-rentisowingthroughS2 (c)State3,turn{onS5thetransistorS2isstilldrainingapositivecurrent (d)State4,turn{oS2,thecurrentpathchangedandS5isdrainingthecurrent (e)State5,turn{onS4&S6,S5isstilldrainingapositivecurrent Figure2.9:SwitchingProcesswheniaandicareNegativeandibisPositive20

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2.4ThirdTopologywith2Switchesand14Diodes ThetopologyisshowninFig.2.10.ThistopologyusesonlytwodrivingswitchesS1andS2whichmakestheswitchingstrategyeasy.Thesetwoswitchesareusedtoconnecttheloadtothethree{phasesourceanddisconnectitaswell.So,whenoneofthetwoswitchesison,theotheroneshouldbeoandviceversa.Inaddition,bothswitchescannotbeclosedatthesametime,becausethiswillshorttheinputvoltagesource.Also,theycannotbeopenatthesametime,becausetheinductor'scurrentpathshouldnotbeopen. Figure2.10:ThirdTopology Also,thereisnomultiplestepsswitchingtechniquethatcanbeappliedinthistopologybuteachoftheswitchesS1andS2isrealizedusingaDiode{Bridgeandonlyoneactiveswitch.21

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3.Average&RMSCurrents InthischaptertheaverageandRMScurrentsfortheswitchesbesidetheACsourcewillbepresentedingeneralformulasforthethreetopologiesasfollows: 3.1FirstTopology[6switchesand6diodes] TheshapesofthewaveformsinthistopologyareshowninFig.3.1. (a)CurrentthroughtheDiode (b)CurrentthroughtheTransistor Figure3.1:CurrentWaveformsoftheSwitches. 3.1.1AverageDiodeCurrent =^IPole TPn=2Xi=0(Z(TPd n+iTP n)iTP nsin(2 TPt)dt)(3.1) WherenXi=0cos(ai)=sin(a 2(n+1))cos(a 2n) sin(=n)(3.2) nXi=0sin(ai)=sin(a 2(n+1))sin(a 2n) sin(=n)(3.3)22

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=^IPole 2"sin(2d n)cos( n) sin( n)#(3.4) 3.1.2RMSDiodeCurrent I2drms=^I2Pole TPn=2Xi=0(Z(TPd n+iTP n)iTP nsin2(2 TPt)dt)(3.5) Idrms=^IPoled 4+d 2n)]TJ /F1 11.955 Tf 16.69 8.08 Td[(1 8sin(4d n)1=2(3.6) Notethattheshapeoftheswitchcurrentinthistopologyisthesameastheshapeofdiodecurrent. 3.1.3AverageTransistorCurrent =^IPole TPn=2Xi=0(Z(TPd n+iTP n)iTP nsin(2 TPt)dt)(3.7) =^IPole 2"sin(2d n)cos( n) sin( n)#(3.8) 3.1.4RMSTransistorCurrent I2drms=^I2Pole TPn=2Xi=0(Z(TPd n+iTP n)iTP nsin2(2 TPt)dt)(3.9) Itrms=^IPoled 4+d 2n)]TJ /F1 11.955 Tf 16.68 8.09 Td[(1 8sin(4d n)1=2(3.10)23

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3.2SecondTopology[12switchesand12diodes] TheshapesofthewaveformsinthistopologyareshowninFig.3.2. (a)CurrentthroughtheDiode (b)CurrentthroughtheTransistor Figure3.2:CurrentWaveformsoftheSwitches. 3.2.1AverageDiodeCurrent =^IPole TPn=6Xi=0(Z(TPd n+iTP n)iTP nsin(2 TPt)dt)+^IPole TPn=6Xi=0(Z(2 3+TPd n+iTP n)(2 3+iTP n)sin(2 TPt)dt)(3.11) =^IPole 2"sin( 6+ n)sin(2d n) sin( n)#(3.12) 3.2.2RMSDiodeCurrent Idrms2=^I2Pole TPn=6Xi=0(Z(TPd n+iTP n)iTP nsin2(2 TPt)dt)+^I2Pole TPn=6Xi=0(Z(2 3+TPd n+iTP n)(2 3+iTP n)sin2(2 TPt)dt)(3.13)24

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Idrms=^IPole"d 6+d n)]TJ /F1 11.955 Tf 16.69 8.09 Td[(1 8sin( 3+2 n)sin(4d n) sin(2 n)#1=2(3.14) 3.2.3AverageTransistorCurrent =^IPole TPn=6Xi=0(Z( 3+TPd n+iTP n)( 3+iTP n)sin(2 TPt)dt)(3.15) =^IPole 2"sin(2d n)sin( 6+ n) sin( n)#(3.16) 3.2.4RMSTransistorCurrent I2trms=^I2Pole TPn=6Xi=0(Z( 3+TPd n+iTP n)( 3+iTP n)sin2(2 TPt)dt)(3.17)Itrms=^IPole"d 12+d 2n+1 8sin( 3+2 n)sin(4d n) sin(2 n)#1=2(3.18) 3.3ThirdTopology[2Switchesand14Diodes] TheshapesofthewaveformsinthistopologyareshowninFig.3.3. 3.3.1AverageDiodeCurrent =^IPole TPn=2Xi=0(Z(TPd n+iTP n)iTP nsin(2 TPt)dt)(3.19) =^IPole 2"sin(2d n)cos( n) sin( n)#(3.20)25

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3.3.2RMSDiodeCurrent I2drms=^I2Pole TPn=2Xi=0(Z(TPd n+iTP n)iTP nsin2(2 TPt)dt)(3.21) Idrms=^IPoled 4+d 2n)]TJ /F1 11.955 Tf 16.69 8.08 Td[(1 8sin(4d n)1=2(3.22) 3.3.3AverageTransistorCurrent =^IPole =3n=6Xi=0(Z( 3+TPd n+iTP n)( 3+iTP n)sin(2 TPt)dt):(3.23) =^IPole =3"sin(2d n)sin( 6+ n) sin( n)#(3.24) 3.3.4RMSTransistorCurrent I2trms=^I2Pole =3n=6Xi=0(Z( 3+TPd n+iTP n)( 3+iTP n)sin2(2 TPt)dt)(3.25) (a)CurrentthroughtheDiode (b)CurrentthroughtheTransistor Figure3.3:CurrentWaveformsoftheSwitches26

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Itrms=p 6^IPole"d 12+d 2n+1 8sin( 3+2 n)sin(4d n) sin(2 n)#1=2(3.26) Table3.1:AverageandRMScurrentsforthethreetopologies Topology Device Current Formula 1 Diode Iave ^IPole 2hsin(2d n):cos( n) sin( n)i Diode Irms ^IPoled 4+d 2n)]TJ /F4 7.97 Tf 15.72 4.71 Td[(1 8sin(4d n)1=2 Transistor Iave ^IPole 2hsin(2d n):cos( n) sin( n)i Transistor Irms ^IPoled 4+d 2n)]TJ /F4 7.97 Tf 15.72 4.7 Td[(1 8sin(4d n)1=2 2 Diode Iave ^IPole 2hsin( 6)]TJ /F12 5.978 Tf 7.8 3.25 Td[( n)sin(2d n) sin( n)i Diode Irms ^IPolehd 6+d n)]TJ /F4 7.97 Tf 15.73 4.71 Td[(1 8sin( 3+2 n)sin(4d n) sin(2 n)i1=2 Transistor Iave ^IPole 2hsin(2d n)sin( 6+ n) sin( n)i Transistor Irms ^IPolehd 12+d 2n+1 8sin( 3+2 n)sin(4d n) sin(2 n)i1=2 3 Diode Iave ^IPole 2hsin(2d n)cos( n) sin( n)i Diode Irms ^IPoled 4+d 2n)]TJ /F4 7.97 Tf 15.72 4.7 Td[(1 8sin(4d n)1=2 Transistor Iave ^IPole =3hsin(2d n)sin( 6+ n) sin( n)i Transistor Irms p 6^IPolehd 12+d 2n+1 8sin( 3+2 n)sin(4d n) sin(2 n)i1=2 TheformulasintheTable3.1presenttheaverageandRMScurrentsforthedevicesthatconnecttheloadtothesource.However,theotherdevicesusethesameformulasafterchanging(d)to(1-d).27

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4.SwitchingLossesCalculations Theswitchinglossdependsontheenergydissipatedateveryswitchingeventforbothtransistoranddiodesemiconductors,sotheswitchingenergyinsemiconductorsisusuallyassumedtobeproportionaltotheconductingcurrentandtheblockingvoltageateachswitchingeventasfollows[12], Ei=ER VRIRviii(4.1) whereER,VRandIRrepresentthereferencevaluesoftheenergyloss,theblockingvoltage,andtheconductingcurrentrespectively.Thesevaluesareusuallyonthemanufacturer'sdatasheets.Therefore,thetotalpowerlossoveronepowerperiodisasfollows: PS=FpXiEi(4.2) InbothtopologiesthatareshowninFig.4.1andFig.4.3,theblockingvolt-ageisline{linevoltageandtheconductingcurrentisthepolecurrentmultipliedbythedutyratio. Beforecalculatingthelossestherearesomeconsiderationswhichhavetobetakenintoaccount.Theseconsiderationsconcerntheswitchinglossesforthediodesatturn{onandturn{oevents.Firstofall,thediodeshavenoturn{onswitchinglosses,becausewhenthetransistorison(carryingthecurrent),thecurrentthroughthediodeiszero.Therefore,atturn{onthereisnoswitchingloss.Moreaccurately,thediodeblocksthecurrentwhenitisreversebiased.In28

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thecaseofasilicondiode,forexample,whenitisforwardbiased,itdoesnotdrainanycurrentuntil0.7Visappliedacrossit,sowhenthediodeisturnedonitwilldrainacurrent;however,thevoltageacrossthediodewillnotdropmorethan0.7V,eventhoughtheinputvoltageoftheconverterisgreater.Con-sequently,theswitchinglossesforthediodesarenegligible. Secondly,thediodeshaveswitchinglossesattheturn{oevent,butthisisafunctionofthevoltagetheyareblockingandthereverserecoverycurrent(nottheloadcurrent).Precisely,thereverserecoveryinthediodeoccurswhenanegativevoltageisappliedacrossthediode.Inotherwords,whenthediodeisinaforwardconduction(loadcurrent),itwillstopconductingatthemomentwhenanegativevoltageisappliedacrosstheterminalsofthediodeforcingthediodetoturno.Hence,incomparisonwiththetransistorswitchinglosseswhichareafunctionoftheline{linevoltageandtheloadcurrent,turn{olossesinthediodesrepresentasmallamountofpower.Finally,inthischapter,thedeadtimeisnotconsideredfortheswitchthathashardswitchingandtherearenoswitchinglossesforthediodesinthethreeexaminedtopologies. InthetopologyshowninFig.4.1,thetransistorst1,t2andt3haveahardswitchingforhalfofthepowerperiod(Tp 2=),wheneverthecurrentispositiveasshowninFig.4.2.Ontheotherhand,thetransistorst4,t5andt6havehardswitchingonlyforasixthofthepowerperiod(Tp 6= 3). InthetopologyshowninFig.4.3,thetransistorst1,t2,t3,t7,t8,andt9,bythevoltagesource,havehardswitchingforasixthofthepowerperiod(Tp 6= 3),asshowninFig.4.4andFig.4.5.However,theothertransistorshave29

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Figure4.1:FirstTopology Figure4.2:SwitchingCurrentsandBlockingVoltage30

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softswitchingasshowninFig.4.4andFig.4.5. InthetopologyshowninFig.4.6,thetransistorst1,andt2havehardswitch-ingduringtheentirepowerperiod. ThedevicesconnectedtophaseAinthetopologyshowninFig.4.1aret1andt4.Thestemplotfortheproductofthecurrentandthevoltageforthetransistorst1andt4attheturn{onandturn{oeventsisshowninFig.4.8.Also,theproductofthecurrentandthevoltageintheotherphasesBandCwillbethesame. ThetopologyshowninFig.4.3hasfourtransistorswhichareconnectedtophaseA.Fig.4.9showsthestemplotfortheproductofthecurrentandthevoltageforthetransistorst1,t4,t7andt10attheturn{onandturn{oevents.Also,theproductofthecurrentandthevoltageintheotherphasesBandC Figure4.3:SecondTopology31

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Figure4.4:SwitchingCurrentsandBlockingVoltage32

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Figure4.5:SwitchingCurrentsandBlockingVoltage Figure4.6:ThirdProposedTopology33

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Figure4.7:SwitchingCurrentsandBlockingVoltage Figure4.8:StemPlotforViIioft1andt4intheTopologyFig.4.134

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Figure4.9:StemPlotforViIioft1,t7,t4andt10intheTopologyFig.2.8willbethesame. InthetopologyshowninFig.4.6therearetwotransistorsintheconverter.Fig.4.10showsthestemplotfortheproductofthecurrentandthevoltageforonlyonetransistort1attheturn{onandturn{oevents.Also,theproductofthecurrentandthevoltagefortheothertransistort2willbethesame. Finally,itcanbeseenfromthestemplotsinFig.4.8andFig.4.9ofthetopologiesinFig.4.1andFig.4.3,respectively,thattheshapesarenotsimilar.However,thesumoftheproductatturn{onandturn{oofthetransistorsinbothtopologiesisequal.Signicantly,thetotalswitchinglossesinbothtopologiesinFig.4.1andFig.4.3arethreetimesthesumofthestemplotinFig.4.8andFig.4.9,respectively,whichareequal.ForthethirdtopologyFig.4.6,thetotalswitchinglossesaretwicethesumofthestemplotinFig.4.1035

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Figure4.10:StemPlotforViIioft1intheTopologyFig.4.6.becauseithasonlytwotransistors.Therefore,thetotalswitchinglossesinthethirdtopologyaredoubledcomparedtothetotalswitchinglossesintheothertwotopologies. Asmentionedabove,itcanbeseenfrom(4.1)thatthetopologieswillhavethesameswitchinglossesonlyiftheyarebuiltbysimilardevices.Actually,thedevicesarenotconductingthesameamountofcurrentinthetopologies,buttheyareblockingline{linevoltage,sothesizeofthedevicewillbedierentinthetwotopologieswhichmakesthereferencevaluesfortheenergylossandtheconductingcurrentin(4.1)havedierentvalues. Therefore,takingintoaccounttheswitchinglossesforeachdeviceintherstandsecondtopologiesattheturn{onandturn{oevents,theanalyticalformulathatexpressesthelosseshasbeendevelopedasfollows:36

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PS=3Fpp 12VinVout jZLoadj"n 3+p 3 2sin(2 n)cos(2 n(2d)]TJ /F1 11.955 Tf 11.95 0 Td[(1))+cos(2 n)#ER VRIR(4.3) However,theanalyticalformulathatexpressesthelossesforthethirdtopol-ogyisasfollows: PS=6Fpp 12VinVout jZLoadj"n 3+p 3 2sin(2 n)cos(2 n(2d)]TJ /F1 11.955 Tf 11.95 0 Td[(1))+cos(2 n)#ER VRIR(4.4) where, d:dutyratio(0d1)Vin:rmsvoltagesourceFp:powerfrequencyZLoad:R+jXLFsw:switchingfrequencyn:Fsw FpVout:outputvoltageoftheconverterwhichis: Vout=Vinp d(4.5) Incomparison,thedevicesinthetopologyshowninFig4.3with12switchesand12diodesareconductinglessamountofcurrentthanthedevicesinthetopologyshowninFig4.1.37

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5.HardSwitchingversusSemi{SoftSwitching Thischaptercomparesthersttwotopologiesaftertakingintoaccountthedead{timefortheswitchesthathavehardswitchingandthefactthattherearenoswitchinglossesforthediodesinbothtopologies. InbothtopologiesshowninFig.5.1andFig.2.8,theblockingvoltageisline{linevoltageandtheconductingcurrentisthepolecurrentmultipliedbythedutyratio. Theconductionlossforthediodesaswellasforthetransistorsisusuallymodeledbytheproductofthecurrentthroughthedeviceandthevoltagedropacrossthisdevice[12].Whenthevoltagedropacrossthedeviceisapproximatedbyalinearfunctiondependsonthecurrentasin(5.1), von(i)=Von+roni(5.1) therefore,theaveragepowerlosscanbedeterminedin(5.2)asfollows: PC=VonIavron+ron(Irmson)2(5.2) whereVonandronareusuallyavailableonthemanufacturer'sdatasheets. 5.1EvaluationofHardSwitchingConverter ThetopologywithhardswitchingisshowninFig.5.1.Thistopologyhassixswitchesthataredividedintotwodrivingthree{phaseswitchesSandS.ThesetwoswitchesSandSareusedtoconnecttheloadtothethree{phasesourceanddisconnectitaswell.Notethatthetwothree{phaseswitchescannot38

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Figure5.1:Buck{typeACChopper.beclosedatthesametimeinthistopologybecausethiscausesashortcircuitonthethreephasevoltagesource.Also,boththree{phaseswitchescannotbeopenatthesametimebecausetheloadwillbedisconnectedandremainsinanopencircuit,whichmaygeneratevoltagespikes[4].Therefore,inthecaseofdoinghardswitching,oneofthethree{phaseswitchesshouldbeclosedwhiletheotherswitchisopenandviceversa.Inotherwords,SandSswitchcomplementarilyasintheDC{DCconverters.Consequently,thistopologyhastohaveadead{timeandduringthistimetheloadcurrentwillowthroughthesnubbercircuitsandincreasethelossesespeciallyforthehighpowerconverters.Inaddition,eachdeviceneedsitsownsnubbertoavoidthevoltagespikesduringtheswitchingprocess.Thissnubbercircuitisusedtocarrytheloadcurrentduringturningotheswitch.Therefore,whentheswitchisturnedotheconductioncurrent39

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willstartchargingthecapacitorinthesnubbercircuitandthevoltagewillraiseasaresult.However,theACinputvoltageischoppedbytheconverterandthenlteredtogivetheoutputvoltagewaveformthathasthesameshapeandfrequencybutadierentamplitudewhichdependsonthedutyratio. Indeed,duringthedead{time,whichisessentialtoensurethatthereisnoshortcircuitonthesource,theloadcurrenthasnopathtogo;meanwhile,theloadcurrentcannotbeinterrupted.Ontheotherhand,thedead{timemustbeasnarrowaspossibletominimizethelossesduetovoltagespikesatturn{onandturn{oevents[18].Nevertheless,theloadcurrentwilldrainacrossthesnubbercircuitsincreasingthepowerlossesasaresultandthesnubbercircuitwillbebulkyforsuchtopology. 5.1.1SwitchingLossesCalculation TheenergystoredinthesnubbercapacitorCstransferstothesnubberresistorRsandtheswitcheverytimeitturnson.Also,theinductiveloadcur-rentcannotbechangedinstantlyduringturn{o.However,thiscurrentdivertsthroughthesnubberresistorRscausingvoltagespikesasshownintheFig.5.3.Ingeneral,thelossoftheconvertermainlyincludesthepowerdevicesconductionlossandswitchingloss.Sincethedevicedatasheetfromthemanufacturerpro-videsthereferencevaluesoftheenergylossin(4.1),thepowerdevicesswitchinglossoftheconvertercanbecalculatedbythefollowingexpression:40

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Ps=3FpVout jZLoadjnp 12Vin"n 3+p 3 2sin(2 n)cos(2 n(2d)]TJ /F1 11.955 Tf 11.96 0 Td[(1))+cos(2 n)#+2(Dt=Cs+Rs)Vout jZLoadj"n 3)]TJ 26.86 17.98 Td[(p 3 2sin(2 n)cos(2 n(2d)]TJ /F1 11.955 Tf 11.95 0 Td[(1))+ 3#oER VRIR(5.3) where, d:dutyratio(0d1)Vin:rmsvoltagesourceFp:powerfrequencyCs:snubbercapacitorFsw:switchingfrequencyRs:snubberresistorn:Fsw FpZLoad:R+jXLDt:dead{timeVout:outputvoltage Vout=Vinp d(5.4) 5.1.2ConductionLossesCalculation DependingontheEquation(5.2),thepowerdevicesconductionlossesoftheconvertercanbecalculatedasfollows:1ConductionlossforthediodesthatareconnectedtophaseAis: CondLossD1(d)=VondD1(d)+RondIRMSD1(d)2CondLossD4(d)=VondD4(d)+RondIRMSD4(d)22ConductionlossesforthetransistorsthatareconnectedtophaseAis: CondLossT1(d)=VontT1(d)+RontIRMST1(d)2CondLossT4(d)=VontT4(d)+RontIRMST4(d)2 Therefore,thetotalconductionlossesforthehardswitchingtopologyis:41

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TotalHS=3fCondLossD1(d)+CondLossT1(d)CondLossD4(d)+CondLossT4(d)g where, Vond;Rond;VontandRontareavailableonthemanufacturer'sdatasheets. disthedutycycle. d=1)]TJ /F1 11.955 Tf 11.96 0 Td[(d. Table5.1:AverageandRMScurrentsforthehardswitchingtopology Topology Device Current Formula Diode Iave ^Vout 2jZLoadjhsin(2d n):cos( n) sin( n)i Hard Diode Irms ^Vout jZLoadjd 4+d 2n)]TJ /F4 7.97 Tf 15.72 4.7 Td[(1 8sin(4d n)1=2 Switching Transistor Iave ^Vout 2jZLoadjhsin(2d n):cos( n) sin( n)i Transistor Irms ^Vout jZLoadjd 4+d 2n)]TJ /F4 7.97 Tf 15.72 4.71 Td[(1 8sin(4d n)1=2 Therefore, PC=3(Vond+Vont)^Vout jZLoadjcos( n)cos( n(2d)]TJ /F1 11.955 Tf 11.95 0 Td[(1))+3(Rond+Ront) ^Vout jZLoadj!21 4+1 2n)]TJ /F1 11.955 Tf 16.69 8.09 Td[(1 4sin(2 n)cos(2 2(2d)]TJ /F1 11.955 Tf 11.96 0 Td[(1))(5.5)42

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5.2EvaluationofSemi{SoftSwitchingConverter TheconvertershowninFig.2.8presentsanewtopologyofACchopperwithacapabilitytoperformsemi{softswitchinginmultiplesteps.Also,theswitchingtechniqueinthistopologyisverysimilartothefour{stepsemi{softcommutationthathasbeenusedintheMatrixConverter(MC)[20].Theadvan-tageofusingthistechniqueintheMCisthattheswitchinglossesarereducedby50%comparedtothehardswitching[20].Ontheotherhand,thefour{stepsemi{softcommutationintheMCsignicantlyincreasestheconductionlosses.However,thesemi{softtopologyovercomestheswitchingproblemsintheACchopperconverterswithoutincreasingtheconductionlossesofthedevices.Theswitchingprocessinthetopologydependsonthecurrentdirectionintheload.Therefore,accordingtothecurrentdirection,therearesixdierentcasesoroperationmodes;eachcaseis60asshowninFig.2.1. Thistopologyhasfourswitchesineachphasetodoamultiplestepsswitch-ingtechniqueinaBuck{typeACchopperallthetime,whilethersttopologyhasonlytwoswitchesineachphase.Therefore,thenumberoftheswitcheshasbeenincreasedinthistopology.Consequently,turningtheswitchesonandointhistopologyneedsfourcontrolsignals.Thistopologyimplementsthemultiplestepsswitchingtechniquethroughouttheentirepowerperiod.However,oneofthetwothree{phaseswitchesisonforhalfofthetimeandisotheotherhalfofthetime.Accordingly,onlyoneofthetwelvetransistorsdrainscurrentataparticulartimeinthesixcases.43

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ThistopologyisslightlydierentfromthersttopologybecausetheloadcanbeconnectedtothevoltagesourcebytheswitchesS1;S2&S3ortheswitchesS7;S8&S9whiletheswitchesS4toS6&S10toS12areo.However,theinputvoltagesourcewillbedisconnectedandtheloadwillbeshortedbytheswitchesS4;S5&S6ortheswitchesS10;S11&S12whiletheswitchesS1toS1&S7toS9areo.Ontheotherhand,whenthecurrentispositiveinonephaseandnegativeintheothertwophases,theswitchesS1toS6willconductthecurrentswhiletheothersixswitchesareoduringthiscase.Intheothercase,whenthecurrentispositiveintwophasesandisnegativeintheotherphase,theswitchesS7toS12willconductthecurrentswhiletheothersixswitchesareoduringthiscase.Thispatternguaranteesthatonlyonetransistorwilldraincurrentataspecictimeandappliesthemultiplestepsswitchingtechnique. TheswitchingprocessthatdependsonthecurrentdirectioninthisconverterhasbeenexplainedinChapter2 5.2.1SwitchingLossesCalculation Thereisnosnubbercircuitinthesemi{softtopologythatisshowninFig2.8.Followingthemultiplestepsswitchingtechnique,createsapathforthecurrent.ThiscurrentowsduringtheswitchingeventsasitshowninFig2.9Chapter2.Then,takingintoaccountthesameconsiderationsthatappliedinthehardswitchingtopology,theanalyticalformulathatexpressestheswitchinglossesinthesemi{softtopologycanbedevelopedasfollows: PS=3Fpp 12VinVout jZLoadj"n 3+p 3 2sin(2 n)cos(2 n(2d)]TJ /F1 11.955 Tf 11.95 0 Td[(1))+cos(2 n)#ER VRIR(5.6)44

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where, d:dutyratio(0d1)Vin:rmsvoltagesourceFp:powerfrequencyZLoad:R+jXLFsw:switchingfrequencyn:Fsw FpVout:outputvoltageoftheconverterwhichis: Vout=Vinp d(5.7) 5.2.2ConductionLossesCalculation DependingontheEquation(5.2),thepowerdevicesconductionlossesoftheconvertercanbecalculatedasfollows:1ConductionlossforthediodesthatareconnectedtophaseAis: CondLossD1+D7(d)=VondD1(d)+RondIRMSD1(d)2+VondD7(d)+RondIRMSD7(d)2=2VondD(d)+RondIRMSD(d)2CondLossD4+D10(d)=VondD4(d)+RondIRMSD4(d)2+VondD10(d)+RondIRMSD10(d)2=2VondD(d)+RondIRMSD(d)22ConductionlossesforthetransistorsthatareconnectedtophaseAis: CondLossT1+T7(d)=VontT1(d)+RontIRMST1(d)2+VontT7(d)+RontIRMST7(d)2=2VontT(d)+RontIRMST(d)2CondLossT4+T10(d)=VontT4(d)+RontIRMST4(d)2+VontT10(d)+RontIRMST10(d)2=2VontT(d)+RontIRMST(d)245

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Therefore,thetotalconductionlossesforthesemi{softswitchingtopologyis: TotalSmeiS=3fCondLossD1+D7(d)+CondLossT1+T7(d)CondLossD4+D10(d)+CondLossT4+T10(d)g where, Vond;Rond;VontandRontareavailableonthemanufacturer'sdatasheets. disthedutycycle. d=1)]TJ /F1 11.955 Tf 11.96 0 Td[(d. Table5.2:AverageandRMScurrentsforthesemi{softswitchingtopology Topology Device Current Formula Diode Iave ^Vout 2jZLoadjhsin( 6)]TJ /F12 5.978 Tf 7.81 3.26 Td[( n)sin(2d n) sin( n)i Semi{Soft Diode Irms ^Vout jZLoadjhd 6+d n)]TJ /F4 7.97 Tf 15.73 4.71 Td[(1 8sin( 3+2 n)sin(4d n) sin(2 n)i1=2 Switching Transistor Iave ^Vout 2jZLoadjhsin(2d n)sin( 6+ n) sin( n)i Transistor Irms ^Vout jZLoadjhd 12+d 2n+1 8sin( 3+2 n)sin(4d n) sin(2 n)i1=2 Therefore, PC=3(Vond+Vont)^Vout jZLoadjcos( n)cos( n(2d)]TJ /F1 11.955 Tf 11.95 0 Td[(1))+3(Rond+Ront) ^Vout jZLoadj!21 4+1 2n)]TJ /F1 11.955 Tf 16.69 8.09 Td[(1 4sin(2 n)cos(2 2(2d)]TJ /F1 11.955 Tf 11.96 0 Td[(1))(5.8)46

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5.3SwitchingProcess 5.3.1HardSwitching Fig.5.2showstheswitchingsignalsforthehardswitchingtopologyandthedead{time.Itcanbeenseenfromthegurethatalltheswitchesareoduringthedead{timeandtheloadcurrentwillowthroughthesnubbercircuitcausingvoltagespikesasshowninFig.5.3 Figure5.2:HardSwitchingPulses 5.3.2Semi{SoftSwitching Fig.5.4showstheswitchingsignalsforthesemi{softswitchingtopologywiththepulsesofthecurrentdirections.Althoughtherearetwelveswitchesin47

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(a)PhaseA (b)PhaseB (c)PhaseC Figure5.3:SwitchingCurrentsandVoltages48

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thesemi{softswitchingtopologyshowninFig2.8,thereareonlythreeswitcheswhichareonallthetimeascanbeseeninFig.5.5byzoominginonFig.5.4 Figure5.4:Semi{SoftSwitchingPulses49

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Figure5.5:Semi{SoftSwitchingPulses 5.4LOSSESANDEFFICIENCYCOMPARISONOFBOTHCONVERTERS AcompletelistofparametersispresentedinTable5.3forbothtopologies. Table5.4showstheresultoftheanalyticalcalculationscomparedagainstmatlabsimulations.Itcanbeseenthattheresultsfrombothmethodsareap-proximatelyconsistent.Duringoneswitchingperiodinthesemi{softswitchingtopology,thereisonlyoneswitchthathashardswitchingandtheotherswitcheshavesoftswitching.Ingeneral,alltheswitchesthatconnecttheloadtothesourcehavehardswitchingasshowninFig.5.6.However,theothersixswitcheshavesoftswitchingallthetimeasshowninFig.5.7.Consequently,theswitch-50

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Table5.3:PrototypeParameters SystemParameters Mains Vin=208(V),Fp=60(Hz) Isolationtransformer n=1:1 Load R=100(),L=100(mH),SL=405(VA) HardSwitchingConverterParameters MOSFETs FDD6N50,VDS=500(V),ID=6(A) SnubberCircuit Rs=700(),Cs=0:2(F) DutyCycle 50% Switchingfrequency 1.2(kHz) Dead{Time 2(sec) Semi{SoftSwitchingConverterParameters MOSFETs FDP5N50F,VDS=500(V),ID=4(A) Switchingfrequency 1.2(kHz) DutyCycle 50% 51

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inglossesaredistributedinthesixswitchesbesidethevoltagesource,whiletheothersixswitcheshavenoswitchinglossesatall. Table5.4:LossCalculation HardSwitching AnalyticalSolutionComputerSimulation SwitchingLosses4.9(W)4.61(W) ConductionLosses3.26(W)3.27(W) Semi{SoftSwitching AnalyticalSolutionComputerSimulation SwitchingLosses2.72(W)2.46(W) ConductionLosses3.26(W)3.24(W) Themainadvantageofhardswitchingisthatthereisnoneedtomeasuretheloadcurrent,whilethedisadvantageisthedesignofthesnubbercircuitwhichisnecessarytodohardswitching.However,themaindisadvantageofsemi{softswitchingistheneedtoknowthecurrentdirection.Also,measuringdevicesareexpensiveinhighpowerapplications.Ingeneral,semi{softswitchingismoreecientthanhardswitchingasshowninFig.5.9(a),andtheswitchinsemi{softswitchingtopologyovercametheACchoppersswitchingproblemswithoutincreasingtheconductionlossesasshowninFig.5.8(a)andFig.5.8(b). 5.5SemiconductorsRatings Powersemiconductorofthedevicecanbespeciedbythemaximumvoltagethedevicecanblockandtheaveragecurrentthedeviceconducts.Theanalytical52

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Figure5.6:TheSwitcheswithHardSwitching Figure5.7:TheSwitcheswithSoftSwitching53

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(a)ConductionLosses (b)SwitchingLosses Figure5.8:ConductionandSwitchingLosses54

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formulasthatexpresstheratingscanbedevelopedasfollows: 5.5.1HardSwitching Si(VA)=3VoT1(d)+D1(d)+T4(d)+D4(d)=3Vo^Vout 2jZLoadj4cos( n)cos( n(2d)]TJ /F1 11.955 Tf 11.96 0 Td[(1)) 5.5.2Semi{softSwitching Si(VA)=3VofT1(d)+D1(d)+T7(d+D7(d)+T4(d)+D4(d)+T10(d)+D10(d)g=3Vo^Vout 2jZLoadj4cos( n)cos( n(2d)]TJ /F1 11.955 Tf 11.96 0 Td[(1)) Althoughthenumberofthedeviceshasbeenincreasedinthesemi{softswitching,thetotalsemiconductor(VA)forbothtopologiesisthesameasshowninFig.5.9(b).55

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(a)Eciency (b)PowerSemiconductor Figure5.9:EciencyandPowerSemiconductor56

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5.6ConclusionandFutureWork 5.6.1Conclusion TherearevarioustopologiesforimplementinganACchopperindistributionsystems,aswellasintransmissionsystems.Therefore,thesemi{softswitchingtopologycanbeusedinapplicationssuchasvoltagecontrolatsensitiveloads,voltagesagcompensatorsinthedistributionsystem,andpowerowcontroltransmissionpowersystems. Forreducingturn{onandturn{olossesinthepowerswitchingdevices,thesemi-softswitchingtopologyshowsbettereciencythanthehardswitchingtopology.Alltheformulasinbothtopologiesmaybeusedforestimatinglossesandinthedesignofsuchconverters.Finally,afterconsideringtheeectsofdeadtimeinthehardswitchingtopology,theresultdeviatesfromtheidealone. Althoughthenumberofswitchesinthesemi{softswitchingtopologywasincreased,thetotalofconductionlossesdidnotincrease. 5.6.2FutureWork Theworkinthisresearchmaybeextendedtoexperimentalimplementationinthelab,inordertocomparethesimulationresultswiththeexperimentalresults.Also,aclosedloopcontrollermaybedesignedtodealwithunbalancedissuesbychangingthedutycycle.57

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REFERENCES[1] J.J.GraingerandW.D.Jr.Stevenson.Powersystemanalysis.InMcGraw-Hill,NY,1994.[2] L.Gyugyi.DynamiccompensationofACtransmissionlinesbysolid{statesynchronousvoltagesources.IEEETransactionsonPowerDelivery,9(2):904{911,April1994.[3] N.G.Hingorani.Powerelectronicsinelectricutilities:roleofpowerelec-tronicsinfuturepowersystems.ProceedingsoftheIEEE,76(4):481{482,April1988.[4] Y.Jang-HyounandK.Bong-Hwan.Switchingtechniqueforcurrent{controlledAC{to{ACconverters.IEEETransactionsonIndustrialElec-tronics,46(2):309{318,April1999.[5] M.F.KangarluandE.Babaei.OperationofACchopperasdownstreamfaultcurrentlimiterandovervoltagecompensator.InPowerElectronicsDriveSystemsandTechnologiesConference(PEDSTC),20112nd,pages403{407,Tehran,Iran,Feb2011.[6] J.W.Kolar,T.Friedli,J.Rodriguez,andP.W.Wheeler.Reviewofthree{phasePWMAC{ACconvertertopologies.IEEETransactionsonIndus-trialElectronics,58(11):4988{5006,Nov2011.[7] C.LihuaandP.Fang-Zheng.Dead{Timeeliminationforvoltagesourceinverters.IEEETransactionsonPowerElectronics,23(2):574{580,March2008.[8] L.A.C.LopesandG.Joos.Pulsewidthmodulatedcapacitorforseriescompensation.IEEETransactionsonPowerElectronics,16(2):167{174,March2001.[9] F.Mancilla-David,S.Bhattacharya,andG.Venkataramanan.Acompar-ativeevaluationofseriespower{owcontrollersusingDC{andAC{linkconverters.IEEETransactionsonPowerDelivery,23(2):985{996,April2008.58

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[19] L.WeiandT.A.Lipo.Anovelmatrixconvertertopologywithsimplecommutation.InIndustryApplicationsConference,2001.Thirty{SixthIASAnnualMeeting.ConferenceRecordofthe2001IEEE,volume3,pages1749{1754,Chicago,IL,Sep{Oct2001.[20] P.W.Wheeler,J.Rodriguez,J.C.Clare,L.Empringham,andA.Weinstein.Matrixconverters:Atechnologyreview.IEEETransactionsonIndustrialElectronics,49(2):276{288,April2002.[21] C.M.Wu,L.Wing-Hong,andH.Shu-HungChung.AnalyticaltechniqueforcalculatingtheoutputharmonicsofanH{bridgeinverterwithdeadtime.IEEETransactionsonCircuitsandSystemsPartI:FundamentalTheoryandApplications,46(5):617{627,May1999.60