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Non-volatile memories, optimal design and performance

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Title:
Non-volatile memories, optimal design and performance
Creator:
Nevedrov, Dmitri
Publication Date:
Language:
English
Physical Description:
50 leaves : illustrations ; 28 cm

Subjects

Subjects / Keywords:
Flash memories (Computers) ( lcsh )
Flash memories (Computers) ( fast )
Genre:
bibliography ( marcgt )
theses ( marcgt )
non-fiction ( marcgt )

Notes

Bibliography:
Includes bibliographical references (leaves 47-50).
General Note:
Department of Electrical Engineering
Statement of Responsibility:
by Dmitri Nevedrov.

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Source Institution:
|University of Colorado Denver
Holding Location:
|Auraria Library
Rights Management:
All applicable rights reserved by the source institution and holding location.
Resource Identifier:
55644335 ( OCLC )
ocm55644335
Classification:
LD1190.E54 2003m N48 ( lcc )

Full Text
NON-VOLATILE MEMORIES. OPTIMAL DESIGN AND PERFORMANCE
by
Dmitri Nevedrov
B.S., University of Tartu, 1994
M.S., University of Tartu, 1996
Ph.D., University of Tartu, 1999
A thesis submitted to the
University of Colorado at Denver
in partial fulfillment
of the requirements for the degree of
Master of Science
Electrical Engineering
2003
. ,---
I I Al. j


This thesis for the Master of Science
degree by
Dmitri Nevedrov
has been approved
by
Hamid Fardi
Titsa Papantoni
(lMo 3
Date


Nevedrov, Dmitri (Master of Science, Electrical Engineering)
Non-volatile memories. Optimal design and performance
Thesis directed by Professor Hamid Fardi
ABSTRACT
There are many advantages associated with the use of flash memory. Its
solid-state nature provides ruggedness far superior to mechanical rotating
media. A flash memory with multilevel cell reduces the memory per-bit
cost. In multilevel cell operation, the logical flash memory cell achieves
two bits per cell using four possible states, defined by four flash cell
threshold voltage ranges. Not only is multilevel cell memory valuable as a
digital media, but advantages such as direct access to each cell, specific
to NOR-based flash architectures, permit reliable charge placement,
sensing, and storage. The smaller the die size, the lower the cost. Cost
breaks are associated with the multilevel technology approach because,
at two bits-per-cell, the density of the device is doubled without increasing
the die size.
This abstract accurately represents content of the candidates thesis. I
recommend its publication.
Signed
m


CONTENTS
Figures...................................................v
Tables..................................................vii
1. Introduction..........................................1
2. Overview of Flash Architectures.......................7
2.1 NOR Flash.............................................7
2.2 NAND Flash............................................8
2.3 AND Flash.............................................9
2.4 DINOR Flash..........................................10
2.5 TRIPLE-POLY Flash....................................10
3. Design...............................................17
4. Results and Analysis.................................24
4.1 MOS Devices..........................................29
5. FRAM.................................................34
5.1 Read Operation.......................................37
5.2 Write Operation......................................38
Appendix
A. Flash Fabrication......................................40
References...............................................47
IV


FIGURES
Figure
1. Samsung (NAND) and Intel (NOR) devices.......................2
2. Schematics of floating gate and thin-film storage-based embedded
nonvolatile memory bitcells..................................3
3. Level to data mapping for standard and multilevel technology.11
4. NOR multilevel flash memory with direct cell connections.....12
5. NOR memory during programming................................14
6. Multilevel memory Erase, Read and Program thresholds.........15
7. Charge pump.................................................17
8. Charge pump layout..........................................18
9. Charge pump output......................................... 19
10. Differential amplifier schematics.........................20
11. Differential amplifier layout.............................21
12. EEPROM layout..............................................22
13. Comparison between the different types of Flash programming.23
14. EEPROM MOS characteristics. ldvs.Vd...................24
15. EEPROM MOS characteristics. Threshold voltage..............25
16. /dand voltage Vss,Vdd,Vg...................................26
17. Id and voltage Vss, Vdd, Vg...............................27
18. MOSFET cross section........................................28
19. Id and voltage Vss,Vdd,Vg..................................29


20. Id and voltage Vss, Vdd, Vg...................................30
21. Id and voltage Vss,Vdd,Vg.....................................31
22. Id and voltage Vss, Vdd, Vg...................................33
23. Perovskite unit cell..........................................34
24. Polarization hysteresis loop of a ferroelectric capacitor.....35
25. FRAM cell layout..............................................36
26. Polarization before and after applying electrical field.......39
27. Residual charge remains even without applying voltage.........39
VI


TABLES
Table
1. Ig temperature dependence
26
Vll


1. INTRODUCTION
By using a single transistor memory cell, the flash memories are currently
nearly as dense as DRAMs and potentially more dense. The development
of flash memories is lagging behind the development of DRAMs because
of the need for high internal voltages for writing and erasing, but new
approaches (such as multi-level flash memories) are being used which
may provide flash memory densities close to those available with
DRAMS. Flash memories are beginning to be widely used in the
commercial market where they are showing up in applications such as
solid state disks. Flash memories do have a limited life of about 104 to 106
erase and write operations but this is sufficient for many applications.
However, the time required to read (70 nsec.) is close to DRAMs.
Initially, flash memories have been based on NOR architecture, exhibiting
fast random access, ideal for code storage applications. Multilevel flash
memory stores multiple bits in each cell by placing different levels of
charge on the cells floating gate so that the corresponding threshold
voltage signifies a digital code. Although there is no theoretical limit to the
number of bits that can be stored per cell, noise immunity decreases
significantly as storage density per cell increases. Practical limits on flash
storage density include programming and reading precision. MirrorFlash
architecture is a breakthrough in flash memory cell architecture that offers
a low-cost, high-density memory solution. This architecture doubles the
storage capacity of a flash memory device without compromising its
endurance, performance or reliability. MirrorFlash memory cells, which
store a full charge in each two physically distinct locations, offer many
-l -


advantages over multilevel cell (MLC) technology, which stores fractional
levels of charge in one location. This architecture also overcomes the
inherent reliability issues, slow random access, and long programming
times of MLC technology. The MirrorFlash devices enable one memory
cell to hold two virtual transistors. Each of these transistors can be read
or programmed independently.
Samsung NAND Device
Rl
Open
\
N J
V. N
P-well
N-sub
Vpp (=20V) Vpp(~10V)
(a) Erase mode (F-N tunneling to body)
? Vpp(=20V)
XI l~ 1
n yA A ^ n

P-well
N-sub
(b) Write mode (F-N tunneling to body)
£1
Vpp(=12V) I-
nW
I Source (n +W
) r-substrate
Intel NOR Device
, Vpp (s12V)
(a) Erase mode (F-N tunneling)
(b) Programming mode (hot electrons)
Figure 1. Samsung (NAND) and Intel (NOR) devices.
The diagram entitled NAND and NOR Architecture contrasts the basic
cell structure of both the Samsung NAND and the Intel NOR flash
memories. The cell structure is very similar to a MOS transistor except
for the floating gate. By adding or removing charge on this floating gate
2


one can turn on or off the transistor. A positive charge on the floating
gate relative to the source turns on the device and a negative charge
turns it off. Because the floating gate is electrically isolated, it retains its
charge indefinitely and hence the cells non-volatility.
Floating Sate
Polysiicon Charge
Storage Medium
(Conductor)
ONO
trrterpoy
electric
cS
Substrate
Floating Gate
Nitaae Charge
Storage Meoum
(insulator)
ssicort NanocrysteJ
Charge Starve Medium
(isolated conductors)
SONOS Nanocrystal
Figure 2. Schematics of floating gate and thin-film storage-based
embedded nonvolatile memory bitcells. Depending on the charge stored
inside the gate dielectric of a MOS field-effect transistor, the threshold
voltage can be very high (off state) or so low that a read voltage applied
to the polysilicon gate can turn on the transistor (on state).
(Source: Motorola Inc.)
3


For both the Intel and Samsung devices, erasing is done by the
mechanism of Fowler-Nordheim tunneling. For both device types, the
control gate is grounded. In the case of the Samsung device,
programming voltage is applied to the substrate, but for the Intel device,
programming voltage is applied to the source. The electric field generated
causes electrons to tunnel away from the floating gate making it more
positive and turning the transistor on.
Samsung devices also use a form of tunneling for writing of individual
floating gates. For writing, the P-well and the A/-Substrate are grounded
and programming voltage is applied to the control gate. The voltage on
the control gate is capacitively coupled to the floating gate, which creates
.an electric field that causes electrons to tunnel from the P-well to the
floating gate making it more negative turning off the transistor.
For Intel devices, Channel Hot Electron injection is used to program
individual transistors. For this approach the source is grounded; the
control gate has programming voltage (Vpp) applied to it while the drain
gets approximately half of the programming voltage applied to it. The
voltage on the control gate is capacitively coupled to the floating gate.
This turns the transistor on and causes the current (electrons) to flow
from the source to drain. Some of these electrons will have sufficient
energy (~3.1eV) to pass through the oxide charging the floating gate.
Electrons deposited on the floating gate charge the gate negatively and
turn off the transistor.
Flash technology continues to evolve at a rapid pace. Foremost among
the changes is the rapid shrinkage of minimum feature size, or design
4


rules. This scaling will continue to allow prices to drop (as chip sizes
decrease) and for densities to increase. In order to maintain constant
electric field inside the chip, the nominal operating voltages will also have
to decrease. This decrease in internal voltage may be hidden from the
system designer because of on-chip voltage translators, but internally, the
device will operate at a lower voltage. Many systems will actually benefit
from the decreased supply voltage requirements, especially battery
operated devices such as digital cellular phones and pagers. In nearly all
memory devices: DRAMs, SRAMs, MROMs, EEPROMs, and flash, each
memory cell typically stores one bit Of information, a 1 or 0. For example,
in a 16 Mbit flash, the memory array is composed of 16 million transistors.
In these devices, a single threshold level separates the 0 state from the
1 state. In flash memory, these two states are differentiated by the
amount of charge on the floating gate of a memory cell transistor. If one
could accurately control the amount of charge such that 4 charge states
were distinguishable, then 2 bits of information could be stored in a single
transistor; thereby halving the number of memory transistors required. If 8
states are distinguishable, then 3 bits of information can be stored per
memory cell transistor.
Several manufacturers have introduced multilevel cell devices. MLC
technology promises a significantly reduced cost per bit, but, ultimately
chip cost is related to die yield and die area. Because the die area
consists of peripheral circuitry, control circuitry, and memory array area,
halving the memory array using a 2 bit MLC design will not halve the die
area. For applications that are very sensitive to cost per bit, MLC flash
may be the most cost effective approach. However, there are tradeoffs.
Data shows that MLC designs have 3-4 times longer programming times
and lower write/erase cycle endurance. Although the block erase times
5


and read times are expected to be comparable to single bit per cell flash,
the longer programming times and reduced lifetime mat take MLC flash
less desirable for solid state disk drives than standard single bit per cell
flash.
As flash technology matures, the development of specialized flash
devices optimized for specific functionality was inevitable. While NAND
flash is optimized for use as a solid state drive, improvements in NOR
flash are on a horizon. The read-while-write NOR flash devices are
essentially two or more memory arrays on a die. This enables the user to
read from one array while programming or erasing the other array. The
next development in NOR flash will likely address the need for increased
performance. Random access speeds will continue to decrease as
lithography decreases, but the falling supply voltage could work against
this. The next evolutionary step is likely to be the emergence of
synchronous flash devices.
6


2. Overview of Flash architectures
2.1 NOR Flash
Within NOR flash, any byte is randomly accessible from a read and write
perspective (with the exception that a byte cannot be rewritten unless its
associated block is erased). This aspect of NOR flash suits it particularly
well for code storage and execute-in-place applications, which require
high-speed random access. Access times range from 65 to 170 nsec.
Intel's 28F016XS, a synchronous flash memory with a three-stage
pipeline, broke the speed record with access times to 30 nsec. This move
translates to zero-wait-state performance at 33 MHz, with burst lengths
up to the full 2 Mbytes.
Traditionally, NOR flash has been associated with large, 64-kbyte erase
blocks and long erase times of 1 to 2 sec. Although the large block size
minimizes the erase granularity, it also minimizes the overhead control
circuitry needed to access the array; this, in turn, minimizes the die size,
which allows a lower cost structure. Hitachi's HN28- F1600 16-Mbit
device, with 512-byte sectors (or blocks), breaks the mold on erase sector
size and erase time for NOR flash. Each 512-byte sector in the
HN28F1600 erases in 10 msec, but the sectors can be configured into
larger block sizes of up to 32 contiguous sectors and erased in 15 msec.
Compared with RAM, NOR-flash write time is several orders of magnitude
slower, typically 7 to 10 psec/byte. Intel's 16-Mbit flash devices have two
7


integrated 256-byte RAM buffers for increasing the burst-write-transfer
rate. Once data is in the buffers, the system gives the flash device the
command to transfer the data into the flash array at a rate of 3 psec/byte,
approximately twice as fast as writing 1 byte at a time. Similar to Intel's
16-Mbit flash, Hitachi's HN28F1600 writes 1 byte at a time, but the device
also has an 8-byte page for increased write performance. Specifically, the
Hitachi flash typically writes 1 byte in 10 psec or an 8-byte page in 20
psec.
2.2 NAND Flash
NAND flash is structured such that the system reads or writes on a page
basis, where a page equals 264 bytes of SRAM (256 plus 8 bytes for
error correction). The 32-Mbit device has a 528-byte page (512 plus 16
bytes for error correction). The system accesses data sequentially within
those pages. NAND flash's system interface consists of I/O pins for both
address and data input and output as well as command inputs. After the
system provides a command to read data from the device, internal
circuitry transfers data from the flash array into the page. Once the data is
in the page, it streams out of the device at an 80-nsec/byte rate.
However, the initial loading of the page takes approximately 25 psec,
which wreaks havoc on NAND flash's random read access. NAND flash is
not optimized for code storage or execute-in-place applications.
Similar to the RAM buffers on Intel's 16-Mbit device, the NAND flash's
page allows the system to perform burst writes to the device. Note that
after the 264- or 528-byte page fills, NAND flash may require up to 5
msec to transfer the page's contents into the flash array.
8


NAND flash has small erase blocks and fast erase times. The 16- and 32-
Mbit devices have a maximum of 512 erase blocks of 4 and 8 kbytes,
respectively. NAND-flash manufacturers ship perfect and imperfect
devices, each with a different price structure. Perfect devices have 100%
functional blocks; imperfect devices have up to 2% bad blocks, which
increases yields. After the manufacturer tests the flash device, 00H is
programmed somewhere within the bad blocks. After installing these
devices, system software identifies (and maps) the bad blocks by
scanning for 00H. This process is analogous to bad sectors on a disk
drive.
The erase time (and current consumption) on NAND devices does not
vary considerably between a single block and an entire chip erase. A
single block erases in a maximum of 100 msec (6 msec is typical);
simultaneous, multiblock erases (up to the entire chip) take a maximum of
130 msec. Compare this with the maximum chip-erase time of 19 sec (1
sec typ) that 16-Mbit NOR devices requirethey must erase all blocks
sequentially (with the exception of Hitachi's HN28F1600).
2.3 AND Flash
The AND flash, primarily driven by Hitachi, is a new cell structure that
incorporates characteristics of NAND and NOR architectures. The first
commercially available AND device contains a 32-Mbit flash array. Some
of the AND flash characteristics include 512-byte erase blocks and
random- and sequential-access modes. In random mode, you can access
data in 120 nsec. Sequential mode has a 1-psec hit for the first access
9


while a page buffer fills, but then subsequent accesses can stream at 50
nsec/byte.
2.4 DINOR Flash
The basic cell structure of DINOR flash looks much like a NOR flash cell.
The major differences between the two architectures are in the erase and
write methods, as well as the cell arrangement. In short, NOR flash uses
a main metal line, and DINOR flash has a polysilicon sub-bit line to
reduce contact area, ultimately reducing the die size by 25% and allowing
faster access. As with other flash devices, the DINOR device includes a
256-byte buffer to increase burst-write performance. The DINOR flash
also allows low-current write and erase, which makes it practical to
integrate an on-chip charge pump to generate internal high voltages from
3.3 V.
2.5 TRIPLE-POLY Flash
The triple-poly architecture, used by Sundisk, produces a die with a very
dense array. The Sundisk flash device writes 32 bytes in parallel (10
psec) because the flash cells program in relatively low channel currents.
Erase sector size is 512 bytes, in addition to 10% overhead for memory
management and error checking and correction. Typical erase time is 1
msec, and a sector-tagging feature allows multiple sectors to erase in
parallel. Sundisk is unusual in that it builds flash devices solely for its own
use in its ATA drives. Because Sundisk's flash devices are buried within
10


an ATA drive, designers can relocate repetitive on-chip circuitry on a
single off-chip controller, reducing die size further. To increase yields,
Sundisk uses devices with known defects, but the ATA drive's internal
logic maps out the bad blocks.
Flash Manufacturers:
NOR: Intel, AMD, Macronix, Atmel, Sandisk
NAND: Toshiba, Samsung, Fujitsu
AND/DINOR: Hitachi, Mitsubishi
In the Flash memory market of today, prices are decreasing. In addition to
process improvements, there are important distinctions to know when
buying multilevel 2-bit-per-cell and 1-bit-per-cell technology. Typical flash
Standa-d ETOX
Technology Cells
V,
1 0 L Lave 11
1 Level D
Intel StrataFlash
Memory Technology
V,
i L
D. Levels
0. 1 Level 2
1.0 Level 1
1. 1 Level
Intel StrataFlash
Me mo ry Techn ol og y
V,
0.0.0 L Level 7
0,0.1 LevelB
0,1,0 Levels
0,1.1 Level 4
1.0,0 Level 3
1.0.1 Level 2
1.1,0 Level 1
1.1.1 Level 0
M (b) W
Figure 3. Level to data mapping for standard and multilevel technology.
memory uses a single bit-per-cell. Each cell is characterized by a specific
threshold voltage Vth level. Electrical charge is stored on the floating gate
11


of each cell. Within each cell, or transistor, two possible voltage levels
exist (Figure 3). These two levels are controlled by the amount of charge
that is programmed or stored on the floating gate. If the amount of charge
on the floating gate is above a certain reference level, the cell is
considered to be in a different level.
rectiy-Ccnnscted Cell Layout
[NQR Architecture)
Flash Memery Cell
[NOR Architecture)
BL
Bit Lines (BL)
BL
r3
.nn-^'nih1 jnii-f
SL
'znpr
ZHII-1 falh1
BL

imi-T
SL
Source Lines (SL)
SL
-WL
-WL
WL
NO -
Tunnel Oxide ^

Source
n+
- WL Word Lines QAfL)..
Control Gate
(Wordline)
poly-2
(-)(-) poly-1
P Substrate
Bitline
metal-1
M
90
Figure 4. NOR multilevel flash memory with direct cell connections.
Todays memory products are capable of storing two bits per memory cell
(Figure 3, b). The multilevel technology path illustrates that NOR-based
multilevel cell technology is easily scaleable to three bits-per-cell which
enables another significant increase in density per area.
In multilevel technology, the voltage across each cell has been divided
into greater than two levels. Figure 3 illustrates Vth level placement for
two and three bit-per-cell technology.
Due to the inherent complexity, multilevel program and read times are
slower than 1-bit-per-cell devices. Voltage range restrictions in multilevel
devices require them to have higher currents to drive the cells to those
voltage ranges. In most cases the die for a multilevel device is not half the
12


size of a die for a single bit per cell device. Multilevel technology is
typically one or two lithography processes behind. Single-bit-per-cell
technology. If a multilevel device is manufactured under a 0.25 mm
process, a single-level device is likely being manufactured at a 0.18 mm
process. This can bring higher yields at lower costs.
The actual memory saving in a multilevel device becomes only about 20-
25%. The cells have to be programmed to adhere to a stricter voltage
level. This requires more complex interface circuitry, which then requires
more space, this further reduces the difference in area. It also takes
longer to program multilevel devices, which causes a loss of time and
revenue. Multilevel flash memories attract a great deal of attention
because they significantly reduce the cost per bit. The memory cell
density can be doubled without a die size increase if the four levels of
data can be stored in one memory cell. One of the requirements is the
precise control of the programmed threshold voltage Vth.
Multilevel cell devices must be able to manage electrical charge precisely.
More specifically, these devices must be able to place charge with
precision, sense charge with precision, and store charge overtime. These
requirements are met by the NOR architectures direct connection to the
gate, source, and drain of each memory cell. Each cell is made up of a
single transistor which is directly connected to the appropriate control
voltages in order to accomplish pinpoint accuracy in charge manipulation.
During programming, a precise charge must be placed onto the floating
gate. The analog voltage that exists across each flash cell is divided into
multiple Vth levels which are controlled by the amount of electrons on the
floating gate
13


During programming, each cells direct ground, bit line, and word line
connection enables precise charge placement. A cells control gate links
to the internally generated supply voltage through a direct word line
connection and row decoding. The drain is pulsed at a constant voltage
through a direct bit line connection and column decoding. The source is
directly connected to ground (Figure 5, a).
Directly-Connected Cell Layout
(NOR Architecture)
Intel Strata FI ash Memory Cell
during Programming
BL
,=11^
iii-r
Bit L E ines (BL) )L 3L
=nP~ =nP
J =II|J mi-1
J =111-1 zni-l
J 5ifi . 5ihJ
SL SL SL
Source Lines (SL)
+Vg
Control Gate
W)
£b)
Figure 5. NOR memory during programming.
Electron storage on the floating gate creates a potential that must be
overcome by the control gate. This potential results in a higher turn-on
threshold voltage. Direct, precise gate and drain control is critical to
multilevel memory cell placement.
The voltage across each cell has been divided into multiple levels. Figure
6 illustrates cell distribution over individual voltage levels, along with the
placement reference points (P1, P2, and P3) for two bit-per-cell
technology. D uring p rogramming, a s pecific v oltage r ange is u sed to
14


represent one of the specific levels. Programming data at a given memory
address transitions selected cells from the 11" (erased) level to the "10",
"01, or "00" (programmed) levels. Storing two bits-per-cell requires four
levels defined by read reference cells; R1, R2, and R3. These voltage
levels are defined by the threshold voltage of the read reference cells as
follows: Vth < Vth (R1) is level 0, Vth (R1) < Vth < Vth (R2) is level 1, Vth
(R2) < Vth < Vth (R3) is level 2, and Vth > Vth (R3) is level 3. Specific,
unique voltage values define each level.
IS
Level 0 ; Level 1 ; Level 2 Level 3
Data 11 Data 10 Data 01 Data 00
ZA /A
I t I M It
V,
(Flash Cell
Threshold Voltage
EV
R1
P1
R2 P2
R3 P3
Figure 6. Multilevel memory Erase, Read and Program thresholds.
During data read, charge sensing is of maximum importance. Through
direct connections to each memory cell, the data read operation
determines the level of each memory cell quickly, accurately, and reliably.
The data read operation senses which of the four levels the memory cell
falls within based on the threshold voltages of the three read reference
cells. The reference cells are biased in such a way that each conducts a
current proportional to the Vth of its specific level. During the read
operation; is placed on the control gate, the source is grounded, and
15


a drain bias is applied. In this mode, a cell conducts a current which is
proportional to the cells Vth.
16


3. Design
When the cells are biased in this way, the current conducted through
each cell has an inverse relationship to its Vth- Therefore, if current
through the flash array cell is greater than the appropriate reference
current then the memory cell Vth is less then the reference cell V#,. The
data is read by comparing the current through the memory cell to the
current through three read reference cells.
The bit line current for the memory cell is compared to the current
produced by three read reference circuits. T he c urrent is s ensed by
connecting the drain to an active load, which is connected to a differential
17


sense amplifier. For a read operation, there is a sense amplifier for each
of the three read reference cells. Each sense amplifier has a flash array
input, from the bit line, and a reference cell input.
10 fcanbda
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Figure 8. Charge pump layout.
18


Figure 9. Charge pump output.
19


VPius
P2
N2
Voul

7777
Figure 10. Differential amplifier schematics.
20


Figure 11. Differential amplifier layout.
21


Figure 12. EEPROM layout.
22


Electron Trapping
Electron Removal
Vcg
Bi-polarity FN-t
Write I Erase
technology
4-t-t
Doa
#
Fowler-Nordheim tunneling
Hot-Electron
injection and FN-t
technology
^1
z^DC l -

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Vcg
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hfcZE-i

Vsub
Fowler-Nordheim tunneling
Hot-Electron Injection
Figure 13. Comparison between the different types of Flash programming
(source ICE Memory 1996).
23


4. Results and Analysis
The multilevel flash memory was designed using Microwind. We
performed simulations for two different temperature values and with
different voltages. Figures 14 and 15 demonstrate current and voltage
characteristics of EEPROM.
24


25


(VOID
r 151 tse2


Vdd=5.0S.DC


1.0C
ov
Figure 16. /dand voltage Vss, Vdd, Vg.
Pulse 1, V Pulse 2, V s/dd, v VSS,V Ig, mA Temperature, F
5.0-10.0 o CD I o 5.0 0.0 46.498 323
5.0-9.5 1.0-6.0 5.0 0.0 42.159 323
5..0-9.0 1.0-6.0 5.0 0.0 55.195 323
5.0-10.0 0 1 o> o 5.0 0.0 31.339 300
5.0-9.5 b I o> o 5.0 0.0 33.978 300
5..0-9.0 o CD I o 5.0 0.0 49.164 300
Table 1. Ig temperature dependence.
26


The simulations were performed with Microwind. Figures 16-22 illustrate
the results of simulations.
The structure has two 0.5 pm-long floating gates mutually isolated by a
50nm spacing. In order to analyze the basic characteristics of the device,
typical values for cell parameters and standard doping profiles have been
considered. The channel width is 0.7 urn; the equivalent thickness of the
second level oxide is 20 nm, and the first level oxide in 10 nm thick. The
source and drain junction depth is 0.35 pm.
(A) !S: ii: iddmatf-0 DOQmA IddAvic.OGOrnA
Kid : red l(N6 4 x2>=42.159mA


r





\
10.0 8.00 6.00 r* ~""" PL P' !i2 : fsel


Vdd=5.0SDC
4.00
2.00
1.QC
0.DQ
-2.0 0.0".......0.5'.. 1.0...............1.5.........2.0.........2.5..........3.0" .......3.5..........4.0~........4.5...Timers;
Figure 17. /dand voltage Vss, Vdd, Vg.
27


Figure 18. MOSFET cross section.
28


10
10':
10"
10"1
10"1
10"
10-1
10"!
10"
w iddm?Jc=0.u0DmA iddAvio ODOrnA
ids iri rat! l(NB 4 X2)=55.195mA

^^
!





ft/oit)

p: ou Ise1 1

VddsS.Qs.Q0

1.00
ov
4.5 Time(ns)
Figure 19. /dand voltage Vss, Vdd, Vg
Double oxide 0.0050 pm, thin oxide 0.0020 pm, N-well 1.00 jam, diff-
n 0.40 (am, diff-p 0.40 pm, contact -1.10 pm, poly 2 0.20 pm, poly -
0.20 pm, metal 0.40 pm, metal 2 0.40 pm, via 0.50 pm, metal 3 0.40
pm, via 2 0.50 pm, metal 4 0.40 pm, via 3 0.50 pm, metal 5 0.80
pm, via 4 0.50 pm, metal 6 0.80 pm, via 5 0.50 pm.
4.1 WSOS devices
MN1 7 28 19 0 N1 W= 0.24U L= 0.12U
MN2 6 22 19 0 N1 w= 0.24U L= 0.12U
MN3 6 27 19 0 N1 w= 0.24U L= 0.12U
MN4 5 23 19 0 N1 w= 0.24U L= 0.12U
MN5 5 30 19 0 N1 w= 0.24U L= 0.12U
MN6 1 20 19 0 N1 w= 0.24U L= 0.12U
29


MN7 1 29 19 0 N1 W= 0.24U L= 0.12U
MN8 1 21 19 0 N1 W= 0.24U L= 0.12U
MN9 7 28 18 0 N1 W= 0.24U L= 0.12U
MN10 6 22 18 0 N1 W= 0.24U L= 0.12U
MN11 6 27 18 0 N1 W= 0.24U L= 0.12U
Figure 20. Id and voltage Vss, Vdd, Vg.
MN12 5 23 18 0 N1 W= 0.24U L= 0.12U
MN13 5 30 18 0 N1 W= 0.24U L= 0.12U
MN14 1 20 18 0 N1 W= 0.24U L= 0.12U
MN15 1 29 18 0 N1 w= 0.24U L= 0.12U
MN16 1 21 18 0 N1 w= 0.24U L= 0.12U
MN17 0 25 16 0 N1 w= 0.24U L= 0.12U
MN18 7 28 15 0 Nl w= 0.24U L= 0.12U
MN19 6 22 15 0 N1 w= 0.24U L= 0.12U
MN2 0 6 27 15 0 Nl w= 0.24U L= 0.12U
MN21 5 23 15 0 Nl w= 0.24U L= 0.12U
MN22 5 30 15 0 Nl w= 0.24U L= 0.12U
30


MN23 1 20 15 0 N1 W= 0.24U L= 0.12U
MN24 1 29 15 0 N1 W= 0.24U L= 0.12U
MN25 1 21 15 0 N1 W= 0.24U L= 0.12U
MN26 7 28 14 0 N1 W= 0.24U L= 0.12U
MN27 6 22 14 0 N1 W= 0.24U L= 0.12U
MN28 6 27 14 0 N1 W= 0.24U L= 0.12U
MN29 5 23 14 0 N1 W= 0.24U L= 0.12U
MN30 5 30 14 0 N1 W= 0.24U L= 0.12U
MN31 1 20 14 0 N1 W= 0.24U L= 0.12U
MN32 1 29 14 0 N1 W= 0.24U L= 0.12U
MN33 1 21 14 0 N1 W= 0.24U L= 0.12U
MN34 13 : 24 11 0 N1 W= 0.24U L= 0.12U
MN35 12 : 26 11 0 Nl W= 0.24U L= 0.12U
10"1 1D'2 10-3 ID4 ID5 !D-6 ID7 1D-0 IQ9 CA) i-ss in a????! iildmsn-tUlOOmA iddA^O.iiaOirA
in reel l(N9 4 x2)=33.978mA


s /





mlS 10.0 8.00 6.00 4.00 2.00 Q.00 p



PL !sal ~

Vdd=5.05.00
-
~ 1.00
OV
2.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 TimB(ns)
Figure 21. Id and voltage Vss, Vdd, Vg.
MN36 MN37 7 28 6 22 10 10 0 Nl W= 0.24U L= 0.12U 0 Nl W= 0.24U L= 0.12U
31


MN38 6 27 10 0 N1 W= = 0.24U L= = 0.12U
MN39 5 23 10 0 N1 W= = 0.24U L= = 0.12U
MN4 0 5 30 10 0 N1 W= = 0.24U L= = 0.12U
MN41 1 20 10 0 N1 W= = 0.24U L= = 0.12U
MN42 1 29 10 0 N1 W= = 0.24U L= = 0.12U
MN4 3 1 21 10 0 N1 W= = 0.24U L= = 0.12U
MN4 4 7 28 9 0 N1 W= 0.24U L= 0.12U
MN45 6 22 9 0 N1 W= 0.24U L= 0.12U
MN4 6 6 27 9 0 N1 W= 0.24U L= 0.12U
MN47 5 23 9 0 N1 w= 0.24U L= 0.12U
MN48 5 30 9 0 N1 w= 0.24U L= 0.12U
MN49 1 20 9 0 N1 w= 0.24U L= 0.12U
MN50 1 29 9 0 N1 w= 0.24U L= 0.12U
MN51 1 21 9 0 N1 w= 0.24U L= 0.12U
MN52 7 28 8 0 N1 w= 0.24U L= 0.12U
MN53 6 22 8 0 Nl w= 0.24U L= 0.12U
MN54 6 27 8 0 N1 w= 0.24U L= 0.12U
MN55 5 23 8 0 Nl w= 0.24U L= 0.12U
MN56 5 30 8 0 Nl w= 0.24U L= 0.12U
MN57 1 20 8 0 Nl w= 0.24U L= 0.12U
MN58 1 29 8 0 Nl w= 0.24U L= 0.120
MN59 1 21 8 0 Nl w= 0.24U L= 0.12U
MN60 7 28 0 0 Nl w= 0.24U L= 0.12U
MN61 6 22 0 0 Nl w= 0.24U L= 0.12U
MN62 6 27 0 0 Nl w= 0.24U L= 0.12U
32


w in green iC:dniax=O.UllumA WdAwflLGOOmA
ids In rc'd ICNB4 x2)=49.164mA







Oj
10.0 (Volt)
e.oo PL !se2
PL isei
6.00
Vdds5.Os.oo
4.00
2.00
1.00
0.00 DV
-2.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Tlme(ns)
Figure 22. Id and voltage Vss, Vdd, Vg.
MN63 5 23 0 0 N1 W= 0.24U L= 0.12U
MN64 5 30 0 0 N1 W= 0.24U L= 0.12U
MN65 1 20 0 0 Nl W= 0.24U L= 0.12U
MN66 1 29 0 0 Nl W= 0.24U L= 0.12U
MN67 1 21 0 0- Nl W= 0.24U L= 0.12U
C3. 1 0: 0.729fF . C16 16 0 0.068fF .MODEL Nl NMOS LEVEL=3
C4 1 0 1.169fF C18 18 0 0.573fF VTO=0.40 00=0.060 TOX=
C5 5 ,0' 1.169fF C19 19 0 0.573fF 2.0E-9
C6 6 0 1. l'69f F . C20 20 0 0.184fF +LD =0.000U THETA=0.500
Cl 7 0 0.729fF C21 21 0 0.184fF GAMMA=0.400
C8 8 0 0.573fF C22 22 0 0.184fF +PHI=0.200 KAPPA=0.060
C9 9 0 0.573fF C23 23 0 0.184fF VMAX=120.00K
CIO 10 0 0.573fF C24 24 0 0.023fF +CGSO=l00.Op CGDO=l00.Op
Cll 11 0 0.143fF C25 25 0 0.023fF +CGBO= 60.Op CJSW=240.Op
C12 12. 0 0.091fF C26 26 0 0.023fF
C13 13 0 0.091fF C27 27 0 0.184fF
C14 14 0 0.573fF C28 28 0 0.184fF
15 15 0 0.573fF C29 29 0 0.184fF
C30 30 0 0.184fF
33


5. FRAM
FRAM is a RAM-based device that uses the ferroelectric effect for a
storage mechanism. This is a completely different mechanism than the
one used by other nonvolatile memories, which use floating gate
technology. The ferroelectric effect is the ability of a material to store an e
lectric polarization in the absence of an applied electric field.
Figure 23. Perovskite unit cell.
34


A FRAM m emory c ell is c reated by dep ositing a f ilm o f f erroelectric
material in crystalline form between two electrode plates to form a
capacitor. This capacitor construction is very similar to that of a DRAM
capacitor. Rather than storing data as charge on a capacitor like a DRAM,
a ferroelectric memory stores data within a crystalline structure. Due to its
basic RAM
Figure 24. Polarization hysteresis loop of a ferroelectric capacitor.
design, the circuit reads and writes simply and easily. However unlike a
DRAM, the data state is stable. Therefore the FRAM memory needs no
periodic refresh and when power fails, the FRAM retains its data. Current
35


Figure 25. FRAM cell layout.
FRAM products use a two-transistor, two-capacitor memory cell. This cell,
which provides each data bit with its own reference, is a well-proven
scheme. A simplified model of a ferroelectric crystal is shown in Figure
36


23. It has a mobile ion in the center of the crystal, and applying an electric
field across the face of the crystal causes this ion to move in the direction
of the field. A reversal of the field causes the ion to move in the opposite
direction. The ion position at the top and bottom of the crystal are stable,
and the ion remains in these states when the external field is removed.
Since no external electric field or current is required for the ferroelectric
material to remain polarized in either state, a
memory device can be built for storing digital (binary) data that will not
require power to retain information stored within it. Typical perovskite
ferrolelectric materials are BaTi03, PbTi03, PZT(PbZri_xTix03), PLZT(Pbi.
xl_xZr03), PMN(PbMg-|.xNbx03), SBT(SrBi2Ta209), SBN(SrBi2Nb209).
5.1 Read Operation
Although the memory element is a capacitor, it does not store data as
linear charge. In order to read a FRAM memory cell, it is necessary to
detect the position of the atoms within the Perovskite crystals.
Unfortunately, they cannot be directly sensed. The read process works as
follows. An electric field is applied across the capacitor. The mobile atoms
will move across the crystals in the direction of the field if they are not
already in the appropriate positions. In the middle of the crystal, a high-
energy state holds the atoms in place when no field is present. As the
atoms move through this high-energy state, a charge spike is emitted.
The circuit dumps charge resulting from the applied field from the
capacitor and compares it to the charge from a reference. A capacitor
with atoms that switch states will emit a larger charge than a capacitor
with atoms that do not switch. The non-switching capacitor will emit the
37


ordinary DRAM charge while the switching capacitor will emit the
combination of the DRAM and ferroelectric charges. The memory circuit
must determine which capacitor switched. This switched charge allows
the circuit to determine the state of a memory cell. The state switch
occurs in under 1 ns, with the complete circuit access taking less than 70
ns. Since a memory read operation involves a change of state, the circuit
automatically restores the memory state. Therefore each read access is
accompanied by a precharge operation that restores the memory state.
Although the read is destructive, the time during which the memory cell is
invalid is under 50 ns.
5.2 Write Operation
A write-operation is very similar to a read operation. Unlike other
nonvolatile memory technologies, a write-operation is very simple and
requires no system overhead. The circuit applies write data to the
ferroelectric capacitors. If necessary, the new data simply switches the
state of the ferroelectric crystals. As with a read, the change of state
occurs in under 1 ns with a full access taking under 70 ns. As with a read,
a precharge operation follows a write access
38


Figure 26. Polarization before and after applying electrical field.
1Q'1 10'2 10-3 10-4 10-S 10-6 10'7 1O-0 10-3 0-J.S w









......

8.00 6.00 4.00 2.00 0.00 (VOID



Vddh=2.50 Vdd=1
! I
ov
-2.0 0.0........2.0...........4.0 .........6.0 ...8.0.......""..10.0.........12.0.........14.0"........ 16.0...... ..19.D'time(ns)
Figure 27. Residual charge remains even without applying voltage.
39


Appendix
A. Flash Fabrication
In the following figures, some of the important process steps involved in
the fabrication of a flash memory are shown.
1. Initial P-substrate with A/-diffusion. An initial oxide layer is grown on
the entire surface. The first lithographic mask defines the n-well
region. Donor atoms, usually phosphorus, are implanted through
this window in the oxide.
40


2. Si02 trench isolation
3. Thin oxide layer growth on entire surface. The thickness and the
quality of the gate oxide are two of the most critical fabrication
parameters, since they strongly affect the operational
characteristics of the MOS transistor, as well as its long-term
reliability
41


4. Thin oxide reduction
5. Polysilicon deposition using chemical vapor deposition and
patterned by dry plasma etching. The created polysilicon lines will
function as the gate electrodes of the transistors and their
interconnects. Also, the polysilicon gates act as self-aligned masks
for the source and drain implantations that follow this step.
42


6. Ar implant. Using a set of two masks, the n+ regions are implanted
into the substrate and into the. Also, the ohmic contacts to the
substrate and to the n-well are implanted in this process step
7. Second polysilicon deposition. An insulating silicon dioxide layer is
deposited over the entire wafer using chemical vapor deposition.
The contacts are defined and etched away to expose the silicon or
polysilicon contact windows. They are necessary to complete the t
interconnections using the metal layer, patterned in the next step
43


8. Create contacts
9. Metal deposit and etachment. Metal (aluminum) is deposited over
the entire chip surface using metal evaporation, and the metal lines
are patterned through etching.
44


10. Via hole and fill


12. Passivation etching. End of process.
46


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50