REALIZATION OF AN AC LINK, PULSE WIDTH MODULATED SHUNT
CONVERTER FOR STATCOM APPLICATIONS
by
Osama, M A1 Gali
BSc, Garyounis University, 2005
A thesis submitted to the
University of Colorado Denver
in partial fulfillment
of the requirements for the degree of
Master of Science
Electrical Engineering
2011
This thesis for the Master of Science
degree by
Osama, M A1 Gali
has been approved
by
Jan Bialasiewicz
Titsa Papantoni
Date
A1 Gali, Osama, M (M.S., Electrical Engineering)
Realization of an AC Link, Pulse Width Modulated Shunt Converter for STAT
COM Applications
Thesis directed by Assistant Professor Fernando MancillaDavid
ABSTRACT
This thesis presents the dynamic modeling and the control strategy of the
ACLink based Static Synchronous compensator (STATCOM). The ACbased
STATCOM is realized using an ACLink, ACAC converter and a coupling trans
former. Using the ACAC converter allows using the simple control technique
used in the PWM DCDC converters. An open loop control system and a closed
loop PI controller have been designed, simulated and tested and gave the re
sults desired. Disturbances have been committed at the sending and receiving
end voltages. A step change in the reference voltage has been committed, and
the system was able to respond and compensate for all these disturbances and
showed feasible results. The waveforms of the voltage and current injected into
the system have been tested, and their quality meet the limits in the Standard
IEEE Std 5191992.
This abstract accurately represents the content of the candidates thesis. I
recommend its publication.
DEDICATION
I dedicate this work to the martyrs of Libya who sacrificed their souls for Libya
to be a better place. To the wounded and all the freedom fighters who risked
their lives for Libya to be free.
Also, I dedicate this work to both of my parents, my mother and my late
father, ALLAH bless his soul, who brought me into this great and wonderful
w'orld and raised me to be the person I am today.
ACKNOWLEDGMENT
In the Name of ALLAH, Most Gracious, Most Merciful
Im truly grateful to ALLAH the Almighty, for giving me the strength and pa
tience to complete this work. I would also like to thank ALLAH for giving me
good health throughout the research until the competition of this project.
I would like to express my deepest gratitude to my supervisor, Dr. Fernando
MancillaDavid for his endless support, guidance, wise words, encouragement,
ideas and help throughout the research. This work would not be done without
his support and advice.
I also wish to express my appreciation to my committee members Dr. Jan
Bialasiewicz and Dr.Titsa Papantoni, for their comments and their help.
I would like to thank my parents who spend their lives supporting me, my
brothers and sisters who encourage me, and my best friends who always help
me.
CONTENTS
Figures ................................................................. x
Tables................................................................ xiii
Chapter
1. Introduction........................................................ 1
1.1 Overview ........................................................... 1
1.2 Literature Review................................................... 3
1.3 Outline of the Research ........................................... 6
2. Vector Switching Converter (VeSC)................................... 8
2.1 Introduction........................................................ 8
2.2 Converter Model..................................................... 8
2.3 Averaged Equivalent Circuit........................................ 12
2.4 Pulse Width Modulated (PWM) VeSC Converter....................... 14
3. Static Synchronous Compensator (STATCOM) .......................... 22
3.1 Introduction....................................................... 22
3.2 The Stateoftheart STATCOM....................................... 23
3.3 Proposed STATCOM................................................... 26
3.4 Principle of Operation of STATCOM.................................. 28
3.5 The Voltage at the point of common coupling, Vpcc, Calculations . 30
3.6 Design Considerations of the STATCOM............................... 31
3.6.1 Capacitor Bank Sizing............................................ 31
vii
3.6.2 Filter Design.................................................. 33
4. ACLink VeSC Base STATCOM Control............................... 36
4.1 Introduction.................................................... 36
4.2 Open Loop Control System ....................................... 36
4.3 Feedback Control System ........................................ 39
4.3.1 Dynamic Model of the VeSC based STATCOM........................ 39
4.3.1.1 StateSpace Equations....................................... 40
4.3.2 Proposed Controller............................................ 47
4.3.2.1 Small Signal Model.......................................... 48
4.3.2.2 Loop Gain Shaping using Bode Plots........................ 50
5. Computer Simulation............................................... 54
5.1 Response to a Step Change in the Reference.................... 56
5.2 Response to Disturbances........................................ 57
5.2.1 Response to a Step Change in the Sending End Voltage ........ 58
5.2.2 Response to a Step Change in the Receiving End Voltage....... 58
5.3 Waveform Quality ............................................... 61
5.3.1 THD of the Voltage at the Point of Common Coupling........... 62
6. Conclusion and Future Wbrk........................................ 64
6.1 Conclusion..................................................... 64
6.2 Future Wfork ................................................... 64
Appendix
A. STATE EQUATION CALCULATIONS AND LINEARIZING THE
SYSTEM ........................................................... 66
A.l Calculating A,B,C,D and v Matrices............................... 66
viii
A. 2 Vpcc Calculations ................................ 68
B. SYSTEM, CONVERTER AND CONTROLLER PARAMETERS . 78
C. SIMULINK/MATLAB BLOCKS ............................. 80
D. FAST FOURIER TRANSFORM IN MATLAB ................... 84
References............................................. 85
IX
FIGURES
Figure
1.1 Realizations of STATCOMs/DSTACOMs (a) Stateoftheart (b) Pro
posed Topology.................................................... 3
2.1 Schematic of SinglePole NThrow ThreePhase Vector Switching Con
verter ........................................................... 9
2.2 Averaged equivalent circuit of the primitive switching power converter . 12
2.3 Averaged equivalent circuit of the primitive switching power converter . 13
2.4 IGBTDiode realization for singlepole multiple throw switch .......... 13
2.5 Three Phase single pole double throw PWM VeSC Boost converter . . 15
2.6 Single Phase Boost converter................................. 16
2.7 Pulse Width Modulator Comparator Signals ............................... 17
2.8 Voltage waveforms Vpcc, V0 and VC2........................... 18
2.9 Current waveforms II, Isw, Iq and Ic\ .................................. 19
3.1 VI Characteristics of STATCOM versus SVC.................... 23
3.2 Realizations of STATCOMs/DSTACOMs, Stateoftheart.......... 24
3.3 Schematic diagram of a single phase CascadedTvpe Multilevel Inverter 25
3.4 Output voltage of a single phase CascadedType Multilevel Inverter . . 25
3.5 Realizations of STATCOMs/DSTACOMs, Using AClink............. 26
3.6 AClink based STATCOM........................................ 27
3.7 Switch voltage and output voltage waveforms.................. 27
3.8 Single line diagram of the transmission line system with the STATCOM 29
x
3.9 Single line diagram of the transmission line system without the STAT
COM .................................................................... 30
3.10 Transmission Line System with the Shunt Compensator .................... 32
3.11 Single line diagram of the STATCOM and the power system................. 33
3.12 Voltage and Current Waveforms of the Inductor (Lj) ..................... 34
3.13 Current and Voltage Waveforms of the Capacitor (Cl)..................... 35
4.1 Block diagram of the open loop control system........................... 36
4.2 Transmission Line System with the Shunt Compensator .................... 37
4.3 Millman equivalent circuit ............................................. 37
4.4 Equivalent Circuit of the Converter..................................... 38
4.5 The relation between d and Vpcc ........................................ 38
4.6 Block diagram of closed loop control system ............................ 39
4.7 A schematic of STATCOM equivalent circuit............................... 40
4.8 Single Line Diagram for the System with the Converter................... 41
4.9 Sign convention of voltages and currents across two terminal Resistor,
Inductor and Capacitor................................................ 41
4.10 Block diagram for the control system.................................... 47
4.11 Block diagram for the small signal model................................ 49
4.12 Bode Plot for the partial loop gain Pg(juj) ............................ 51
4.13 Bode Plot for the partial loop gain (/3h(jui)g(jui)) ................... 52
4.14 Bode Plot for the loop gain (T(juj) =/3h(juj)g(juj)) ................... 53
5.1 Single line diagram of the transmission line system with the STATCOM 54
5.2 Three phase Vpcc without the converter.................................. 55
xi
5.3 Single line diagram of the transmission line system without the STAT
COM .............................................................. 55
5.4 The magnitude of Vpcc without the converter.......................... 55
5.5 The relationship between Vpcc and d ................................. 56
5.6 Response to a Step Change in the Reference .......................... 57
5.7 Injected current to compensate for the reference step change......... 58
5.8 Response to a Step Change in the sending end voltage................. 59
5.9 Injected current to compensate for the sending end step change .... 59
5.10 Response to a Step Change in the receiving end voltage .............. 60
5.11 Injected current to compensate for the receiving end step change .... 61
5.12 Fourier magnitude spectrum of Vpcc................................... 62
5.13 Fourier magnitude spectrum of Iinj................................... 63
5.14 Fourier magnitude spectrum of 11 63
C.l PI controller........................................................ 80
C.2 Pulse width modulation generator .................................... 80
C.3 Power System with the converter and the control system............... 81
C.4 Switches of ACAC boost converter.................................... 82
C.5 Sending end voltage generator ....................................... 83
xii
TABLES
Table
B.l Coupling Transformer Parameters................................. 78
B.2 Controller Data................................................. 78
B.3 System Parameters............................................... 79
B.4 Converter Parameters............................................ 79
xiii
1. Introduction
1.1 Overview
In recent years, the electricity demand is growing dramatically and peoples
concerns about having clean, reliable and efficient power supplies by replacing
the conventional power plants with clean renewable sources is being a very con
siderable issue. Therefore, the operators of the power system industry need
to upgrade the electricity infrastructure to maintain these changes and the in
crease of the reliable power demand. As the consumers of the electric power have
become more reliant on highquality and highreliability electric power, many
countries are adopting Smart Grid initiatives. The Smart Grid is basically a
transmission system with higher levels of control and flexibility that will allow
better utilization of the resources in the transmission system, and hence meet
ing the requirements for safe, reliable, and efficient delivery of electric power.
The key elements in realizing Smart Grids are power electronic converters; an
arrangement of power semiconductors, capacitors, and inductors that are con
nected and controlled in a specific fashion.
The utility companies have developed a powerelectronicsbased technology
called Flexible AC Transmission Systems (FACTS). As it has been defined by
IEEE, FACTS is A power electronic based system and other static equipment
that provide control of one or more AC transmission system parameters to en
hance controllability and increase power transfer capability [1].
1
Generally, we can divide the FACTS controllers into three categories [2]:
1. Series controllers
2. Shunt controllers
3. Combined seriesseries Controllers
4. Combined seriesshunt controllers
The shunt controllers have shown that they are feasible in term of cost
effectiveness in a wide range of problemsolving in both transmission and distri
bution levels. It has been recognized that the transmitted power and the voltage
profile along the transmission line can be controlled by an appropriate amount
of reactive current injected into the system at a particular point on the system.
Also, the shunt controller is capable of improving the transient stability and
damping power oscillation during postfault events. With a highspeed power
converter, the shunt controller can even cancel the flicker problem caused by the
arc furnaces [3]. The developments in the field of power electronics have intro
duced a new family of versatile FACTS controllers, namely Static Synchronous
Compensator (STATCOM).
The powerelectronicsbased technology is referred to as Flexible AC Trans
mission System (FACTS) wdien it is connected to the transmission System, and
Custom Power technology when it is connected to the distribution system [4].
This project will focus on a FACTS device, Static Compensator (STAT
COM). The existed stateoftheart converter that has been used to realize
2
STATCOMs is called DC Link Voltage Source Inverter (VSI), which as can
be seen in figure 1(a), includes a DC capacitor, a VSI, and an injection trans
former. The proposed approach, as depicted in figure 1(b), includes an AC
capacitor bank, an AC Link vector switching converter, and an injection trans
former.
Busbar
Busbar
Coupling
Figure 1.1: Realizations of STATCOMs/DSTACOMs (a) Stateoftheart (b) Pro
posed Topology.
1.2 Literature Review
The reactive power compensation has been a well established practice to con
trol the power transferred along the transmission lines in the power systems and
improve the voltage regulation wherever its needed. In the past, the rotating
synchronous condenser had been used widely for reactive shunt compensation
in both transmission and distribution levels. Even though it has some desirable
functional characteristics, such as high capacitive output current at low system
voltage levels and inductive source impedance that doesnt cause harmonic res
onance with the transmission network, it has very important drawbacks those
3
need to be thought and taken care of. The most important disadvantages of
the rotating synchronous condenser are the slow response, the potential for ro
tational instability, the low short circuit impedance and the high maintenance
[5],
In recent years, the need for fast reactive compensation in power transmis
sion systems has become increasingly called for [5]. Thus, researchers had to
think about a solidstate synchronous voltage source in order to substitute the
rotating one. Therefore, in 1985, the concept of Flexible AC Transmission Sys
tem was established for the first time in the literature [6]. One of the FACTS
first generation controllers was the Static Var Compensator (SVC) [7]. It acts
like a synchronous machine with zero inertia and instantaneous response gen
erates a balanced set of three phase sinusoidal voltages. Also, it can generate
reactive power both capacitive and inductive, and its able to exchange a real
power between the AC system and energy storage if theres any. Based on self
commuted power semiconductors without turnoff capability the SVC works as
a variable impedance device, so the current can be adjusted using conventional
thyristors (with no turnoff ability) [6].
The last decade has seen a remarkable development in the industry of power
semiconductors, so the turnoff capable devices such as Gate TurnOff Thyristors
GTOs and Integrated GateCommutated Thyristors IGCTs have been added
to the family of fully controlled power semiconductors. Having the turnoff ca
pable devices allows a second generation of the FACTS devices based on Voltage
4
Source Inverters (VSI) to be introduced [6], The stateoftheart the most im
portant VSIbased FACTS controllers are the Static Synchronous Compensator
(STATCOM), the Static Synchronous Series Compensator (SSSC) and the Uni
fied Power Flow Controller (UPFC) [8]. The stateoftheart converter that has
been used to realize these controllers is called DC Link based Voltage Source
Inverter (VSI), so they all have an intermediate DC stage. These converters
may be convenient and useful in the field of industrial AC Motor Drives be
cause the intermediate DC stage is needed in order to realize independent and
unbalance threephase power systems. However, it would be redundant if we
have the intermediate DC stage in dealing with control of power flow and/or
voltage regulation in AC power systems since the frequency is constant there [6].
Recently, there have been researches aim to substitute the DC link with an
AC one without missing the functional capability that the DC link based VSI
has. In his paper[9],G. Venkataramanan presents a fundamentally different ap
proach for realizing power control functions using threephase vectorswitching
converters instead of the DC link. Also, with F. MacillaDavid, Venkatara
manan proposes a new FACTS device based on pulse width modulated ac link
conversion named TController [10]. Based on the Vector Switching Converters,
it offers functional capabilities similar to the Unified Power Flow Controller.
Julio C. RosasCaro, Juan M. Ramirez and Fang Z. Peng introduce a Simplified
Vector Switching Converter SVeSC and the topology of the E and T controllers.
Based on this novel simplified scheme, which reduces the number of switches, it
increases the reliability and reduces the cost of implementation while it holds
5
the operating principle [11].
1.3 Outline of the Research
The first chapter of this thesis introduced a brief overview about the FACTS
devices and the shunt controllers, and it focuses on STATCOM. Also, a literature
review on how the reactive power compensation was established and the devel
opments it has been through to be what it is today was discussed in chapter one.
Chapter two introduces the concept of the vector switching converter (VeSC)
along with the corresponding converter model, equivalent circuit, switch real
ization, and modulation strategy.
Chapter three introduces the concept of the static synchronous compensator
(STATCOM). in this chapter we discuss the stateoftheart STATCOM along
with the proposed one. The principle of operation, the design considerations
of the proposed STATCOM and the voltage at the point of common coupling,
(Vpcc), are being discussed in this chapter.
Chapter four introduces the control strategies used in this work. Open loop
and PI controller have been designed and tested in this chapter. The state space
equations for the system discussed in this work have been derived and linearized
around an operating point using small signal model. Loop gain shaping using
bode plot and the performance indices to have a stable and fast control system
have been discussed in this chapter.
6
In chapter five, computer simulations are carried out to verify the perfor
mance of the proposed PWM ACAC converter based STATCOM using MAT
LAB/Simulink. The results of the simulations show the response of the system
to the disturbances on the nonmanipulated inputs and step change in the ref
erence voltage.
Finally, chapter six has the conclusion and the future work.
7
2. Vector Switching Converter (VeSC)
2.1 Introduction
After several ACAC conversion devices without frequency change to realize
the power flow7 control had appeared in the literature, Giri Venkataramanan
introduced the Vector Switching Converters in [9]. The principle of Pulse Width
Modulation is used in these devices to ease the power flow control technique and
have a better performance. VeSC is able to control the power flow at any point
of connection with an arbitrary number of branches in a complex system [9].
2.2 Converter Model
A schematic of a singlepole Nthrow threephase vector switching converter
is illustrated in Figure 2.1. This system controls the power flow7 between N stiff
three phase voltage sources (Vt\(ABC) to Vtm(ABC) and one stiff three phase
current source Ip(ABC) as shown in the figure. As can be seen from the figure,
the number of switches is equal to the number of the stiff current loads, and the
number of throws is equal to the number of the stiff voltage sources.
Assuming ideal throws of the switches is a valid assumption according to
[9]. These assumptions include:
The forward voltage drop of the switch throws during the onstate is ne
glected.
The onstate current carrying capacity and the offstate voltage blocking
capacity correspond to the current and the voltage ratings of the system.
8
Figure 2.1: Schematic of SinglePole NThrow ThreePhase Vector Switching Con
verter
The transition period between the open and closed switch throws that
permit repetitive highfrequency switching are neglected.
Also, assuming that the voltages at the throw' terminals and the switch pole
currents are stiff, allows neglecting their variations over the switching period.
Having all these assumptions in hand makes it possible to focus on the power
transfer process and the functioning features. In practical power converters, fil
ter elements appropriately applied at the input and output ports of the system
would ensure that these assumptions are valid.
9
The system shown in Figure 2.1 generates an adjustable threephase pole
voltage (Vpa, Vpb, and VpA) by switching between N stiff three phase voltage
sources {Vtx(ABC), Vt2(ABC), VtN(ABC)) [for, venc). Since the poles in the figure
are ganged together, we can say that tiA = tiB = tic for i = 1,2...N.
The throw voltages Vfo throw currents Iti, pole voltages Vp and pole currents
Ip can be represented in vectors as following:
(v \ VtiA (i \ iti A (v \ VpA (l \ *pA
Vu = VtiB ? Ifi hiB , vp = VpB 1 Ip IpB
\Vtuc j \JtliC ) vW
Where i = 1,2....N.
The pole of each switch may be connected to any of the throws at a given instant
of time. To maintain continuity of the load currents, one of the throws connected
to the pole of each switch has to be closed; however, no more than one throwT can
be connected to a given pole may be closed. Otherwise, two stiff direct voltages
will be shortcircuited together and resulting in uncontrolled currents through
the switch throws.
Let Hi(t) be the switching function of a throw connecting the voltage Vtl to the
current Ip. Here, we can express the pole voltage as a function of the throw
voltage and the switching function Hi(t) as in equation (2.1),and the throw
current can be expressed as a function of the pole current and the switching
10
function as in equation (2.2).
N
Vp{t) = YJHl(t) Vti i=i (2.1)
Iu(t) = Hi(t) Ip (2.2)
The switching function, //t(/), is defined by equation (2.3).
Hi(t) =
1
<
0
if tj is closed
otherwise
(2.3)
When the switching frequency (fs) is large compared with the power frequency
(/p), the net power transfer from the voltage ports (throws) to the current ports
(poles) is established from the DC value of the switching function that can be
represented by the duty ratio {di(t)) of a particular throw. Having said that,
we can express the pole voltage and the throw current as functions of the duty
ratio instead of the switching function as following:
N
vp(t) = Y,d^yv (24)
i=1
Iti(t) = di(t) Ip (2.5)
Where the dutv ratio of the ith throw' is defined as:
/T + T
Hi(t) dt where T is the switching period (2.6)
11
(2.7)
N
=1
i=i
This converter is called Vector Switching Converter because it works by control
ling the connectivity between various threephase voltage and/or current vectors
by switching between their components simultaneously [9].
2.3 Averaged Equivalent Circuit
The average throw currents and average pole voltage can be represented in
the form of an equivalent circuit as shown in Fig. 2.2, with the terminal quan
tities represent the average value of the quantities over a complete switching
cycle.
Figure 2.2: Averaged equivalent circuit of the primitive switching power converter
By having said that, we can draw the singlephase equivalent circuit of the vec
tor switching converter shown in Figure. 2.1.
The singlepole multiplethrow switches used in the schematic shown in figure
2.1 can be realized using real semiconductors as shown in figure 2.4.
12
Figure 2.3: Averaged equivalent circuit of SinglePole NThrow ThreePhase Vector
Switching Converter
O
O
o
=
Figure 2.4: IGBTDiode realization for singlepole multiple throw switch
2.4 Pulse Width Modulated (PWM) VeSC Converter
13
2.4 Pulse Width Modulated (PWM) VeSC Converter
Solidstate line conditioners have been used in the industry to support and
improve weak and disturbed AC lines. In the past, most of these conditioners
depended on thyristor technology. Even though, these conditioners are reliable
and have a large power handling capabilities, they have a slow response speeds
and need large inputoutput filters in order to reduce the low order harmonics.
Later on, the techniques of selfcommutated switches and pulse width modula
tion have been developed, and they have improved the performance of the AC
line conditioners significantly [12] [13].
PWM to realize DCDC power conversion applications has been widely used
and well understood due to its simplicity. The technique used in PWM ACAC
converter is the same as that used to realize DCDC converters, so they have
the same simplicity. However, when it came to bidirectional requirements, it
didnt show a feasible performance due to its complexity. Later on, a new family
of PWM ACAC converters, which allows practical applications of PWM tech
nology to ACAC conversion, has been proposed.
Figure 2.5 shows the three phase PWM VeSC boost converter, one of the
new families of ACAC converters, that is used in this thesis.
This Converter may be operated through the control of the duty ratio as in
DCDC converters. This converter doesnt perform frequency conversion as the
14
V,n
Figure 2.5: Three Phase single pole double throw PWM VeSC Boost converter
The steady state inputoutput voltage gain of the boost converter is
where D is the duty ratio.
Therefore,
f'out
V
v m
lD
(2.8)
15
In the proposed compensator, a PWM VeSC converter is used to interface
between the capacitor bank and the line in order to control the reactive power
injected into the system. Figure 2.6 shows a schematic of a singlephase boost
converter to control the reactive power supplied by the capacitor bank into the
system. The converter, as shown in the figure, consists of a capacitor bank rep
resented by C2, an inductor represented by L2 to assist smoothing the current
waveform, IGBTs switching modules represented by X and X', and an output
filter capacitor represented by C\ to assist smoothing the waveform of the out
put voltage of the converter.
Figure 2.6: Single Phase Boost converter
The voltage VC2 corresponds to the capacitor bank voltage, V0 corresponds to the
IGPT chopped voltage, and Vpcc corresponds to voltage at the point of common
coupling where the compensator is connected. Likewise, Ii, Isw, Ic\ and I0 cor
respond to the current through the inductor, the current through the switches,
the current through the output filter capacitor and the output current to the
line respectively.
16
The IGBTs are driven by PWM signal generated by a Digital Signal Pro
cessor, DSP. Figure 2.7 illustrates the PWM concept.
Figure 2.7: Pulse Width Modulator Comparator Signals
As can be observed from equation (2.8), the output voltage of the converter
varies by varying the duty ratio, D.
Where,
D = ^ (2.9)
SW
Since the switching frequency, fsw = , is constant, the duty ratio can be con
trolled by adjusting the switch ontime, ton. In the PWM switching at a constant
frequency, the switch control signal, shown in figure 2.7, which controls the state
(on or of f) of the switch, is generated by comparing the control voltage with
17
the sawtooth waveform. When the control voltage is greater than the sawtooth
waveform, the switch control signal becomes high causing the switch to turn
on. Otherwise, the switch is off. The frequency of the sawtooth with a constant
peak, Vst, establishes the switching frequency, fsw, which is chosen to be a few
kilohertz to a few hundred kilohertz [14].
Figure 2.8: Voltage waveforms VpcC, V0 and VC2
Figure 2.8 shows the voltage at the point of common coupling, Vpcc, IGBT
chopped voltage, V0 and the voltage across the capacitor bank, Vc2. When the
switch X in figure 2.6 is conducting, V0 is equal V^c. When the switch X is
turned off and X' is conducting, VQ is equal the reference voltage. As a result,
the shape of VQ is a chopped VpcC whose average depends on the duty ratio, D. If
18
the duty ratio is set to be close to one, the average of VQ will be close to Vpcc. As
can be observed from figure 2.8, the voltage across the capacitor bank is equal
to the average of the chopped voltage.
Figure 2.9: Current waveforms II, ISw, lo and Ic 1
The current flows through the inductor II, the current through the switch Isw,
the current through the capacitor Ic\ and the output current I0 are shown in fig
ure 2.9. Il is continues because it is equal to the current through the capacitor
(C2), the derivative of the voltage across the capacitor, which is sinusoidal as
shown in figure 2.8. Isw is nothing but the chopped version of II since it passes
through the switch X, so when the switch is open, Isw is equal to II', otherwise,
19
its equal to zero.
h
Vr
T 
c2 Ac
(2.10)
I0 is the output current of the converter flowing into the system at the point
of common coupling, so its equal to the voltage at the point of common coupling
divided by the impedance of the capacitor bank referred to the high voltage side
of the converter.
, VpcJJ2
~ Xc
(2.11)
As can be observed from equation (2.11), the output current can be con
trolled by adjusting the duty ratio D, so by controlling the duty ratio, the
injected power into the system can be controlled. Ic\ is the result of subtracting
hw from Ia.
Id = IoIv (2.12)
According to equation (2.11), the output current of the converter I0 is pure
reactive current, if we neglect the active current resulted from the nonideality
20
of the power components. Therefore, the power injected into the system is pure
reactive power, and by controlling the reactive power injected, the voltage at
the point of common coupling wall be controlled as shown in equation (2.13).
hpcc
Ps
j(Qa Qc)
v;
Equation (2.13) will be derived in chapter 3
(2.13)
21
3. Static Synchronous Compensator (STATCOM)
3.1 Introduction
All the shunt controllers control the value of an impedance connected in
shunt with the system at the point of common coupling in order to control the
injected current into the system at that point. When the injected current is in
phase quadratic with the line voltage, the controller will supply or absorb only
reactive power.
Basically, we can divide the shunt controllers into three groups:
1. Static var compensator (SVC)
2. Static synchronous compensator (STATCOM)
3. Static synchronous generator (SSG), or STATCOM with energystorage
system (ESS)
STATCOM is defined by IEEE as a self commutated switching power converter
supplied from an appropriate electric energy source and operated to produce a
set of adjustable multiphase voltage, which may be coupled to an AC power sys
tem for the purpose of exchanging independently controllable real and reactive
power [15]. As an advanced static VAR compensator (SVC), STATCOM has
been developed with a voltage source convertor (VSC) instead of the controllable
reactors and switched capacitors. STATCOM has some disadvantages compared
with SVC regarding the cost and losses since it requires selfcommutated power
semiconductor devices such as GTO, IGBT, etc (with higher costs and losses);
22
however, it has many technical advantages over the SVC. The most important
advantages are: faster response, less space requirement, easy to be relocated,
it can be interfaced with real power sources, and unlike SVC, STATCOM has
superior performance during lowr voltage condition as the reactive current can
be maintained constant [12].
Figure 3.1 illustrates the voltage current characteristics of the STATCOM ver
sus SVC.
V
(a)
(b)
Figure 3.1: VI Characteristics of STATCOM versus SVC
3.2 The Stateoftheart STATCOM
The existed stateoftheart converter that has been used to realize STAT
COMs is called DC Link Voltage Source Inverter (VSI) as shown in figure 3.2.
The VSI converts the dc voltage across the storage device into a set of three
phase ac output voltages. These voltages are in phase and coupled with the ac
23
system through the reactance of the coupling transformer.
In order to have this STATCOM able to control the reactive power systems
Busbar
Coupling
Figure 3.2: Realizations of STATCOMs/DSTACOMs, Stateoftheart
I
and improve the system stability, using a VSI with highvoltage and highpower
capabilities may be required. A twolevel inverter can not do the job since the
semiconductor devices must be connected in series to obtain the required high
level capabilities. This can be achieved by summing several twolevel converters
with transformers or inductors, or direct series connection. Also, it can be done
by more complex topologies such as the diode clamped inverter and the flying
capacitor inverter. To overcome this complexity, Multilevel PWM inverter had
been introduced and drawn a tremendous interest as it can easily provide the
highpower requirements. Figure 3.3 illustrates the multilevel cascaded inverter.
Figure 3.4 shows the output voltage of the cascaded multilevel inverter.
24
Figure 3.3:
Figure 3.4:
Schematic diagram of a single phase CascadedType Multilevel Inverter
5V,t
a,
a,
* t
tv
>v
7764;
Output voltage of a single phase CascadedType Multilevel Inverter
25
3.3 Proposed STATCOM
Since there is no need to a variable frequencies in AC power quality and
voltage control process, having a DC stage would be considered a redundant
stage. There have been topologies in the literature eliminate the DClink and
replace it with an AClink based ACAC converter as shown in figure 3.5. These
topologies have the same functional capability as the DClink based VSI [13].
In these topologies, we can use the well know PWM technology that is used in
the DCDC converters to control the reactive power injected into the system.
As a result of being able to use the PWM technique, we will have a more simple
control of the ACAC converter to adjust the reactive current flows through the
inductance between the converter and the system.
Figure 3.6 shows a schematic of the proposed VeSC based STATCOM. The
Busbar
Coupling
Figure 3.5: Realizations of STATCOMs/DSTACOMs, Using AClink
output voltage of the converter and voltage across the switches are shown in
figure 3.7.
26
Point of
common
Figure 3.6: AClmk based STATCOM
Figure 3.7: Switch voltage and output voltage waveforms
27
3.4 Principle of Operation of STATCOM
As shown in figure 3.8, the proposed STATCOM consists of AClink and AC
AC converter connected to the system through a coupling transformer. In order
to control the exchange of the real and reactive power between the STATCOM
and the system, we adjust the amplitude and the angle of the output voltage
of the STATCOM. With disregarding the losses of the converter used in the
STATCOM, we can consider the output voltage of the converter to be in phase
with the systems voltage. Having that under consideration, there wouldnt be
a real power circulating in the STATCOM, so the real source wont be needed.
When the output voltage is adjusted to be greater than the systems voltage,
the STATCOM will act as a reactive power generator; therefore, the reactive
power will flow from the STATCOM into the system, and itll be operated in
the capacitive mode. In the other hand, when the converters output voltage
is adjusted to be less than the systems, the reactive power will flow from the
system to the STATCOM, and the STATCOM will be operated in the inductive
mode [12].
However, converter without losses is always not the case; consequently, with
out a proper control, the capacitor voltage will discharge to compensate the in
ternal losses caused by the nonideality of the power semiconductors devices and
passive components. To overcome this challenge, a small phase shift between
the converter voltage and the power system voltage is introduced.
28
Figure 3.8: Single line diagram of the transmission line system with the STATCOM
Figure 3.8 illustrates the single line diagram of a transmission system with
a STATCOM using ACLink based VeSC connected in shunt with the system
at the point of common coupling (PCC). V, and VT represent the voltages at
the sending and receiving ends respectively, Zs, Zl, and Zr are the sending
end, transmission line, and the receiving end impedances respectively. The
AClink is a capacitor bank whose output voltage (VQ) is controlled using an
ACAC converter. The STATCOM is connected to the grid through a coupling
transformer represented in the figure by its leakage reactance Xt I0 in the figure
represents the current flows from the STATCOM to the system through the point
of common coupling. By controlling the output voltage of the converter, we can
control the reactive power injected into the system from the capacitor bank, so
the voltage at the point of common coupling can be controlled.
29
3.5 The Voltage at the point of common coupling, V^., Calculations
Vpcc can be calculated as following:
Before having the compensator, the system will be as shown in figure 3.9.
Figure 3.9: Single line diagram of the transmission line system without the STAT
COM
Vpcc = VsVzs (3.1)
Where VZs is the voltage drop across the sending end impedance.
Vzs = IsZa (3.2)
Where Is is the current flowing in the system at the sending end.
/. = (3.3)
*8
Where Ps and Qs are the active and reactive power flow in the system before
having the compensator connected.
By substituting Eq (3.2) and Eq (3.3) in Eq (3.1), we get the voltage at the
point of common coupling as a function of the apparent power at the sending
end of the transmission line.
Thus,
Vpcc = Vs{(Fs~vjQs)Z^ (3.4)
30
When the STATCOM is connected, the system will be as shown in figure 3.8,
and the Vi
PCCnew
will be calculated as following:
Vpccnew Vs
pccneu)
{<
Ps j{Qs Qc)
Vs
(3.5)
The reactive power injected by the STATCOM (Qc) will affect the system
and increase the voltage at the point of common coupling.
Therefore, as Qc increases, (Qs Qc) decreases and the voltage drop across
Zs decreases, so Vj** increases. Since the reactive power injected into the system
from the STATCOM is function of the duty ratio of the converter, the voltage
at the point of common coupling can be controlled by adjusting the duty ratio
between 0 and 1.
3.6 Design Considerations of the STATCOM
3.6.1 Capacitor Bank Sizing
The size of the capacitor bank depends on the reactive power needed to to
boost the voltage at the point of common coupling by so much. In our case, the
voltage at the point of common coupling needs to be boosted by 2% to compen
sate for the voltage drop at this point, so with maximum compensation, VpcCnew
will be equal to 102%VpcCold. Figure 4.2 shows the Transmission Line System
with the Shunt Compensator.
Before the compensation, we can calculate VpcC as in equation (3.6):
31
Figure 3.10: Transmission Line System with the Shunt Compensator
Vpcc = K ~ IsZs (3.6)
j Vs ~ Vr
Zs + Zl + ZT
Where, Vs, Vr, Is, Zs, Zl and Zr are the voltage at the sending end, the volt
age at the receiving end, current flows from the sending end to the receiving
end, the impedance of the sending end, the impedance of the transmission line
and the impedance of the receiving end respectively.
After having the reactive power compensator connected in shunt with the
system at the point of common coupling, we can calculate the new Vpcc using
the supper position as in equation (3.8):
Vs(jXc)(ZL + Zr)
Zs{Zl + ZT jXc) jXc(ZL + Zr)
VT{ jXC)ZS
(ZL + Zr)(Zs jXc) jXcZs
(3.8)
32
Since everything in the previous equation is known but the capacitor bank (Xc),
we can find a solution for one equation and one unknown to find the appropriate
value for the capacitor bank that boosts the voltage at the point of common
coupling by the desired value.
3.6.2 Filter Design
Usually the ripple of the output current and the output voltage of the con
verter without filter may be large enough to be unacceptable to be injected into
the power system. Therefore, having filters to smooth the output voltage and
current waveforms are needed to decrease the Total Harmonic Distortion (THD)
to an acceptable value. In order to smooth the output voltage, an output ca
pacitor needs to be connected at the output of the converter as (C/) in figure
3.11. Also, (Lj) needs to be designed to smooth the current injected by the
main capacitor (C).
< L i.
Figure 3.11: Single line diagram of the STATCOM and the power system
33
Determination of Lf
In order to determine the value of the inductance of Lf, we assume a degree
of stiffness for the current flowing through Lf (iif) and determine its amplitude
of the peak to peak ripple (Aiif). Draw the waveform of the voltage across Lf
(VLf) as in figure 3.12 and calculate the area under the curve (AA) at the point
where the ripple is the largest. Now, we can use the formula in equation (3.9).
(3.9)
(3.10)
Figure 3.12: Voltage and Current Waveforms of the Inductor (Lf)
Lf =
AA
f A iLf
AA = VLfA t
34
Determination of Cf
Like in the determination of Lf, to determine the value of the capacitance
of Cf, we assume a degree of stiffness for the voltage across Cf (Vcf) and de
termine its amplitude of the peak to peak ripple (AVcf). Draw the waveform
of the current flowing through Cf (icf) as in figure 3.13 and calculate the area
under the curve (Aq) at the point where the ripple is the largest. Now, we can
use the formula in equation (3.11).
Cf
_Aq_
AVCf
A q = iCfAt
(3.11)
(3.12)
Figure 3.13: Current and Voltage Waveforms of the Capacitor (Cl)
35
4. ACLink VeSC Base STATCOM Control
4.1 Introduction
In this chapter, we discuss the control strategies used in this research work.
In this research we designed and tested open loop and PI closed loop control
systems, and they both showed satisfied results.
4.2 Open Loop Control System
In the open loop control strategy, we can control the voltage at the point of
common coupling, (V^.c), by changing the duty ratio, (d), manually as shown in
figure 4.1. The planet, g{s), represents the power circuit whose output, VpcC, is
controlled by changing the manipulated input d. The input, u, represents the
energy inputs, sending and receiving end voltages.
Using Millman theorem simplify finding the relationship between the manipu
Figure 4.1: Block diagram of the open loop control system
lated input d and the controlled output VpcC.
36
Millman Theorem
Via Millman theorem we can simplify the circuit shown in figure 4.2 to be
as in figure 4.3
Figure 4.2: Transmission Line System with the Shunt Compensator
Vm
In
Figure 4.3: Millman equivalent circuit
Where Vm is millmans voltage and Xm is millmans impedance.
Y 1 Y 1 1 za' 2 ZL + Zr (4.1)
v VsYl + VrY2 m Vi + y2 (4.2)
z 1 m Yi + Y2 (4.3)
37
V
' pec
Figure 4.4: Equivalent Circuit of the Converter
Here, we can calculate the equivalent impedance of the converter as function
of the duty ratio as following.
Xeq(d) =
(jXLfjXc)(jXcf)
jXLj jXc (P]Xcf
\Vpccm=
+ jXiT
(4.4)
(4.5)
Zm + Xeq(d)
Now, for a system with the parameters showed in appendix B, we can find the
relationship between the duty ratio (d) and the voltage at the point of common
coupling (Vpcc) which is shown in figure 4.5.
Figure 4.5: The relation between d and VpcC
38
4.3 Feedback Control System
The basic structure of the closed loop control system is shown in figure 4.6.
The plant g{s), the manipulated input d and the energy inputs u are exactly
the same as in the open loop control system. (/?) is a transducer through which
the output voltage is measured and compared with the reference voltage Vre/
to generate the error (e). When the error is generated, the compensator h(s)
processes it and generate the manipulated input to drive the controllable device
of the plant. Since our system has a single input and single output (SISO),
the control design for a nominal operating condition can be done by a classic
technique such as bode plots [16].
pcc
Figure 4.6: Block diagram of closed loop control system
4.3.1 Dynamic Model of the VeSC based STATCOM
To have the control system designed, we need to have the dynamic modeling
for the power circuit identified. Figure 4.7 illustrates a singlephase dynamic
equivalent circuit of the proposed STATCOM.
39
Figure 4.7: A schematic of STATCOM equivalent circuit
4.3.1.1 StateSpace Equations
The mathematical description of the system is described and derived using
the statespace equations as following [17]:
x = Ax + Bu (4.6)
y = Cx + Du (4.7)
Where x is a column vector containing all the state variables; u is a column
vector containing all the input variables; y is a column vector containing all the
output variables; A, B, C, and D are matrices that have appropriate dimensions
relating the state variables, inputs and outputs.
Figure 4.8 shows a single diagram of the system and the converter we are
working on in this thesis.
The state variables in the common electric circuits are the current through the
inductors and the voltage across the capacitors.
The stem equations for the capacitors, inductors and the resistors describe
40
Figure 4.8: Single Line Diagram for the System with the Converter
VR
+
i
ic
Vc
C
Figure 4.9: Sign convention of voltages and currents across two terminal Resistor,
Inductor and Capacitor
their dynamic behavior. Also, they form the starting point to develop the state
equations of the system.
Stem Equation for the Inductor:
f = (4.8)
Stem Equation for the capacitor:
dVr 1
JZ =IC ju,Vc (4.9)
Stem Equation for the Resistor:
Vr = R iR (4.10)
In our case, the state variables for the system shown in figure 4.8 are:
(Vc)) the voltage across the compensation capacitor (C).
41
(Ip), the current through the filter inductor (Lf).
(Vcf), the voltage across the filter capacitor (C/).
(Il{), the current through the transformers inductance (Lt).
(II,), the current through the sending end inductance (La).
Thus, the vector x is defined as,
x =
1p
Vcf
c
\hJ
The input variables of our system are:
(Ks), the voltage at the sending end. (Vr), the voltage at the receiving end.
Thus, the vector u is defined as,
As we are controlling the voltage at the point of common coupling, the out
put of the system will be VpcC, and the vector y will be equal to Vpcc:
V = [Vpccj
By using the Stem Equations (4.8) (4.9) and (4.16), we can derive the state
space equations those represent the system shown in figure 4.8 in the state
42
equation form.
Solving for Vc dVc h i7 dt ~ c( Ip) JujVc (4.11)
Solving for Ip: ^ = T^c iVc,) }.rP (4.12)
Solving for Vcf
dVCt 1  (4.13)
Solving for Iit\ d ht dt. = ^(Vc, h,Rt  Ml (4.14)
Solving for Ils \ dll df J (V8 ^Ls^s Vpcc) j^^Ls (4.15)
Solving for V^cc:
Vpcc = {Ll + Lr){^jL + ]y + ju{h, + Jjht)) + {Rl + Rt){h, + jjht) + Vr
(4.16)
To have the state equations in the form (x = Ax + Bu) and (y = Cx + Du),
we used MATLAB as shown in the Appendix A.l, and we got:
43
"4l,l "4l,2 "4l,3 "4l,4 "4l,5 ( Vc
dip dt "42,1 "42,2 "42,3 "42,4 "42,5 S
dVc, ~ct = "43,1 "43,2 "43,3 "43,4 "43,5 Vc,
dll, ~3t "44,1 "44,2 "44,3 "44,4 "44,5 ht
dlu ^"45,1 "45,2 "45,3 "45,4 "45,5y
/
+
#1,1 #1,2
#2,1 #2,2
#3,1 #3,2
#4,1 #4,2
#5,1 #5,2
\
M
W
/
v
y pcc
I Ci,i C 1,2 Cl,3 Cl,4 Cl,5
Ip
Vc,
ht
\7W
+ 1 #1,1 #1,2
W
(4.17)
(4.18)
Where ,4, B, C and D are functions of the duty ratio (d) and the system param
eters (C, Cj, #ti #0 #51 #sj #Li #r> #r)
44
Steady State
Since the capacitors and the inductors are constant in the steady state, the
derivative of inductor currents and capacitor voltages are zero.
dVÂ£ _ _dhL_ djL n
dt dt dt dt dt
Therefore,
0 = Ax + Bu (419)
x = A~lBu (4.20)
The output y is given by:
y = Cx + Du (4.21)
By substituting the value of x from equation (4.20) in equation (4.21), we get:
y = C(A~xBu) + Du (4.22)
Since the equations are all in terms of complex quantities, separation into real
and imaginary parts is necessary. Therefore, x vector will become
x = (vcr Va Ipr IPi VCfr VCfi htr hti hST hs^j
4pcc bpccr T jVpcci
\Vpcc] = x/(VW)2 + (^cci)2
45
Therefore, the equations (4.17) and (4.18) become:
( dVcr \
at
dVa
dt
dlpr
dt
dlr
dt
dVCfr
~St
dVcH
dt
dlu.
dt
dh
dt
dhsr
dt
dIL
Var/
(a ,' \
4i,i ^4i,io
A
5,5
^4io,i A
10,10
l Vcr^
Vr
a
1pr
*pi
Vc,r
Vofi
dLtr
hti
iLsr
V ^Lsi)
( O O \
1,1 ' #1,4
+
Sio,i 610,4
fv.\
Vsi
Vr,
(4.23)
\Vri J
C1.1
c
1,10
(VCr^
Va Ipr
Ipi (v \
Vcfr + ^611 Dx 2 613 614^ vsl
Vofi v^r
dLtT lLtt dL,r [Vrij
V7W
(4.24)
46
4.3.2 Proposed Controller
As the product between the manipulated input (d) and the state variables
(x) generates the undesired nonlinearity in the system, we need to linearize the
system in order to be able to apply classical control techniques [16]. Therefore,
the first step we need to consider in designing the controller is linearizing the
plant around an operating point and then we find a combination of a propor
tional (P), integral (I) gains. PI controllers are widely used in the industry
and have become standard for control system design, and the more complicated
techniques are used only if PI controllers fail.
The closed loop control system including the PI controller is shown in figure
4.10.
V,
ref
JUU1 y.
PI d PWM Pulse Generator Power
Controller i System
m
p <*
I'pcc
Figure 4.10: Block diagram for the control system
The duty ratio can be generated by processing the error in the PI controller,
and then it can be compared with the sawtooth waveform in the PWM pulse
generator to have the pulses to drive the switches of the power converter.
The duty ratio can be represented as:
d(t) = Kpe{t) + Kt [ e{r)dT (425)
Jo
47
4.3.2.1 Small Signal Model
Since the system is nonlinear, a small signal model is needed to linearize
the system around a nominal operating point, lets say x0. The operating point
can be obtained by assigning a value for the duty ration, lets say do, and solve
the equations in the steady state. The equations can be written as in the form
shown in equations (4.26) and (4.27).
x{t) = f(x(t),u{t), d(t)) (4.26)
y{t) = g{x{t),u{t),d(t)) (4.27)
Thus, linearizing the equations shown above around the operating point, Xo,
becomes:
f(x{t),u(t),d.(t)) = f(x0, uq, d0) + L
g(x(t),u(t),d(t)) = g(xQ, u0, d0) + fz
(x{t) x0) +
o
(x(t) x0) + 2
{d(t) do)
(d(t) do)
0 0
By applying Laplaces transform, the small signal model becomes:
(4.28)
(4.29)
s Ax = A Ax + B Ad (4.30)
AV^, = C Ax + D Ad (4.31)
Where,
A = M. ,B=9L Â£1 ll D= Â§1
dx dd 0 dx 0 0 dd
Ax = (x xq),
AVpcc (bpcc Lpcco) &frd Ad (d do)
48
From equation (4.30), we can find Ax and substitute it in equation (4.31)
to find the transfer function of interest AYP?C.
Ax = (si A) IB Ad
Al/pe, = C(sl A)~'B Ad+DAd
Now, we can write the transfer function of the power system as:
Wycc
Ad
C(sl A)~lB + D
(4.32)
(4.33)
(4.34)
The transfer function of the PI controller can be written using Laplace
transform as:
Ad AV ,
~r~ = (Kp H ) 4.35
Ae s
The block diagram of the small signal model of the whole system can be shown
as in figure 4.11.
The transfer function of the whole system is defined as ^yCCf
AVref
Figure 4.11: Block diagram for the small signal model
AVpcc T(s)
AVTef fd 1 + T(s)
(4.36)
49
Where T(s) is the loop Gain:
T(s) = 0 h{s) g{s) (4.37)
Appendix A.2 shows the Matlab code that is used in this thesis to linearize the
system around an operating point, d = .5.
4.3.2.2 Loop Gain Shaping using Bode Plots
There are three performance indices need to be considered in order to have
the controller well designed [16]:
1. Stability Margins
In order to have the system stable, the phase angle of the loop gain must
be away from (180) when the magnitude is unity. Security margins are
imposed by control designers to keep the system away from such critical
values. These margins are called phase inversion frequency (PIF), thats
when T(s) has a phase angle of 180, and the gain crossover frequency
(GCF), thats when the T(s) has a magnitude of (1). It is necessary to
maintain GCF < PIF to provide a positive phase margin,(fim, at GCF
and positive gain margin, Gm at PIF.
2. Bandwidth
GCF is called bandwidth as well, and it needs to be as high as possible
in order to fast the response of the regulator.
BW = (4.38)
response time
50
3. Steady State Error
The steady state error can be directly evaluated from T(0). According to
equation (4.37), T(s) should be infinite in order to drive the steady state
error to zero.
Appendix B shows the parameters of the system, coupling transformer and
the converter. Based on this data, the regulator is designed by assigning a value
for the transducer (/? = 10~5) to measure the output voltage which is about
\\t)KV. The frequency response of the partial loop gain, fi g(s), is shown in
figure 4.12. From the figure, we can see that the system is unstable because its
obvious that PIF < GCF. Also, T(0) doesnt go to infinite.
Figure 4.12: Bode Plot for the partial loop gain fig(ju))
Therefore, an appropriate regulator to stabilize the system needs to be de
signed. in this research, we used (SISOTOOL), a matlab function to calculate
51
the control gains [18]. By selecting the PI controllers gains, Kj 2554.5 and
Kp = 1.175, the frequency response for the final loop gain, T(s) = flh(s) g(s)
hpromps as shown in ficmrp 4 1 4
Figure 4.13: Bode Plot for the partial loop gain (/3h(jtn)g(ju>))
As we can see from figure 4.13, can consider that the controller is well
designed as all the performance indices are met. The stability security margins
are within the specified range (Gm 6.25dB = 2.05, (j>m = 85.1), and the
condition that CGF < PIF is met. Also, the the integral part of the regulator
guarantees that T(0) = oo.
Figure 4.14 shows the time response for the controller to respond for the
disturbances those may occur in the system. As we can see from the figure, the
system recovers from the disturbance in 0.05 second, which is OK for a 110KV
100MVA system.
52
Time Response
Figure 4.14: Response time of the controller
53
5. Computer Simulation
In this chapter, computer simulations are carried out to verify the perfor
mance of the proposed PWM ACAC converter based STATCOM using MAT
LAB/Simulink. The system including the STATCOM is simulated based on the
specifications shown in appendix B. Figure 5.1 illustrates the single line diagram
of the system with the STATCOM.
Figure 5.1: Single line diagram of the transmission line system with the STATCOM
Figure 5.2 shows the voltage at the point of common coupling when the
converter is disconnected, and the system is as shown in figure 5.3. Figure 5.4
shows the magnitude of Vpcc without the converter.
54
x 10s
Figure 5.2: Three phase Vpcc without the converter
Figure 5.3: Schematic of a single line diagram of the transmission line system
without the STATCOM
0.81 '..... \
J5, 0.6 >
u
u
0.2 H
!
o1111J11111
0 0.1 0.2 0.3 04 05 08 0.7 08 09 1
Time(sec)
Figure 5.4: The magnitude of Vpcc without the converter
Figure 5.5 shows the response of the voltage at the point of common coupling
to the change of the duty ratio (d). As can be seen from the figure, when the
duty ratio is zero, the voltage is affected by only the filters and increased by a
very small portion. However, when the converter is fully connected (d = 1), the
55
voltage is affected by the filter and the whole amount of the capacitor bank and
increased by (2%) as designed.
Figure 5.5: The relationship between VpcC and d
Appendix C has the MATLAB/Simulink block diagrams of the whole sys
tem; transmission line, coupling transformer, converter and the reactive ele
ments.
The typical tests evaluated are the response of the system upon a step change
in the reference voltage and upon small disturbances on the nonmanipulated
inputs (VsendkVrec).
5.1 Response to a Step Change in the Reference
This test is carried out to verify the boundary input boundary output
(BIBO) stability of the system and the dynamic performance of the regula
tor. In this test, we commit a 1.5% step change in the reference voltage, and
the system response is shown in figure 5.6. As can be seen from the figure,
56
the system is stable and the regulator responds to the step change in a short
time, 0.04sec, which indicates that the bandwidth is adequate. Also, the results
show that the regulator is able to track the reference, and the output voltage is
following the command voltage.
Figure 5.6: Response to a Step Change in the Reference
Figure 5.7 shows the injected current into the system in order to compensate
for the change in the reference.
5.2 Response to Disturbances
This test is carried out to evaluate the ability of the system to track the
reference under small disturbances on the nonmanipulated inputs of the system.
Step changes have been committed to the magnitude of the sending and receiving
end voltages, and the regulator showed a very acceptable response to these
disturbances.
57
Figure 5.7: Injected current to compensate for the reference step change
5.2.1 Response to a Step Change in the Sending End Voltage
A step change of 2% has been committed to the magnitude of the sending
end voltage and lasts for 0.5,sec. Figure 5.7 shows the magnitude of the voltage
at the point of common coupling, the peak to peak and the step change on
sending end voltage, Vsend
As can be seen from the figure, the response of the system to the disturbance,
when it happened and after it was gone, is very acceptable since the regulator
tracks the reference in both when the disturbance occurs and and when it is
gone. The speed response of the regulator is 0.05sec in both, when the system
encounters the disturbance and when the sending end voltage returns to normal.
Figure 5.9 shows the injected current into the system in order to compensate
for the change in the sending end voltage.
58
/ II 1.2 1.3 1.4 1.5 1.6 1.7
Time(sec)
Figure 5.8: Response to a Step Change in the sending end voltage
Figure 5.9: Injected current to compensate for the sending end step change
5.2.2 Response to a Step Change in the Receiving End Voltage
The same as in the previous subsection, a step change of 2% that lasts for
0.5sec has been committed, but in this section its committed to the magnitude
of the receiving end voltage. Figure 5.10 shows the magnitude of the voltage at
the point of common coupling, the peak to peak and the step change on
receiving end voltage, Vnec.
59
Time(sec)
Figure 5.10: Response to a Step Change in the receiving end voltage
Figure 5.11 shows the injected current into the system in order to compen
sate for the change in the receiving end voltage.
Figure 5.11: Injected current to compensate for the receiving end step change
60
The results of the small disturbances show that the regulator is able to track
the reference upon small disturbances on the nonmanipulated inputs, and the
system has a fast speed response to recover from these disturbances and bring
the system back to the steady state.
5.3 Waveform Quality
The nonlinear loads produce harmonic currents, which interact with the
utility supply system in an undesired way. This interaction works on increasing
the voltage and current total harmonic distortion in the system. The IEEE
standard 519 1992 came to put limits to the level of harmonic currents injected
into the point of common coupling. The levels of the harmonic distortion are
described by either the complete harmonic spectrum with both magnitude and
angle of each individual harmonic component, or to use a single quantity of the
effective value of harmonic distortion [19]. According to the IEEE standard [20],
we can calculate the total harmonic distortion as in equation (5.1):
Where /1, /2, /a,... are harmonic currents in amperes. I\ refers to the fun
damental frequency current (60Hz). /2 refers to the second harmonic, or the
current at twice the fundamental frequency (120Hz) and so on.
5.3.1 THD of the Voltage at the Point of Common Coupling
Figure 5.12 shows the Fourier magnitude spectrum of the voltage at the
point of common coupling, The Matlab code thats used to plot the figure
and calculate the THD is provided in appendix D.
(5.1)
61
Figure 5.12: Fourier magnitude spectrum ofVpcc
As we can see from the figure, the magnitude of the voltage at the funda
mental frequency (60Hz) represents the voltage magnitude of the voltage needed
to be at the point of common coupling, the magnitude voltages around (3KHz)
and (6KHz) represent the harmonic voltages caused by the switches of the con
verter as the switching frequency is (3KHz). The THD of V^. is calculated and
found to be (0.553%).
Figure 5.13 shows the Fourier magnitude spectrum of the injected current
at the point of the common coupling Iinj. The THD of Iin] is calculated and
found to be (0.571%).
Figure 5.14 shows the Fourier magnitude spectrum of the current trough the
line 11. The THD of Ii is calculated and found to be (0.05%).
62
Magnitude of 7,nj
Frequency(Hz)
Figure 5.13: Fourier magnitude spectrum of Unj
Magnitude of the Current through the Line
Figure 5.14: Fourier magnitude spectrum of II
63
6. Conclusion and Future Work
6.1 Conclusion
In this research, an efficient approach to realize the STATCOM in order to
compensate for a voltage drop at the point of connection has been proposed.
The proposed approach is based on ACAC vector switching converter, VeSC.
Since there is no need to have a variable frequency at any point during the
process, having a dc stage will be considered redundant. Therefore, ACAC
converter without a DC stage will be considered a good replacement to the DC
AC inverter in this process. Using ACAC converter allows us to take advantage
of using the well known and easy to control pulse width modulation technique
that is used in the DCDC converters. Also, the simulations were carried out
by Matlab showed that using an ACAC VeSC converter instead of the DCAC
inverter to realize the STATCOM allows us to use a less number of switches to
do the same job. The PI controller thats been designed in this work has shown
a feasible performance in terms of stability and speed response. The waveform
test thats been done by calculating the total harmonic distortion, THD, of the
voltage at the point of common coupling, the injected current and the current
through the line shows that they are way below the limits in the IEEE Std
5191992.
6.2 Future Work
This work can be extended to be implemented in the lab and compare the
simulation results we got out of this research to the experimental results. Also,
64
a control system for the distribution static synchronous compensator, DSTAT
COM, can be designed with taken the unbalance issue under consideration. In
addition, a study for the losses and the cost of implementation can be done and
compared to the stateoftheart.
65
APPENDIX A. STATE EQUATION CALCULATIONS AND
LINEARIZING THE SYSTEM
A.l
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
Calculating A,B,C,D and y Matrices
clear all; close all; clc
syms dip vc vcf dvc dvcf ip dilt ilt dils ils
syms vr vs Vpcc
syms c cf If It Is lr Rs Rr Rt LI R1 N d w real
syms vsr vsi vrr vri real
syms vcr vci vcfr vcfi ipr ipi iltr ilti ilsr ilsi real
eql=dvc = (l/c)*(ip)j*w*vc;
eq2=dip = (1/lf)*(vcd*vcf)j*w*ip;
eq3=dvcf= (1/cf)*(d*ipilt)j*w*vcf;
eq4=dilt= (l/lt)*(vcfilt*Rt(Vpcc/N))j*w*ilt;
eq5=dils= (l/ls)*(vsils*RsVpcc)j*w*ils;
eq6=Vpcc= (Ll+lr)*(dils+(dilt/N)+j*w*(ils+(ilt/N))) + ...
(Rr+Rl)*(ils+(ilt/N))+vr;
SS=solve(eql,eq2,eq3,eq4,eq5,eq6,dvc',dip, dvcf,...
dilt,dils,Vpcc);
dvc = simple(SS.dvc);
dip = simple(SS.dip);
dvcf = simple(SS.dvcf);
dilt = simple(SS.dilt);
66
0020 dils = simple(SS.dils);
0021 Vpcc = simple(SS.Vpcc);
0022 Xr=[vcr; vci; vcfr; vcfi; ipr; ipi; iltr; ilti; ilsr; ilsi]
0023 ur=[vsr; vsi; vrr; vri];
0024 vc = vcr + j*vci;
0025 vcf = vcfr + j*vcfi;
0026 ip = ipr + j*ipi;
0027 ilt = iltr + j*ilti;
0028 ils = ilsr + j*ilsi;
0029 vs = vsr + j*vsi;
0030 vr = vrr + j*vri;
0031 exl = eval(dvc); ex2 = eval(dvcf);
0032 ex3 = eval(dip); ex4 = eval(dilt);
0033 ex5 = eval(dils); ex6 = eval(Vpcc);
0034 A1 = simple(real(exl)); A2 = simple(imag(exl));
0035 A3 = simple(real(ex2)); A4 = simple(imag(ex2));
0036 A5 = simple(real(ex3)); A6 = simple(imag(ex3));
0037 A7 = simple(real(ex4)); A8 = simple(imag(ex4));
0038 A9 = simple(real(ex5)); A10= simple(imag(ex5));
0039 All= simple(real(ex6)); A12= simple(imag(ex6));
0040 Vr= eval([Al; A2; A3; A4; A5; A6; A7; A8; A9; A10]);
0041 Yr= eval([All; A12]);
0042 YY= sqrt((Yr(l)~2)+(Yr(2)~2));
0043 for ii=l:10
67
0044
Ar(1:10,ii)= simple(diff(Vr,l,Xr(ii)));
0045 end
0046 Ar=simple(Ar);
0047 B=simple(VrAr*Xr);
0048 B=simple(B);
0049 Br= simple(diff(Vr,l,d));
0050 Br= simple(Br);
0051 for ii=l:4
0052 Brl(1:10,ii)= simple(diff(Vr,1,ur(ii)));
0053 end
0054 Brl= simple(Brl);
0055 for ii=l:10
0056 Cr(l,ii) = simple(diff(YY,1,Xr(ii)))
0057 end
0058 Cr=simple(Cr);
0059 Dr= simple(diff(YY,1,d));
0060 Dr=simple(Dr);
0061 for ii=l:4
0062 Drl(l,ii)= simple(diff(YY,l,ur(ii)));
0063 end
0064 Drl= simple(Drl);
A.2 Vpcc Calculations
0001 clear all; close all; clc
68
0002 V=110e3; S=100e6;
0003 N=10; F=60;
0004 w=2*pi*F;
0005 thr=20; ths=0;
0006 Zb=(V~2)/S;
0007 Zbl=((V/N)~2)/S;
0008 vs=V*sqrt(2/3)*(cos(ths*pi/180));
0009 vr=V*sqrt(2/3)*(cos(thr*pi/180)+li*sin(thr*pi/180));
0010 %===================================%
0011 7. system parameters'/.
0012 Rs=.025*Zb; Rl=0.045*Zb;
0013 Rr=.025*Zb; Rt=.8*Zbl;
0014 ls=.07*Zb/w; Ll=.l*Zb/w;
0015 lr=0.07*Zb/w; lt=(5.05e2)*Zbl/w;
0016
0017 /===================================
0018 '/. Reactive components '/.
0019 lf=5.75e4;
0020 c=8.786e4;
0021 cf=6.554e5;
0022 %==================================
0023 '/. Receiving & Sending Voltages 7.
0024 vsr = real(vs);
0025 vrr = real(vr);
69
0026
0027
0028
0029
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
0040
0041
0042
0043
0044
0045
0046
0047
0048
0049
vsi = imag(vs);
vri = imag(vr);
ur = [vsr; vsi; vrr; vri];
%=========================
d=.5;
Ar= [0, w, 0, 0, 1/c, 0, O o o 0
w, o, O o o 1/c, o o o 0
o, o, 0, w, d/cf, 0, l/cf, 0, o, 
o, 0, o 0 5* 1 d/cf, 0,1/cf, 0,0
1/lf, o, d/lf, 0, 0, w, O o o 0
0, 1/lf, 0, , d/lf,  w, 0, o o o 0
0, 0, QT2*(L1 + lr+ls))/(Ll*ls+lr*ls+Ll*N~2*lt+N'2*lr*lt+ ^
N~2*ls*lt), 0, 0, 0, (Rl*ls + Rr*ls + Ll*N2*Rt + N~2*Rt*lr+
N~2*Rt*ls)/(Ll*ls + lr*ls + Ll*N~2*lt+N2*lr*lt+N~2*ls*lt),w,
(N*(Rl*ls + Rr*ls Rs*lr Ll*Rs))/(Ll*ls+lr*ls+Ll*N2*lt+^
N"2*lr*lt + N"2*ls*lt), 0
0,0, 0, (N~2*(Ll+lr+ls))/(Ll*ls+lr*ls+Ll*N~2*lt+N~2*lr*lt+...
N~2*ls*lt), 0, 0, w, (Rl*ls + Rr*ls + Ll*N~2*Rt+N~2*Rt*lr+^
N~2*Rt*ls)/(Ll*ls + lr*ls + Ll*N~2*lt+tr2*lr*lt+N~2*ls*lt),0,
(N*(Rl*ls + Rr*ls Rs*lrLl*Rs))/(Ll*ls+lr*ls+Ll*N~2*lt+...
N~2*lr*lt + N~2*ls*lt)
0,0,(N*(Ll + lr))/(ls*(lt*N2+Ll+lr)+Ll*N2*lt+N2*lr*lt), ^
0,0,0,(N*(Rl*lt+Rr*ltRt*lrLl*Rt))/(ls*(lt*N~2+Ll+lr)+ ^
Ll*N~2*lt + N~2*lr*lt),0,(Rs*lr+Ll*Rs+N~2*Rl*lt+N~2*Rr*lt+ ^
70
0050 N~2*Rs*lt)/(ls*(lt*N~2 + LI + lr) + Ll*N~2*lt + N~2*lr*lt), w
0051 0,0,0,(N*(Ll + lr))/(ls*(lt*N~2+Ll+lr)+Ll*N~2*lt+N~2*lr*lt)
0052 0,0,0, (N*(Rl*lt + Rr*lt Rt*lrLl*Rt))/(ls*(lt*N~2+Ll+lr)^.
0053 + Ll*N~2*lt + N~2*lr*lt), w,(Rs*lr+Ll*Rs+N~2*Rl*lt+tT2*Rr*lt
0054 + N~2*Rs*lt)/(ls*(lt*N~2 + LI + lr) + Ll*N"2*lt + N~2*lr*lt)];
0055
0056 B=[ 0
0057 0
0058 0
0059 0
0060 0
0061 0
0062 (N*(Ll*vsr + lr*vsr + ls*vrr))/(Ll*ls + lr*ls + Ll*N"2*lt
0063 N2*lr*lt+ N~2*ls*lt)
0064 (N*(Ll*vsi + lr*vsi + ls*vri))/(Ll*ls + lr*ls + Ll*N"2*lt +^_
0065 N~2*lr*lt+N~2*ls*lt)
0066 (Ll*vsr + lr*vsr N~2*lt*vrr + N"2*lt*vsr)/(ls*(lt*IT2 + Ll^
0067 + lr)+ Ll*N~2*lt + N2*lr*lt)
0068 (Ll*vsi + lr*vsi N~2*lt*vri + N~2*lt*vsi)/(ls*(lt*IT2 + Ll^_
0069 + lr)+Ll*N"2*lt + N~2*lr*lt)];
0070 Xr = (Ar~1)*B;
0071 vcr = Xr(l); vci = Xr(2);
0072 vcfr = Xr(3); vcfi = Xr(4);
0073 ipr = Xr(5); ipi = Xr(6);
71
0074 iltr = Xr(7); ilti = Xr(8);
0075 ilsr = Xr(9); ilsi = Xr(10);
0076 Br=[0 0 ipr/cf ipi/cf vcfr/lf vcfi/lf 0000];
0077 Brl= [ 0, 0, 0, 0
0078 0, 0, 0, 0
0079 0, 0, 0, 0
0080 0, 0, 0, 0
0081 0, 0, 0, 0
0082 0, 0, 0, 0
0083 (N*(L1 + lr))/(ls*(lt*N~2 + LI + lr) + Ll*N~2*lt+N~2*lr*lt).0___
0084 (N*ls)/((Ll*lt + lr*lt + ls*lt)*IT2 + Ll*ls + lr*ls), 0
0085 0, (N*(L1 + lr))/(ls*(lt*N~2 + LI + lr)+Ll*N~2*lt+N~2*lr*lt)____
0086 0, (N*ls)/((Ll*lt + lr*lt + ls*lt)*N'2 + Ll*ls + lr*ls)
0087 (lt*N~2 + LI + lr)/(ls*(lt*lT2 + LI + lr) + Ll*N~2*lt + N~2*lr...
0088 *lt),0,(N2*lt)/(ls*(lt*N2 + LI + lr) + Ll*N~2*lt + N~2*lr*lt),0
0089 0, (lt*N~2 + LI + lr)/(ls*(lt*N2 + LI + lr) + Ll*JT2*lt + ^
0090 N~2*lr*lt),0, (N2*lt)/(ls*(lt*N2 + LI + lr) + Ll*N~2*lt...
0091 + N2*lr*lt)];
0092 Cr=[0,0,(N~2*ls*(Ll+lr)*(Ll*ls*vcfr+lr*ls*vcfrLl*Rt*iltr*ls+...
0093 Ll*N*lt*vsr+Rl*iltr*ls*lt+Rr*iltr*ls*ltRt*iltr*lr*ls+N*lr*...
0094 lt*vsr+N*ls*lt*vrrLl*N*Rs*ilsr*lt+N*Rl*ilsr*ls*lt+N*Rr*ilsr...
0095 *ls*ltN*Rs*ilsr*lr*lt))/(((N~2*(Ll*ls*vcfi+lr*ls*vcfiLl*Rt*...
0096 ilti*ls + Ll*N*lt*vsi + Rl*ilti*ls*lt+Rr*ilti*ls*ltRt*ilti*lr*...
0097 Is + N*lr*lt*vsi + N*ls*lt*vriLl*N*Rs*ilsi*lt+N*Rl*ilsi*ls*lt+...
72
0098 N*Rr*ilsi*ls*ltN*Rs*ilsi*lr*lt)~2)/(Ll*ls+lr*ls+Ll*N~2*lt+N"2 ^
0099 *lr*lt + N~2*ls*lt)~2+OT2*(Ll*ls*vcfr+lr*ls*vcfrLl*Rt*iltr*ls+^
0100 Ll*N*lt*vsr+Rl*iltr*ls*lt+Rr*iltr*ls*ltRt*iltr*lr*ls+N*lr*lt*vsr
0101 +N*ls*lt*vrrLl*N*Rs*ilsr*lt+N*Rl*ilsr*ls*lt+N*Rr*ilsr*ls*lt...
0102 N*Rs*ilsr*lr*lt)~2)/(Ll*ls+lr*ls+Ll*N~2*lt+N~2*lr*lt+N~2*ls*...
0103 lt)2)(l/2)*(Ll*ls + lr*ls+Ll*N~2*lt+N"2*lr*lt+N~2*ls*lt)~2)___
0104 (N~2*ls*(Ll+lr)*(Ll*ls*vcfi+lr*ls*vcfiLl*Rt*ilti*ls+Ll*N*lt*vsi+
0105 Rl*ilti*ls*lt+Rr*ilti*ls*ltRt*ilti*lr*ls+N*lr*lt*vsi+N*ls*lt*vri
0106  Ll*N*Rs*ilsi*lt+N*Rl*ilsi*ls*lt+N*Rr*ilsi*ls*ltN*Rs*ilsi*lr*^_
0107 It))/(((N~2*(Ll*ls*vcfi+lr*ls*vcfiLl*Rt*ilti*ls+Ll*N*lt*vsi+...
0108 Rl*ilti*ls*lt+Rr*ilti*ls*ltRt*ilti*lr*ls+N*lr*lt*vsi+N*ls*lt*...
0109 vriLl*N*Rs*ilsi*lt+N*Rl*ilsi*ls*lt+N*Rr*ilsi*ls*ltN*Rs*ilsi*...
0110 lr*lt)~2)/(Ll*ls+lr*ls+Ll*N"2*lt+N~2*lr*lt+N~2*ls*lt)~2+(N~2*...
0111 (Ll*ls*vcfr+lr*ls*vcfrLl*Rt*iltr*ls+Ll*N*lt*vsr+Rl*iltr*ls*lt+^_
0112 Rr*iltr*ls*ltRt*iltr*lr*ls+N*lr*lt*vsr+N*ls*lt*vriLl*N*Rs*...
0113 ilsr*lt+N*Rl*ilsr*ls*lt+N*Rr*ilsr*ls*ltN*Rs*ilsr*lr*lt)2)/(Ll*^
0114 ls+lr*ls+Ll*N~2*lt+N~2*lr*lt+N"2*ls*lt)~2)~(l/2)*(Ll*ls+lr*ls+...
0115 Ll*N~2*lt + N~2*lr*lt+N~2*ls*lt)~2).0.0.(N~2*ls*(Rl*lt+Rr*lt...
0116 Rt*lrLl*Rt)*(Ll*ls*vcfr+lr*ls*vcfrLl*Rt*iltr*ls+Ll*N*lt*vsr+...
0117 Rl*iltr*ls*lt+Rr*iltr*ls*ltRt*iltr*lr*ls+N*lr*lt*vsr+N*ls*lt*...
0118 vrrLl*N*Rs*ilsr*lt+N*Rl*ilsr*ls*lt+N*Rr*ilsr*ls*ltN*Rs*ilsr*...
0119 lr*lt))/(((N~2*(Ll*ls*vcfi+lr*ls*vcfiLl*Rt*ilti*ls+Ll*N*lt*vsi+^_
0120 Rl*ilti*ls*lt+Rr*ilti*ls*ltRt*ilti*lr*ls+N*lr*lt*vsi+N*ls*lt*...
0121 vriLl*N*Rs*ilsi*lt+N*Rl*ilsi*ls*lt+N*Rr*ilsi*ls*ltN*Rs*ilsi*.. .
73
0122 lr*lt)~2)/(Ll*ls+lr*ls+Ll*N~2*lt+N~2*lr*lt+N"2*ls*lt)~2+(N~2*...
0123 (Ll*ls*vcfr+lr*ls*vcfrLl*Rt*iltr*ls+Ll*N*lt*vsr+Rl*iltr*ls*lt+. .
0124 Rr*iltr*ls*lt Rt*iltr*lr*ls + N*lr*lt*vsr+N*ls*lt*vrrLl*N*Rs*^
0125 ilsr*lt+N*Rl*ilsr*ls*lt+N*Rr*ilsr*ls*ltN*Rs*ilsr*lr*lt)~2)/(Ll*^
0126 ls+lr*ls+Ll*N~2*lt+N~2*lr*lt+N~2*ls*lt)~2)~(l/2)*(Ll*ls+lr*...
0127 ls+Ll*N~2*lt+N~2*lr*lt+N~2*ls*lt)~2),(N~2*ls*(Rl*lt+Rr*lt...
0128 Rt*lrLl*Rt)*(Ll*ls*vcfi+lr*ls*vcfiLl*Rt*ilti*ls+Ll*N*lt*vsi+...
0129 Rl*ilti*ls*lt+Rr*ilti*ls*ltRt*ilti*lr*ls+N*lr*lt*vsi+N*ls*lt*...
0130 vriLl*N*Rs*ilsi*lt+N*Rl*ilsi*ls*lt+N*Rr*ilsi*ls*ltN*Rs*ilsi*...
0131 lr*lt))/(((N"2*(Ll*ls*vcfi+lr*ls*vcfiLl*Rt*ilti*ls+Ll*N*lt*vsi+^
0132 Rl*ilti*ls*lt+Rr*ilti*ls*ltRt*ilti*lr*ls+N*lr*lt*vsi+N*ls*lt*...
0133 vriLl*N*Rs*ilsi*lt+N*Rl*ilsi*ls*lt+N*Rr*ilsi*ls*ltN*Rs*ilsi*...
0134 lr*lt)~2)/(Ll*ls+lr*ls+Ll*N~2*lt+N~2*lr*lt+N~2*ls*lt) ',2+(N2 ^
0135 *(Ll*ls*vcfr+lr*ls*vcfrLl*Rt*iltr*ls+Ll*N*lt*vsr+Rl*iltr*ls*lt+..
0136 Rr*iltr*ls*lt Rt*iltr*lr*ls+N*lr*lt*vsr+N*ls*lt*vrrLl*N*Rs*...
0137 ilsr*lt+N*Rl*ilsr*ls*lt+N*Rr*ilsr*ls*ltN*Rs*ilsr*lr*lt)~2)/(Ll*..
0138 ls+lr*ls+Ll*N~2*lt+N"2*lr*lt+N~2*ls*lt)~2)"(l/2)*(Ll*ls+lr*ls+...
0139 Ll*N~2*lt + N~2*lr*lt+N~2*ls*lt)~2),(N~3*lt*(Rl*ls+Rr*lsRs*lr...
0140 Ll*Rs)*(Ll*ls*vcfr + lr*ls*vcfrLl*Rt*iltr*ls+Ll*N*lt*vsr+Rl*...
0141 iltr*ls*lt+Rr*iltr*ls*ltRt*iltr*lr*ls+N*lr*lt*vsr+N*ls*lt*vrr...
0142 Ll*N*Rs*ilsr*lt+N*Rl*ilsr*ls*lt+N*Rr*ilsr*ls*ltN*Rs*ilsr*lr*lt))/
0143 (((N"2*(Ll*ls*vcfi + lr*ls*vcfi Ll*Rt*ilti*ls+Ll*N*lt*vsi+
0144 Rl*ilti*ls*lt + Rr*ilti*ls*lt Rt*ilti*lr*ls + N*lr*lt*vsi+...
0145 N*ls*lt*vriLl*N*Rs*ilsi*lt+N*Rl*ilsi*ls*lt+N*Rr*ilsi*ls*lt...
74
0146 N*Rs*ilsi*lr*lt)~2)/(Ll*ls+lr*ls+Ll*N~2*lt+N~2*lr*lt+N~2*ls*lt)~2 _
0147 +(N~2*(Ll*ls*vcfr+lr*ls*vcfrLl*Rt*iltr*ls+Ll*N*lt*vsr+Rl*iltr*.. .
0148 ls*lt + Rr*iltr*ls*lt Rt*iltr*lr*ls+N*lr*lt*vsr+N*ls*lt*vrr...
0149 Ll*N*Rs*ilsr*lt+N*Rl*ilsr*ls*lt+N*Rr*ilsr*ls*ltN*Rs*ilsr*lr*lt)~2)
0150 /(Ll*ls+lr*ls+Ll*N~2*lt+N"2*lr*lt+N"2*ls*lt)~2)~(l/2)*(Ll*ls+...
0151 lr*ls+Ll*N~2*lt+N~2*lr*lt+N"2*ls*lt)~2),(N~3*lt*(Rl*ls+Rr*ls...
0152 Rs*lrLl*Rs)*(Ll*ls*vcfi+lr*ls*vcfiLl*Rt*ilti*ls+Ll*N*lt*vsi+...
0153 Rl*ilti*ls*lt+Rr*ilti*ls*ltRt*ilti*lr*ls+N*lr*lt*vsi+N*ls*lt*...
0154 vriLl*N*Rs*ilsi*lt+N*Rl*ilsi*ls*lt+N*Rr*ilsi*ls*ltN*Rs*ilsi*. .
0155 lr*lt))/(((N~2*(Ll*ls*vcfi+lr*ls*vcfiLl*Rt*ilti*ls+Ll*N*lt*vsi+...
0156 Rl*ilti*ls*lt+Rr*ilti*ls*ltRt*ilti*lr*ls+N*lr*lt*vsi+N*ls*lt*...
0157 vriLl*N*Rs*ilsi*lt+N*Rl*ilsi*ls*lt+N*Rr*ilsi*ls*ltN*Rs*ilsi*...
0158 lr*lt)~2)/(Ll*ls+lr*ls+Ll*N~2*lt+N~2*lr*lt+N~2*ls*lt)~2+(N~2 ^
0159 *(Ll*ls*vcfr+lr*ls*vcfrLl*Rt*iltr*ls+Ll*N*lt*vsr+Rl*iltr*ls*...
0160 lt+Rr*iltr*ls*ltRt*iltr*lr*ls + N*lr*lt*vsr + N*ls*lt*vrr 
0161 Ll*N*Rs*ilsr*lt+N*Rl*ilsr*ls*lt + N*Rr*ilsr*ls*lt N*Rs*ilsr*...
0162 lr*lt)2)/(Ll*ls + lr*ls+Ll*N~2*lt+N~2*lr*lt+N~2*ls*lt)~2)~(l/2)...
0163 *(Ll*ls + lr*ls + Ll*lT2*lt + N~2*lr*lt + N~2*ls*lt)2)];
0164 Dr=0;
0165 Drl=[(N~3*lt*(Ll + lr)*(Ll*ls*vcfr+lr*ls*vcfrLl*Rt*iltr*ls + ...
0166 Ll*N*lt*vsr + Rl*iltr*ls*lt + Rr*iltr*ls*lt Rt*iltr*lr*ls +
0167 N*lr*lt*vsr + N*ls*lt*vrr Ll*N*Rs*ilsr*lt + N*Rl*ilsr*ls*lt +
0168 N*Rr*ilsr*ls*ltN*Rs*ilsr*lr*lt))/(((N"2*(Ll*ls*vcfi+lr*ls*vcfi.
0169 Ll*Rt*ilti*ls + Ll*N*lt*vsi + Rl*ilti*ls*lt + Rr*ilti*ls*lt 
75
0170 Rt*ilti*lr*ls + N*lr*lt*vsi + N*ls*lt*vri Ll*N*Rs*ilsi*lt + ...
0171 N*Rl*ilsi*ls*lt + N*Rr*ilsi*ls*lt N*Rs*ilsi*lr*lt)"2)/(Ll*ls
0172 lr*ls + Ll*N2*lt + N~2*lr*lt + N~2*ls*lt)~2 + (N~2*(Ll*ls*vcfr +
0173 lr*ls*vcfr  Ll*Rt*iltr*ls + Ll*N*lt*vsr + Rl*iltr*ls*lt + Rr*...
0174 iltr*ls*lt  Rt*iltr*lr*ls + N*lr*lt*vsr + N*ls*lt*vrr  Ll*N*Rs*
0175 ilsr*lt+N*Rl*ilsr*ls*lt+N*Rr*ilsr*ls*ltN*Rs*ilsr*lr*lt)~2)/...
0176 (Ll*ls + lr*ls + Ll*N~2*lt+ir2*lr*lt + N~2*ls*lt)~2)~(1/2)*...
0177 (Ll*ls + lr*ls + Ll*N"2*lt+N~2*lr*lt+IT2*ls*lt)~2),(N~3*lt*(Ll+^_
0178 lr)*(Ll*ls*vcfi + lr*ls*vcfi  Ll*Rt*ilti*ls + Ll*N*lt*vsi + Rl*^
0179 ilti*ls*lt + Rr*ilti*ls*lt  Rt*ilti*lr*ls + N*lr*lt*vsi + N*ls*^_
0180 lt*vri Ll*N*Rs*ilsi*lt + N*Rl*ilsi*ls*lt + N*Rr*ilsi*ls*lt 
0181 N*Rs*ilsi*lr*lt))/(((N~2*(Ll*ls*vcfi + lr*ls*vcfi Ll*Rt*ilti*ls
0182 + Ll*N*lt*vsi + Rl*ilti*ls*lt + Rr*ilti*ls*lt Rt*ilti*lr*ls + ^
0183 N*lr*lt*vsi + N*ls*lt*vri Ll*N*Rs*ilsi*lt + N*Rl*ilsi*ls*lt + ^
0184 N*Rr*ilsi*ls*lt N*Rs*ilsi*lr*lt)~2)/(Ll*ls + lr*ls + Ll*N"2*lt^
0185 + N~2*lr*lt + N~2*ls*lt)~2 + (N~2*(Ll*ls*vcfr + lr*ls*vcfr Ll*^
0186 *lr*ls + N*lr*lt*vsr + N*ls*lt*vrr Ll*N*Rs*ilsr*lt + N*Rl*ilsr*
0187 ls*lt + N*Rr*ilsr*ls*lt N*Rs*ilsr*lr*lt)~2)/(Ll*ls + lr*ls + ^
0188 Ll*N~2*lt+N~2*lr*lt+N~2*ls*lt)~2)~(l/2)*(Ll*ls+lr*ls + L1*N"2*...
0189 lt+N~2*lr*lt+IT2*ls*lt)*2),(N~3*ls*lt*(Ll*ls*vcfr+ lr*ls*vcfr...
0190 Ll*Rt*iltr*ls + Ll*N*lt*vsr + Rl*iltr*ls*lt + Rr*iltr*ls*lt Rt*
0191 iltr*lr*ls + N*lr*lt*vsr + N*ls*lt*vrr Ll*N*Rs*ilsr*lt + N*R1*^
0192 ilsr*ls*lt+N*Rr*ilsr*ls*ltN*Rs*ilsr*lr*lt))/(((N~2*(Ll*ls*vcfi+^_
0193 lr*ls*vcfiLl*Rt*ilti*ls+Ll*N*lt*vsi + Rl*ilti*ls*lt + Rr*ilti*..
76
0194 ls*ltRt*ilti*lr*ls+N*lr*lt*vsi + N*ls*lt*vri Ll*N*Rs*ilsi*lt...
0195 +N*Rl*ilsi*ls*lt+N*Rr*ilsi*ls*lt N*Rs*ilsi*lr*lt)~2)/(Ll*ls +
0196 lr*ls+Ll*N~2*lt + N~2*lr*lt + N~2*ls*lt)~2 + (N~2*(Ll*ls*vcfr +
0197 lr*ls*vcfrLl*Rt*iltr*ls + Ll*N*lt*vsr + Rl*iltr*ls*lt + Rr*iltr...
0198 *ls*ltRt*iltr*lr*ls + N*lr*lt*vsr + N*ls*lt*vrr Ll*N*Rs*ilsr*...
0199 lt+N*Rl*ilsr*ls*lt + N*Rr*ilsr*ls*lt N*Rs*ilsr*lr*lt)~2)/(Ll*ls..
0200 +lr*ls+Ll*N~2*lt + N~2*lr*lt + N2*ls*lt)2)(l/2)*(Ll*ls + lr*ls^.
0201 +Ll*N~2*lt + N~2*lr*lt + N~2*ls*lt)~2), (N~3*ls*lt*(Ll*ls*vcfi +...
0202 lr*ls*vcfiLl*Rt*ilti*ls+Ll*N*lt*vsi + Rl*ilti*ls*lt + Rr*ilti*...
0203 ls*ltRt*ilti*lr*ls + N*lr*lt*vsi + N*ls*lt*vri Ll*N*Rs*ilsi*lt..
0204 +N*Rl*ilsi*ls*lt + N*Rr*ilsi*ls*lt N*Rs*ilsi*lr*lt))/(((N~2*(Ll..
0205 *ls*vcfi + lr*ls*vcfi Ll*Rt*ilti*ls + Ll*N*lt*vsi + Rl*ilti*ls*lt
0206 + Rr*ilti*ls*lt Rt*ilti*lr*ls + N*lr*lt*vsi + N*ls*lt*vri L1*N*
0207 Rs*ilsi*lt+N*Rl*ilsi*ls*lt + N*Rr*ilsi*ls*ltN*Rs*ilsi*lr*lt)~2)...
0208 /(Ll*ls + lr*ls + Ll*N~2*lt + N2*lr*lt + N~2*ls*lt)~2 + (N2*(L1^.
0209 *ls*vcfr + lr*ls*vcfr Ll*Rt*iltr*ls + Ll*N*lt*vsr + Rl*iltr*ls*lt
0210 +Rr*iltr*ls*lt Rt*iltr*lr*ls + N*lr*lt*vsr + N*ls*lt*vrr LI*...
0211 N*Rs*ilsr*lt + N*Rl*ilsr*ls*lt + N*Rr*ilsr*ls*lt N*Rs*ilsr*lr*...
0212 lt)~2)/(Ll*ls + lr*ls + Ll*JT2*lt + N'2*lr*lt + N~2*ls*lt)~2)(1/2)
0213 *(Ll*ls + lr*ls + Ll*N~2*lt + N~2*lr*lt + N~2*ls*lt)2)];
0214 y(n,l)= Cr*(inv(Ar))*(Br*d+Brl*ur)+Dr*d+Drl*ur;
77
APPENDIX B. SYSTEM, CONVERTER AND CONTROLLER
PARAMETERS
Table B.l: Coupling Transformer Parameters
Symbol Per Unit Value Actual Valuel\Q/\lKV 100MVA 60HZ
S 0.38 38 MV A
1 U0KV
Rp 0.4 480
Xp 0.025 8 mH
Vs 1 11KV
Rs 0.4 0.48fi
Xs 0.025 80 nH
Table B.2: Controller Data
Symbol Value
P 1 x 10~5
KP 1.175
Ki 2554.5
78
Table B.3: System Parameters
Symbol Per Unit Value Actual Value 110KV 100MVA 60HZ
S 1 100MVA
Vsend 1 110 KV
Rsend 0.025 3.02512
Xsend 0.07 22.5 mH
v v rec 1Z 20 11 KV
^rec 0.025 3.02512
Xrec 0.07 22.5 mH
Rline 0.045 5.4512
Xline 0.1 2,2 AmH
Table B.4: Converter Parameters
Symbol Per Unit Value Actual Value 11 KV 100 MV A QOHZ
S 0.38 38MVA
^Csank 2.58 0.85 mF
Filter 34.5 63.5 fiF
^LFilte r 0.185 0.6 mH
Fs 50 3000HZ
79
APPENDIX C. SIMULINK/MATLAB BLOCKS
Lf."
Figure C.l: PI controller
Figure C.2: Pulse width modulation generator
80
Figure C.3:
Power System with the converter and the control system
00
to
Figure C.4: Switches of ACAC boost converter
Figure C.5: Sending end voltage generator
83
APPENDIX D. FAST FOURIER TRANSFORM IN MATLAB
0001 clc; close all
0002 SampleTime=Vpcc.time;
0003 tmin=1.2; tmax=tmin+6/60;
0004 sampling_freq=100*Fs;
0005 alreadyjunif _sampled=0;
0006 flag=l; Fp=60;
0007 tr=[tmin : 1/( 1000*Fp) : tmin + 2/(Fp)];
0008 [mVpcc,aVpcc,freqVpcc, sampledtimeVpcc, sampled.signalVpcc] =
0009 spectrum( SampleTime, tmin tmax, Vpcc(:,l), sampling_freq,
0010 already _unif .sampled, flag );
0011 Vpcc_r = mVpcc(fi)*sin(2*pi*Fp*tr + aVpcc(fi));
0012 figure (1)
0013 plot(tr.sqrt(3/2)*Vpcc_r,b)
0014 figure (2)
0015 stem(freqVpcc,mVpcc)
0016 XX=0;
0017 for n=fi+6:6:60001
0018 XX=XX+(mVpcc(n)~2);
0019 end
0020 THD= sqrt(XX/((mVpcc(fi))~2))*100
84
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