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Development of field oriented vector controller for an induction motor using Matlab embedded coder

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Title:
Development of field oriented vector controller for an induction motor using Matlab embedded coder
Creator:
Babaiahgari, Bhanu ( author )
Language:
English
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1 electronic file (87 pages) : ;

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Subjects / Keywords:
SIMULINK ( lcsh )
MATLAB ( lcsh )
Electric motors, Alternating current -- Automatic control ( lcsh )
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bibliography ( marcgt )
theses ( marcgt )
non-fiction ( marcgt )

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Review:
In this thesis project, a eld oriented vector control system for an induction motor is implemented on an experimental evaluation board. By looking at the performance point of view, the TMS320F28335 DSP is selected as the digital controller of the vector control system. All the required peripheral and interfacing circuits are developed for the three-phase inverter control, signal measurement and for system protection as well. This project is tested by means of level-by-level approach. Firstly, it is tested using a simpler controller i.e. V/F control. Secondly, a current PI controller is implemented and next it is tested by speed PI controller. At the stage of the controller design, the vector control system is simulated in Matlab/Simulink using Simulink blocks. The simulation results meet the design specications well. When the control system is veried by simulations, the DSP evaluation board is programmed using the le generated by embedded coder (Simulink Tool) and tested. The test results show that the current regulator and speed regulator are able to control the stator current and the motor speed accurately. Finally, a performance comparison is evaluated between the conventional approach and the one used in this project. The results show that the approach used in this project has higher eciency and exibility in terms of development time.
Thesis:
Thesis (M.S.) - University of Colorado Denver.
Bibliography:
Includes bibliographic references.
System Details:
System requirements: Adobe Reader.
General Note:
Department of Electrical Engineering
Statement of Responsibility:
by Bhanu Babaiahgari.

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|University of Colorado Denver
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|Auraria Library
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945380466 ( OCLC )
ocn945380466
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LD1193.E54 2015m B33 ( lcc )

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Full Text
DEVELOPMENT OF FIELD ORIENTED VECTOR CONTROLLER FOR AN
INDUCTION MOTOR USING MATLAB EMBEDDED CODER
by
BHANU BABAIAHGARI
Bachelor of Science, Jawaharlal Nehru Technological University, 2013
A thesis submitted to the
Faculty of the Graduate School of the
University of Colorado in partial fulfillment
of the requirements for the degree of
Master of Science
Electrical Engineering
2015


This thesis for the Master of Science degree by
Bhanu Babaiahgari
has been approved for the
Department of Electrical Engineering
by
Jaedo Park, Chair
Tim Lei
Yiming Deng
November 16, 2015
n


Babaiahgari, Bhanu (M.S., Electrical Engineering)
Development of Field Oriented vector controller for an induction motor using Matlab
embedded coder
Thesis directed by Assistant Professor Jaedo Park
ABSTRACT
In this thesis project, a held oriented vector control system for an induction motor
is implemented on an experimental evaluation board. By looking at the performance
point of view, the TMS320F28335 DSP is selected as the digital controller of the vector
control system. All the required peripheral and interfacing circuits are developed for
the three-phase inverter control, signal measurement and for system protection as well.
This project is tested by means of level-by-level approach. Firstly, it is tested using a
simpler controller i.e. V/F control. Secondly, a current PI controller is implemented
and next it is tested by speed PI controller. At the stage of the controller design,
the vector control system is simulated in Matlab/Simulink using Simulink blocks.
The simulation results meet the design specifications well. When the control system
is verified by simulations, the DSP evaluation board is programmed using the hie
generated by embedded coder (Simulink Tool) and tested. The test results show that
the current regulator and speed regulator are able to control the stator current and
the motor speed accurately. Finally, a performance comparison is evaluated between
the conventional approach and the one used in this project. The results show that
the approach used in this project has higher efficiency and hexibility in terms of
development time.
m
The form and content of this abstract are approved. I recommend its publication.


Approved: Jaedo Park
IV


ACKNOWLEDGMENT
I would like to express my deepest thanks to my advisor, Dr. Jae Do Park, for
his valuable guidance and suggestions he has given me in this project. Without him,
this would have been impossible. Also, I thank the committee members, Dr. Tim Lei
and Dr. Yiming Deng for spending their vaulable time for reviewing this report and
attending my defense.
I would like to express gratitude to my mother Samanthakamani(Chitti) and my
father Nagaraju for their encouragement and support throughout the project.
I would also like to thank Muahnnad Alaraj for explaining some of the topics
related to this project.
v


DEDICATION
The thesis is dedicated to my family and entourage who have encouraged me to go
further during my life.
vi


TABLE OF CONTENTS
Chapter
1. Introduction........................................................... 1
1.1 Background ......................................................... 1
1.2 Objectives.......................................................... 2
1.3 Scope............................................................... 2
2. Induction Machine Vector Control System Description.................... 3
2.1 AC Induction Machine ............................................... 4
2.2 Three-phase Inverter and Pulse Width Modulation (PWM)............... 6
2.3 Vector Control System .............................................. 8
2.3.1 Clarke and Park Transformations............................... 9
2.3.2 Inverse Clarke and Park Transformations ..................... 11
3. Vector Control Design for Machine Control.............................. 13
3.1 Measurement and Estimation of Parameters of Induction Machine . 13
3.1.1 Rated value of Rotor Flux Linkage,\edr....................... 13
3.1.2 Stator Transient Inductance, 3.1.3 Mutual Inductance, Lm........................................ 15
3.2 Equivalent model of Induction Machine (T-Model).................... 15
3.3 Current Regulator.................................................. 16
3.3.1 Current Reference............................................ 18
3.3.2 Feed Forward................................................. 18
3.3.3 Voltage Limiter.............................................. 19
3.3.4 Anti-windup ................................................. 19
3.4 Flux Estimator..................................................... 19
3.5 Speed Regulator.................................................... 21
3.6 Simulation......................................................... 22
3.7 Discretization .................................................... 23
vii


4. DSP Programming and CCS V5.5............................................. 26
4.1 Overview of DSP .................................................. 27
4.1.1 ADC Module.................................................. 29
4.1.2 PWM module............................................... 33
4.1.2.1 Time-base submodule.................................... 34
4.1.2.2 Counter-compare submodule.............................. 38
4.1.2.3 Action Qualifier submodule ............................ 39
4.1.2.4 Deadband submodule..................................... 40
4.1.2.5 Event Trigger submodule................................ 41
4.1.2.6 Duty cycle calculation ................................ 42
4.1.3 Encoder Module.............................................. 44
4.1.4 Offset Measurement.......................................... 46
4.2 Hardware Setup.................................................... 46
4.3 System Initialization and Configuration of CCS V5.5............... 48
4.3.1 Initialization.............................................. 48
4.3.2 Configuration............................................... 48
4.3.3 Configuration of CCS V5.5 .................................. 52
4.3.3.1 Makefile Setup ........................................ 53
4.3.3.2 Configuration Parameters .............................. 54
4.4 Incremental Build Technology ..................................... 56
4.5 Troubleshooting DSP............................................... 56
5. Testing and Evaluation................................................... 57
5.1 Open loop test with V/F control................................... 57
5.2 Closed loop test with Current Regulator........................... 57
5.2.1 Analysis on Results ........................................ 59
5.3 Closed Loop test with Speed Regulator............................. 59
5.3.1 Experimental Results ....................................... 59
viii


5.3.2 Analysis on Results ........................................ 60
6. Simulink or C: A comparitive study....................................... 61
6.1 Introduction to C................................................. 61
6.1.1 How does C work?............................................ 62
6.1.2 Drawbacks of C.............................................. 62
6.1.3 Replacement for C........................................... 63
6.2 Introduction to Simulink.......................................... 63
6.2.1 Flexibility with Simulink................................... 63
6.3 Advantages of Simulink over C.................................... 64
7. Conclusions.............................................................. 66
7.1 Results from Present work......................................... 66
7.2 Future work....................................................... 66
References................................................................ 67
Appendix
A. Simulations and Waveforms .............................................. 69
A.l Simulations........................................................ 69
A. 2 Waveforms......................................................... 72
IX


LIST OF TABLES
Table
4.1 ADC input channels and corresponding addresses............................. 31
4.2 Encoder Truth table ....................................................... 46
4.3 Configuration of ADC....................................................... 49
4.4 eQEP configuration......................................................... 49
4.5 ePWM configuration......................................................... 50
5.1 Open loop test with V/F control..................................... 57
x


LIST OF FIGURES
Figure
2.1 Overview of Induction Machine vector control system................... 3
2.2 Structure of an Induction Machine..................................... 3
2.3 Operating principle of Induction Machine ............................. 6
2.4 Three Phase PWM Inverter Schematic (OrCAD) ........................... 7
2.5 Pulse Width Modulation (PWM) generation principle..................... 8
2.6 Clarke and Park Transformations...................................... 10
3.1 Equivalent T circuit of the induction motor dynamic model ........... 15
3.2 Overview of Current Regulator........................................ 17
3.3 Structure of Flux estimator.......................................... 20
3.4 Speed control Regulator.............................................. 21
3.5 Integral of the complex number in Simulink........................... 22
3.6 Saturation of the complex number in simulink......................... 23
3.7 Forward Euler approximation.......................................... 24
3.8 Integral form of Forward Euler approximation......................... 24
4.1 Programming Design................................................... 27
4.2 Flow chart of the program............................................ 28
4.3 Block diagram of ADC module [1] 30
4.4 ADC module configuration setup in this project [1]................... 32
4.5 Block Diagram of F28335 [2].......................................... 34
4.6 Internal modules of ePWM and their connections [3]................... 37
4.7 Time base counter synchronization scheme for F28335 38
4.8 Counter-compare event, up-down counter mode.......................... 39
4.9 Block diagram of ePWM dead band submodule............................ 41
4.10 Waveform of PWM with dead band inserted.............................. 42
4.11 Block diagram of eQEP module [4]..................................... 45
xi


4.12 An example waveform of the eQEP (anti-clockwise rotation)................ 47
4.13 Harware Setup in the lab ................................................ 47
4.14 Simulink code configuration for ADC...................................... 49
4.15 Simulink configuration for eQEP.......................................... 50
4.16 Simulink configuration for ePWM.......................................... 51
4.17 Simulink configuration for ePWM.......................................... 52
4.18 Make hie configuration in Matlab......................................... 53
4.19 Environment variables defined in the project............................. 55
5.1 Step response of the d and q currents.Fig(a) is the step response of the d
current with a reference of 80mA, and fig(b) is the step response of the q
current with a reference of 80mA.................................... 58
5.2 Response in q current due to a step in i current. Fig. (a) shows q current
with respect to step in d current and Fig. (b) shows q current with respect
to quadrature reference i.e. zero...................................... 58
5.3 Speed step response at 300rpm and very small bandwidth.................... 59
6.1 Programming Languages used in Embedded Designs [5]................... 61
6.2 Illustration of two different approaches that can be used in the project . 64
A.l Simulink model for V/F.................................................... 69
A.2 Simulink model for V/F subsystem.......................................... 69
A.3 Simulink model for Current control........................................ 70
A.4 Simulink model for Speed control.......................................... 71
A.5 (a) shows Stator voltages in abc reference frame and (b) shows Stator
voltages in stationary reference frame ................................ 72
A.6 Stator voltages in rotating reference frame............................... 72
A.7 (a) shows Stator currents in abc reference frame and (b) shows Stator
currents in stationary reference frame................................. 73
A.8 Stator currents in rotating reference frame............................... 73
xii


A.9 Theta varying from II to +11 ........................................... 74
A. 10 Offset in current...................................................... 74
xiii


1. Introduction
1.1 Background
AC (Alternating Current) motors have a simple structure and has higher efficiency
than the DC motors when operated at a high speed [6]. In the past, due to convenience
of torque and speed control, the DC machine had been used widely for adjustable
speed drive (ASD). However, recently, with the development of power electronics
technology, the AC machine drive system such as the induction machine and the
synchronous machine driven by a variable voltage variable frequency (VVVF) inverter
are being used. AC machines do not have the commutator and brush of DC machine,
which need regular maintenance are the weak points of a DC machine. AC motors
also provide more durable service with a lower cost compared to DC motors. Besides,
AC motors can easily be supplied directly from the grid and therefore they are widely
used in the industry. And this trend shift from DC machine to AC machine has
been continued because of the development of not only the previously mentioned
power electronics but also the control theory of AC machine such as held orientation
control.
For a variable-speed application, if the power source is DC, a variable-speed driver
is needed, which is usually done with three phase inverter. With feedback orientation,
AC motors can be modelled similar to separately excited DC motor through a series
of coordinate transformations. For the transformed AC motor model, DC motor
control methods can be applied to control parameters like speed, torque, currents to
obtain good transient performance [7]. This method of controlling the transformed
AC motor is called vector control.
Usually, an embedded microcontroller takes care of the overall operation of AC
motor controller. Among various microcontrollers, Digital Signal Processor (DSP)
can perform complex computations, such as coordinate transformations and control
algorithms.
1


1.2 Objectives
The main objective of this project is to design and implement sensored vector
control system in Matlab/Simulink on the TMS320F28335 board for an induction
machine. Also, designing an experimental setup for the students to access the entire
project is part of the task. The approach used in this project is much easier to
understand and implement the system. In the past, the programming was usually
done in C language, which requires an expert knowledge in C. But the approach used
in this project is entirely done in Matlab/Simulink, the software that many people
use in these days to reduce the time to implement the system. The final outcome of
this project should be sensored vector control system of an induction machine on an
evaluation board.
1.3 Scope
The contents of this project covers many academic and practical areas, such as
programming, debugging, analog and digital circuit design and construction, induc-
tion machine modelling and vector control theory.
2


2. Induction Machine Vector Control System Description
In this chapter, a brief description of induction machine control system is given.
The basic overview of induction machine vector control system used in this project
is shown in Fig. 2.1. The vector control system includes a few hardware devices
namely induction machine and inverter, and technical theory such as vector control
strategy and Pulse Width Modulation (PWM). Details about the different parts will
be discussed in the latter chapters.
Figure 2.1: Overview of Induction Machine vector control system.
Figure 2.2: Structure of an Induction Machine
3


2.1 AC Induction Machine
An induction or asynchronous machine is an AC electric motor in which the
electric current in the rotor needed to produce torque is obtained by electromagnetic
induction from the magnetic held of the stator winding. An induction motor therefore
does not require mechanical commutation. An induction motors rotor can be either
wound type or squirrel-cage type [8]. The induction machine is composed of a stator
and a rotor as shown in Fig. 2.2(a) and Fig. 2.2(b). The stator is fixed while the
rotor rotates inside with a small air gap between them. The rotor contains conductor
bars and end rings as shown in Fig. 2.2(b). The rotor cage is a closed conductor
as the conductor bars are all short-circuited by the end rings. The rotor is mounted
on the shaft with two bearings [8]. Normally one of the two shaft ends is used for
driving the load while the other one for mounting the shaft position or the speed
measurement devices. The stator is made up of several pole pairs. Each pole pair
has three windings placed symmetrically in space as shown in Fig. 2.2(a). Based on
the arrangement of the three windings, the flux linkages (T^,TS and Tc) generated
by the windings have 120 displacement in space. The magnitudes of flux linkages
(T^,TS and Tc) could be expressed as
(t) = J(us(t) Ris(t))dt, (2.1)
where us{t) is the applied voltage to each winding, R is the resistance of each winding
and is{t) is the current through each winding. If a three phase voltage is applied on
the stator windings, i.e.
7T ua(t) = Upk sin(2vrft + -) (2.2)
7n ub(t) = Upk sin(2vrft + ) 0 (2.3)
1 \n uc(t) = Upk sm(27Tft + ) 0 (2.4)
where Upk and / are the peak value and the frequency of the applied voltage respec-
tively, this will result in a sinusoidal flux linkage in each phase that lags the phase
4


voltage by 90 if the winding resistance is neglected, that is
^A(t) = ypksm(27r ft) (2.5)
2tt
^B(t) = 'FPk sin(2vrft + ) (2.6)
d'c(t) = 'bp*. sin(2vrft + -^) (2.7)
The waveforms of the three currents are shown in Fig. 2.3(a). In each period, the
current from each winding reaches its maximum value once. As shown the Fig.
2.3(b), the resultant flux can be obtained by adding the three flux linkages and has
a magnitude of 1.5From analysis of different moments, it could be noticed that
the magnitude of resultant flux vector doesnt change and it rotates with a constant
magnitude. The rotation of the rotor can be seen in Fig. 2.3(c). The magnitude of
this rotating flux vectro is 1.5 times of the peak value of each windings flux linkage.
The rotating speed Ns (in rpm) of the resultant flux is called synchronous speed,
calculated as
N8 = 120 x ^ (2.8)
Where / is three phase voltage frequency and P is number of poles.
The rotating resultant stator flux linkage cuts the rotor bars, which will induce a
voltage in the rotor bars. Since the rotor bars are short-circuited, this induced voltage
will drive a current in the rotor bars. By Lenzs law, An induced current is always in
such a direction as to oppose the motion or change producing it, the induced current
will generate a torque trying to make the rotor follow the rotating flux generated
by the stator windings. However, if the rotor speed is exactly equal to synchronous
speed, there will not be an induced current and hence no torque. Other external
factors like friction torque and load torque will make the rotor slow down. So the
induction machine rotor runs at a slightly slower speed than the synchronous speed
in order to get enough induced current and driving torque. There always exists a gap
5


between machine speed and synchronous speed, which is referred to as slip. This is
why induction machine has another name as asynchronous machine.
Figure 2.3: Operating principle of Induction Machine
2.2 Three-phase Inverter and Pulse Width Modulation (PWM)
The three-phase inverter supplies the induction machine with three-phase alter-
nating voltage. From the oread schematic of three-phase inverter shown in Fig. 2.4,
it can be seen that the three-phase inverter is fed by a DC voltage as the energy
input and has three parts, each containing two IGBTs and two diodes. Consider the
DC-link voltage fed into the three-phase inverter as Vdc- For phase A, if U1 is turned
on, the phase voltage relative to ground will be equal to +Vkc/2; while if switch U2
is turned on, it is equal to VdJ2.
Though it seems like the three-phase inverter only can generate two possible
voltage values for phase voltage, +VdJ2 or Vdc/2, Pulse Width Modulation(PWM)
6


makes it possible to for the three-phase inverter to convert the DC-link voltage to
three-phase alternating voltage by controlling the on-times and ofT-times of the IG-
BTs. By adjusting the proportion of on-time in one PWM switching period for the
same bridge, any value between +Vdc/2 and Vdc/2 can be obtained as the phase volt-
age. The ratio of on time and the total on and off time is described as duty cycle and
can be formulated as:
D
T
-L CVi
(2.9)
Ton + Taff
The basic principle of PWM generation is to compare waveforms of a triangular
LEVEL= 1V
PERIOD 1mS
Figure 2.4: Three Phase PWM Inverter Schematic (OrCAD)
wave (carrier wave) and a sine wave (reference wave) shown in Fig. 2.5. When the
magnitude of the sine wave is larger than the triangular wave, the PWM signal will
output a high voltage level to switch on the corresponding IGBT. On the contrary,
when the magnitude of the sine wave is smaller than the triangular wave, the PWM
7


signal will produce a low voltage level to turn off the IGBT. This process is illustrated
in Fig. 2.6. Hence the corresponding time moments of the intersections of the two
waves serve as the turning points to switch on or off the IGBT in the inverter.
To show the operation of a three-phase inverter, a simulation in Fig. 2.4 by Or-
CAD software is performed. The reference voltages for the three phases are assumed
to be constant and DC-link voltage is 220V. The loads of the inverter are assumed to
be resistive and connected in a Y-configuration.
U(U13:0UT) o U(U5:) 7 U(U6:+) & U(U7:+)
Tine
Figure 2.5: Pulse Width Modulation (PWM) generation principle
2.3 Vector Control System
Vector control, also called field-oriented control (FOC), is a variable-frequency
drive (VFD) control method where the stator currents of a three-phase AC electric
motor are identified as two orthogonal components that can be visualized with a vec-
tor. One component defines the magnetic flux of the motor, the other the torque. The
8


main advantage of vector control system is it gets rid of machine speed dependency
on power grid frequency and make it possible to reach desired machine speed within
safety and power limits, although it gives rise to a considerable complex computation
for the processor where the control algorithms are implemented.
Normally, in a vector control system, the phase currents of the machine and
machine speed are taken as control system inputs, and phase voltages to the machine
are taken as outputs. Two important transformations involved in the vector control
system allows it to transform AC machine like a separately magnetized DC machine,
namely Clarke Transformation and Park Transformation. The three phase sinusoidal
quantities can be easily transformed into DC quantities in steady state using both
the transformations.
2.3.1 Clarke and Park Transformations
If the three-phase stator coils are arranged symmetrically in space with a 120
displacement as shown in Fig. 2.6(a), and the sum of the phase currents amplitude is
zero (ia(t) + ib(t)+ic(t) = 0), neglecting the zero sequence currents, the instantaneous
three-phase currents can be expressed by an equivalent space current vector ia, with
two-phase quadrature quantities as
is(t) = |(ia(t) + ib(t)eJm/3 + ic(t)eJ4U/3) (2.10)
= |(*a(i) - - Uc(t) + - ic(t))) (2.11)
= X + */3 (2-12)
where constant 2/3 is placed in order to make the two-phase quantities to have the
same amplitude as the three-phase quantities. As can be seen from the Fig. 2.6(a),
the o-axis of the aft coordinate system is aligned with the direction of the A-phase
space vector. As the aft coordinate system is stationary with respect to the coils and
the coils are fixed to the stator, the aft coordinate system is stationary as well.
9


(a) (b)
Figure 2.6: Clarke and Park Transformations
In vector control theory, the three-phase to two-phase coordinate transformation
is named as Clarke Transformation. The reverse process that turns three-phase back
to two-phase is called Inverse Clarke Transformation, which is explained in the latter
sections. Clarke Transformation can be expressed in the matrix notation as:
2 -1 -1
ia 3 3 3
_u C3 C3_
%
tc
(2.13)
respectively. This transformation can be applied any other three-phase quantities,
such as flux, voltages and so on, in order to get two-phase quantities.
If you notice the a and the /3 components of these rotating vectors, you could
see that they are still AC sinusoidal quantities. Therefore a new coordinate system
is defined, called the dq coordinate system, which has the same origin as the ot/3
coordinate system but it rotates with the speed we specify. Usually we rotate dq
coordinate system with the same speed as flux rotates to make the imaginary part
of the coordinate system to be zero. This transformation of a space vector can be
achieved by multiplying the vector by e-J0, where 9 is the angle between the two
coordinate system. As seen in the Fig. 2.6(b), the afd coordinate system has been
10


transformed to dz coordinate system. The transformation can be explained as:
'i-dq
ioc/3 x e
-jo
(2.14)
This Transformation from the a/3 coordinate system to dq coordinate system is called
Park Transformation while its reverse process is called Inverse Park Transformation,
which is explained in the next section. If the vector notation is expressed in terms of
scalar notation, the above equations can be written as:
A T ji/3 (2.15)
idq b 4 jiq (2.16)
and e can be expanded using Eulers formula as:
e~jd = cos 9 j sin 9 (2-17)
Therefore equation 2.14 can be expressed in matrix form as:
id cos 9 sind ^a
h sin 9 cos 9
(2.18)
2.3.2 Inverse Clarke and Park Transformations
As said earlier, the Inverse Clarke Transformation and Inverse Park Transfor-
mation are the reverse process of the transformations discussed above. This inverse
transformations are required in the vector control theory [9] to transform the modified
two-phase rotating quantities to three-phase stationary quantities, which are inputs
to the three phase inverter.
The same theory discussed above applies to the inverse transformation theory
as well, however, we approach this in a reverse direction. Hence we take inverse of
equation 2.13 and this can be explained as:
(2.19)
^a -1 r "I
2 -1 -1
3 3 3 ^a
k _u C3 C3_ c
ic
11


ia 1 0
ib -l a/3 ia
2 2
-1 -d3
2 2
The Inverse Park Transformation can be derived from equation 2.14 as:
(2.20)
M/3 ^dq X ?
and eJe can be expressed using Eulers formula as:
(2.21)
eje = cos 9 + j sin 9
(2.22)
From the above equations, the
Matrix form as:
ia
Inverse Park Transformation can be expressed in
~ ~
cos 9 sin 9 id
sin 9 cos 9 iq
(2.23)
12


3. Vector Control Design for Machine Control
This chapter discusses about designing the controller blocks namely flux estima-
tions, current regulators and speed regulators, that have to be undergone succeeding
the transformations discussed in chapter 2. The parameters of the machine should
be identified for setting the gains of the regulators, limiting values of the limiters of
the controller, reference and feed-forwarding values to the regulator, and so on. In
general, the parameters of the machine are determined using locked rotor test or by
the no-load test. But, in actual operating conditions, these values might vary widely.
The following sections discuss briefly about the vector control system.
3.1 Measurement and Estimation of Parameters of Induction Machine
In this section, some of the methods to identify the parameters of electric machines
[10] based on the extra tests or name plate data of the machinery are introduced.
Though the method based on an extra test provides reasonably accurate parameters,
the methods may need some tools to apply the test signals or special setup for the
test. Hence, it is difficult to be used generally in the industry site.
3.1.1 Rated value of Rotor Flux Linkage,\dr
The stator voltage equation for rotor flux-oriented vector-controlled induction
machine can be written form the calculation part, as
T2 rlie T
VI = (Rs + Rr-f )4 + aLs- uoeaLxiV Rr^rAe
Li at
qs
, L2 ,. di
Vqs = (Rs + Rr~^)Rqs + cRs-
T /xdr
qs j -e Lm \e
+ a)eaLsids + urAdr
(3.1)
(3.2)
it ' Lr
Based on some approximations done at near rated operating speed with no load, the
equation 3.2 can be written as
Vqs UrXlr UeKlr (3-3)
In this mode of operation, we have V^s voltage can be approximated as V^s. Hence the rated flux can be calculated from the
13


rated voltage and rated frequency of the induction machine. This is done by simply
dividing the peak of the rated phase voltage by the rated angular frequency,Ae of the
machine.
3.1.2 Stator Transient Inductance,aLs
The stator transient inductance of the induction machine can be defined and
approximated as
aLs = LS-^ (3.4)
It is to be noted that, the transient inductance varies with the magnitude and the
frequency of the current flowing through the inductance. If the stator transient induc-
tance is not accurately measured, the torque of the machine might lead to oscillatory
response. The transient inductance can be estimated by applying a short voltage
pulse to the induction machine through a PWM inverter as shown in Fig. 3.1. The
Fig. 3.2 shows the flow of current in the circuit. In this test, the phase voltage
equation can be derived as
Vas = (Rs + Rr)ias + {Lis + Lir)r = (Rs + Rr)ias + oLs (3-5)
at at
If the width of the voltage pulse is small enough compared to the stator time constant
defined as T = R^_SR most of the voltage will be applied to the stator transient
inductance and can be approximated as
Vas = aLs(3.6)
at
Hence the transient inductance, aLs, can be estimated as
aLs
Vad
t2 ~ tl
(3.7)
14


3.1.3 Mutual Inductance, Lm
The mutual inductance of a machine can be identified easily if no-load operation
is possible for the system. In this case, by simply measuring the phase current and
the phase voltage, the sum of the stator leakage reactance and the mutual reactance
can be obtained by dividing voltage by the current. Then the mutual inductance
can be approximated by dividing the sum by the operating frequency, ue, under
the assumption that the stator leakage inductance is much smaller than the mutual
inductance. Note that the operating frequency should be near the rated value to
reduce the error due to the resistance voltage drop of the stator winding. The mutual
inductance of the machine varies according to the magnitude of the rotor flux linkage
decided by the magnitude of the d-axis current of the synchronous reference frame.
3.2 Equivalent model of Induction Machine (T-Model)
The equivalent model of the induction machine can be described by using space
vectors. Although there are many dynamic models of the machine, we use T model
defined in the stationary af3 system in this manual. The equivalent circuit in the
form of T-circuit [11] is shown in Fig. 3.1 From the circuit shown above, the stator
Figure 3.1: Equivalent T circuit of the induction motor dynamic model
15


and rotor dynamic equations can be derived as,
Vs Rsis T
dips
dt
Vr 0 Rrir T
dipr
dt
ju)rify
where the stator and rotor flux linkage equations can be written as,
(3.8)
(3.9)
rtf)s Lisis Lmir (3.10)
Vv Lirir + (3.11)
The torque equation can be derived finally as,
3 l ^ ^
Te = x P x ~p- x Imagitjjl is) (3-12)
z Jjr
The quantities used in the induction motor are listed below.
Vs = Vsa + jVsfi : Stator voltage Rs : Stator resistance
Vr = Vra + jVrp : Rotor voltage Rr : Rotor resistance
is = isa + jisfi ' Stator current Ls : Stator inductance
ir = ira + jirfj : Rotor current Lr : Rotor inductance
im = is + jir ' Magnetizing current Lm : Mutual inductance
V = + j'V's/3 : Stator flux linkage Lis ' Stator leakage inductance
Vv = ipra + jVV/3 : Rotor flux linkage Lir : Rotor leakage inductance
ojr : Electrical rotor angular speed P : Pole pairs
Te : Torque
3.3 Current Regulator
The main parts of the current regulator are PI regulator [12], feed forward and
anti-windup. The Fig. 3.2 shows the complete structure of a current regulator. The
input signals for the current regulator are:
is,ref, calculated from the reference value of the torque and the rotor flux.
16


Figure 3.2: Overview of Current Regulator
is, the stator current in clq- coordinates, which is obtained from the transfor-
mations of the measured phase currents.
The electrical rotor angular speed, ur which is obtained by multiplying the
number of pole pairs with the mechanical rotor angular speed.
The angular speed and the magnitude of the rotor flux, which are calculated by
the flux estimator.
The output signal from the current regulator is:
Stator voltage saturated by the voltage limiter. This limited voltage is then
transformed using Inverse Clarke and Park and then taken to the inverter and
then is applied to the induction machine as three-phase voltages.
17


3.3.1 Current Reference
The current reference term can be derived from the rotor side equation in the
equivalent circuit as,
o = Rritd+inPZd-{u-UfWZq (3-13)
where p is the differential term. Since the term ^ = 0, the equation above can be
written as
p4>\
rd
f> 7e
1 tr
76
6rd
tPrd Lmisd
Lr
(3.14)
(3.15)
Using both the above two equations and considering a single-order delay system i.e.
p = 0, the final expression would be,
i
e
sd
4ri
(3.16)
3.3.2 Feed Forward
From the dynamic equation of the stator currents in the T-model, we have
Ll
dien
Vq% = (Rs + Rr^)iega + (TLs^- + UJeuLsieds +
Lr
dt
Ln
11.
(3.17)
It could be found that the last term and last but one term need to be removed in
order to get a linear relation between voltage and the current. The first term in the
relation is usually known as the resistive voltage drop and the second term in the
relation is known as the inductive voltage drop. The existence of the third term in
the relation introduces the cross-coupling between d and q components. Also the
fourth term comprises of back-emf turns. Since the coupling and back- emf turns are
not expected during the current regulator design, a feed forward signal is applied to
eliminate the two terms and it is shown in the Fig.3.2
18


3.3.3 Voltage Limiter
As we know based on the principle of the three-phase inverter and PWM, the
amplitude of the equivalent sinusoidal voltage applied to the machine should be lim-
ited to the half of the DC-link voltage. This limitation of the voltage can be done by
using voltage limiter. This can be seen in the Fig. 3.2 It should also be noted that
the amplitude of the modulation voltage is expected to be smaller than the half of the
DC-link voltage because he inverter will output a constant voltage if the magnitude
of the modulation voltage is larger than half DC-link voltage. In this project, as
the DC-link voltage is 48V, the peak value of the phase voltage is set to be within
+20V or -20V. Even after you transform the DC vectors to three-phase sinusoidal
quantities, the peak value of the three-phase quantity remain the same and will never
change. This is why we set the voltage limiter in a current controller.
3.3.4 Anti-windup
There are some instances where, the output voltage of the current regulator may
not reach the value which is needed due to the existence of the voltage limiter. Then
the current error between the reference current and the feedback might let the inte-
grator of the PI regulator integrate to a very large value. Even if the error is finally
reduced, it would still take long time for the integrator to come to normal value,
which gives a delay [13] in the signal. This phenomenon is called integrator windup
problem. In order to overcome this situation, the difference between the voltage val-
ues before and after the voltage limiters fed back to the integrator through some gain
which makes the integrator reset [14] every time and eliminates the integrator windup
problem.
3.4 Flux Estimator
There are two types of flux estimators, voltage model estimator current model
estimator. The structure of an example flux estimator can be seen in Fig. 3.3. The
19


Figure 3.3: Structure of Flux estimator
current model estimator, is more suitable for low speed application despite of sensitiv-
ity to parameter variations [15] rather than the voltage model estimator. As a result,
the flux estimator used in this project is the current model estimator implemented
in Indirect Field Orientation, which indicates that the quantities used for the flux
estimation are currents taken from the d q system. With the stator d and q currents
and the electrical rotor angular speed as inputs, the flux determination equations for
the estimator can be derived as,
d^ = Rmd-^R (3.18)
dt Lm
o = Rdq (uJl UJr)^R (3.19)
where uq ur is the difference speed between the synchronous speed and the electri-
cal rotor speed, the slip frequency. The Fig.3.3 illustrates the structure of the flux
estimator.
20


3.5 Speed Regulator
Figure 3.4: Speed control Regulator
The dynamic equation of the mechanical part of the induction motor can be
expressed as
dur B Te- Tl
Â¥-_7' + xr
(3.20)
where
ojr : The mechanical angular speed
Te : Torque of the motor
Tl : Load torque
B : Friction coefficient
J : Motor Inertia
The speed regulator design is very similar to the current regulator design. Like in
current regulator design, the speed regulator also has the anti-windup setup. But
this regulator does not have any feed forward terms but has the current limiter alike
voltage limiter in current control regulator. The current limiter has the peak value
21


of the rated current of the machine since the machine operating current should not
exceed the rated machine current. To avoid large overshoots in the speed response,
anti-windup is added. The structure of the speed regulator is shown in Fig. 3.4
The speed regulator has the output of torque reference which can be converted to
q-current, which acts on the motor immediately and directly. Since the inner current
loop has a very high bandwidth, the speed loop should have smaller bandwidth.
3.6 Simulation
The designated vector control system is implemented or simulated in Mat-
lab/Simulink. The block diagram of the vector control design is same as the figure
shown before and the structures of sub-blocks of the current regulator, flux estimator
and speed regulator are almost the same as shown in the previous figures. But some-
times in Simulink, the integrator block as well as the limiter block does not accept
the complex values. Therefore, the complex number is split into real and imaginary
part, which are then dealt separately. This process is illustrated in the Fig. 3.5 For
inp-ut
I m
C smp 1st tc-
ResJ-lmag
m*


Real-1 mag to
Complex
Jbtpyt
Figure 3.5: Integral of the complex number in Simulink
the limiter, the complex number is expressed in polar form, and then the magnitude
of the limiter is saturated as shown in Fig. 3.6 In the entire stages of simulation,
the whole vector control system is built with Simulink blocks. The advantages of
building the model with Simulink blocks is that it is very easy to observe a variable
22


Figure 3.6: Saturation of the complex number in simulink
by adding a scope wherever it is needed. Moreover, it is more flexible to modify the
system structure.
3.7 Discretization
All the design above is based on continuous time. But the DSP does not allow
to execute the continuous time varying signals. Therefore, the signals of each block
have to be discretized for the proper execution of DSP. For example, if the control
loop period is 0.1msec, the sampling period h for the discretized system is selected as
0.1msec. At a certain time instant t = kh, in one cycle of the control loop sampling
takes place firstly, then the sampled values at t = kh are passed down in to the
function block chain. Then each block takes its input signals and stored state variables
into calculation, derives its output to feed into the next block and then get its state
variable updated for the next iteration at time instant t = (k + l)h.
In this project, Forward Euler approximation is used to transform the continuous
system into discrete system. With x(t) defined as a continuous variable, x(kh) as its
value at the current time instant and x[{k + 1 )h\ for the next time instant, as shown
in Fig. 3.7 the derivatives can be approximated with a forward difference as [13]
dx(t) x[(k + 1 )h\ x(kh)
dt h
3.21
23


Figure 3.7: Forward Euler approximation
Figure 3.8: Integral form of Forward Euler approximation
The integral form of Forward Euler approximation is shown in Fig. 3.8, where the
area below the curve x(t) can be approximated to the integral of variable x, denoted
as X. Over the interval between kh and (k + 1 )h, the area below the curve of x(t) is
approximated to the area of the rectangle with x(kh) and h as dimension of it. The
24


integral of x(t) can be calculated as, by using the Forward Euler approximation,
X[{k + l)h\ = X[kh\ + hx[kh] (3.22)
All the equations which are continuous time varying signals are presented in integral
form using Forward Euler approximation. For the blocks containing dynamic parts
like integrals, the above equation should be used into the original equations to replace
the integrals to make it a completely discrete system.
25


4. DSP Programming and CCS V5.5
The integrated interface for any user developing code in C language in this project
is the Code Composer Studio v5.5. Code Composer Studio (CCS) [16] is the Inte-
grated Development Environment (IDE) for TIs microcontrollers. TI also has an
integrated solution called the Control SUITE [17] which consists of all the header
hies, source hies, libraries, linker command hies for executing a program. Also the
Code Composer Studio has many extensive examples and example codes that might
help any new user for a quick start of developing code.
The design of induction motor vector control is shown in Fig. 4.1. There are some
modihcations and assumptions, however, in the actual design, during the implemen-
tation. Some of the modihcations are hrstly, only two phase currents are measured
instead of all the three phases. It is sufficient to take the measurements of two phases
for the Clarke Transformation, if the three phase currents are balanced with the con-
dition of ia{t) + ib(t) + ic{t) = 0 [18]. If three phases are balanced, one phase can be
calculated from the other two phases. At the start if the testing, hrst, V/F control
is implemented in order to test the motor functionality and the Simulink [19] blocks.
The how chart of the various steps that the DSP undergoes after implementing the
code is shown in Fig. 4.2. The program, as shown in figure, starts with variables dec-
larations, initializations and configuration of the used hardware in the DSP, start-up
of the inverter and offset measurement. The latter process is in the implementation
in the hardware but the starting process depends on the software. After the DSP
is configures, the PWM sequence is started and the program enters in to loop. In
this project, the control strategy is designed such that, the control loop is synchro-
nized with the PWM carrier wave. Every start of PWM period will trigger an ADC
sequence. The ADC sequence consists of eight channels, which are used to measure
phase currents, fault currents and fault voltages and DC link voltages. At the end
of ADC sequence, the program jumps into measuring the current and speed values,
26


Figure 4.1: Programming Design
where the offset compensation is added. Following the measurement calculations, the
vector control algorithm is executed. Finally, the PWM duty cycles are updated with
the new calculated values and the program then waits for the next trigger from the
PWM. In the following sections, brief introduction to the F28335 DSP is given and
also description about the hardware modules are given. In this section, introduction
to the DSP F28335 is briefly studied, followed by the modules description and also the
features of DSP. The PWM module plays an important role in this project because
of its functioning to output the three-phase signals to the inverter, decide the control
loop period and to synchronize the ADC. This is the reason why more details are
given in PWM module in this document.
4.1 Overview of DSP
Coming to the peripherals of the DSP, the F28335 DSP consists of a 32-bit CPU
and a single-precision 32-bit floating-point unit (FPU), which enables the floating-
point computation to be performed in the hardware. Also the CPU of the F28335
has a 8-stage pipeline structure, which makes the CPU be able to execute eight
27


Figure 4.2: Flow chart of the program
instructions simultaneously on one system clock period. The 150MFlz system clock is
provided by an on-chip oscillator and a phase-locked loop (PLL) circuit. The oscillator
generates 50MFlz clock signal, which is tripled to 150 MHz by the PLL circuit. The
F28335 has independent logical memory spaces and separated memory buses for the
program and the data as seen in Fig. 4.3. The memory bus consists of a program read
bus, a data read bus and data write bus. The physical memory of the F28335 consists
of 34Kxl6 single-access random access memory (SARAM), a 256K xl6 Flash, an 8K
x 16 read-only memory (ROM), a IK x 16 one-time programmable memory (OTP)
28


and the registers. The ROM has been pre-programmed by the DSP manufacturer.
The program existing in the ROM has a standard programming procedure for DSP
booting as well as some optimized codes for the mathematical functions. The registers
control the behavior of the DSP and each peripheral module. For the F28335, reading
from or writing to registers applies the bit-held address structures. F28335 also has
the feature of direct memory access (DMA). With the DMA bus, the data can be
passed from one part of the DSP to the other part without the interaction of the
CPU, which increases the data transmission speed. Since it is designed mainly for
applications like ours, the F28335 has plenty of peripheral circuits. For instance,
in our project, the motor vector control uses 16-channel, 12-bit ADC module, the
PWM module and the encoder module. Also there are different communications that
could be achieved with the F28335, which are controller area network (CAN) module,
the serial communication interface (SCI) module, the serial peripheral interface (SPI),
the multichannel buffered serial port (McBSP) module and the inter-integrated circuit
(I2C) module. F28335, also, supports 96 interrupts. These interrupts are governed by
the peripheral interrupt expansion (PIE) block, which helps in enabling or disabling
the interrupts, decide the interrupt priorities and inform the CPU of the occurrence of
a new interrupt. The F28335 has the joint test action group (JTAG) interface, which
helps us in real-time debugging. With the help of this JTAG, anyone can look and
modify the contents of the memory and the registers without stopping the processor.
This section explains about different modules.
4.1.1 ADC Module
The block diagram for ADC module [20] configured in F28335 is shown in Fig. 4.9.
It consists of 16 analog input channels, which are connected to an analog multiplexer
(MUX). The channel to be sampled can be selected by sending its corresponding 4-
bit address to the MUX. The relations between the channels and the 4-bit addresses
are listed in Table. 4.1. From the Fig. 4.9, we can observe that the analog MUX
29


Figure 4.3: Block diagram of ADC module [1]
consists of two 8-to-l multiplexers, MUX1 and MUX2. The outputs from the two
multiplexers are connected to two sample and hold (S/H) circuits, S/H-A and S/H-B,
respectively. The two S/H circuits allow the possibility of sampling two analog signal
simultaneously. After the S/H circuit has done the sampling, the analog-to-digital
converter begins to transfer the analog signal held on the S/H circuit into a 12-bit
binary number. The entire functioning of the ADC is governed by the ADC control
registers. There are sequencer blocks in the ADC, Sequencerl and Sequencer2. These
two sequencers are then merged into a cascaded sequencer, where maximum sixteen
channels can be selected. These two sequencers are placed in an appropriate order and
each sequencer maximum of eight channels can be selected. In order to start an ADC
sequence, a start-of-conversion (SOC) signal is needed. For sequencerl and sequencer2
or cascaded sequencer, the SOC signal could be given by the PWM module or the
bit S/W, which can be set or reset in the software. Sequencerl and the cascaded
sequencer could also be triggered by an external signal through a general-purpose
30


Table 4.1: ADC input channels and corresponding addresses
Input Channel Address S&SiSo Input Channel Address S&SiSo
ADC INAO 0000b ADC INB0 1000b
ADC INAl 0001b ADC INB1 1001b
ADC INA2 0010b ADC INB2 1010b
ADC INA3 0011b ADC INB3 1011b
ADC INA4 0100b ADC INB4 1100b
ADC INA5 0101b ADC INB5 1101b
ADC INA6 0110b ADC INB6 1110b
ADC INA7 0111b ADC INB7 1111b
input/output (GPIO) pin. The ADC clock frequency decides the time to take for one
conversion. The ADC clock is obtained by prescaling the system clock. This is done
in default if you set the DSP as F28335. The total prescaling factor is equal to the
product of the prescaling factors of the high-speed prescalar, the ADC clock prescalar
and the extra prescalar. The conversion results will be will be written into the result
registers, through a result selection MUX. For each sequence, the result selection
MUX will send the first conversion result to Result RegO, the second one to Result
Regl and so on, until this sequence is finished. Whenever the complex conversions
occur like analog-to-digital conversions are needed in two different moments during
one control, the dual-sequence mode can be applied. In this project, all the analog
signals are sampled at the same moment and the number of analog signals is less
than eight. Due to this, one sequence of conversion per control loop is enough. But
cascaded mode of operation is still applied, which can leave flexibility to the channels
and DSP pins assignment. Sometimes it is required that all the analog signals are
31


ccw
12.5MHz
Figure 4.4: ADC module configuration setup in this project [1]
sampled at exactly when the PWM carrier wave reaches its peak. But since there
are only two S/H circuits, in the practical implementation, the two phase currents
phase A and phase B are sampled firstly and then the other parameters are sampled.
The sampling mode of the ADC module should be simultaneous. The ADC clock
frequency is better to be high, from the point of conversion speed. But too high ADC
clock frequency might cause some non-linearity to the conversion results [21]. So
12.5MHz, the highest ADC clock frequency is recommended and is being set in this
project. Another issue that might be noticed is the width of the sampling window,
which is defined as the number of clocks that the S/H circuit spends on sampling the
signal. For the signals that change very slowly, a wider sampling window might work
perfect bringing the advantage of removing the noise by averaging the input signal.
But in this project, since the currents change very fast, wide sampling does not
32


work, instead smallest sampling window of one ADC clock is applied. Then the ADC
module should work in start/stop mode, which means that the conversion is started
by the SOC signal and stops when the sequence is finished, waiting for the next SOC
signal. The SOC signal is triggered by the PWM module. Finally, an interrupt service
routine has to be generated by the ADC, once the sequence is finished. The vector
control algorithm will be executed in the Interrupt Service Routines (ISR). The block
diagram based on the ADC module configurations described above in the theory is
shown in Fig. 4.10. In simultaneous sampling mode, a pair of conversions counts for
one. Also the ADC counts from 0 instead of 1, so the value of the MAXConv should
be calculated as
,, , r No.o f Conversions. . .
MAXconv = [-----------^ 1 (4-1)
This section explains about PWM module.
4.1.2 PWM module
There are six independent enhanced PWM (ePWM) modules in the DSP. The
enhanced PWM means that it can generate complex PWM waveform with the least
CPU resources occupied [22], Each of the ePWM module has two output channels:
ePWMxA and ePWMxB belonging to the ePWMx module. Each ePWM module
contains seven submodules, which can realize different functions in the generation
of PWM waveforms. They are time-base (TB) submodule, counter-compare (CC)
submodule, action-qualifier (AQ) submodule, dead-band (DB) submodule, PWM-
chopper (PC) submodule, trip zone (TZ) submodule and event-trigger (ET) submod-
ule. The Fig. 4.4 shows the complete structure of a single ePWM module with each
submodule between the subsections. In this project, not all but some of them are
used for various accomplishments. The following sections will briefly describe the
ePWM modules individually to get a clear idea of how the ePWM functions.
33


Figure 4.5: Block Diagram of F28335 [2]
4.1.2.1 Time-base submodule
The function of time-base module is to take charge of the event timing for its
own ePWM module. The structure and block diagram of the time-base submodule
containing registers is shown in Fig. 4.4. The main function of the time-base sub-
module is to find the PWM time-base block relative to the system clock. The PWM
time-base clock is to regulate the timing of all the events in the PWM module. The
system clock period is defined as Tsysclkout and the time-base clock is defined as
Ttbclk The time-base clock period can be scaled to many times of the system clock
34


period as:
Ttbclk = Tsysclkout x CLKDIV x HSPCLKDIV (4.2)
where CLKDIV and HSPCLKDIV are bits in the time-base control register
(TBCTL) that helps to set the time-base clock pre-scale.
The time-base submodule is also used to specify the period of the time-base
counter (TBCTR) depending in which mode it is operating. There are three modes
of operation for the time-base submodule, which can be selected in time-base control
register (TBCTL), namely up-count mode, down-count mode and up-down mode. In
the first mode and the second mode, TBCTR always keep incrementing or decre-
menting all the time giving a saw tooth carrier wave. But the third one i.e. up-down
mode, the TBCTR increments in the first half of the PWM period and then decre-
ments the second half part of the PWM period giving a triangular carrier wave. The
main difference of the up-down mode is that in one period the counter changes in a
symmetrical fashion, where the corresponding movement to the PWM carrier peak
time is easily found. The peak time of the PWM carrier wave has to be known for
signal sampling and that is the reason why up-down mode count mode is used in this
project. To obtain the desired PWM frequency, the value in time-base period regis-
ter (TBPRD) is supposed to be determined. For up-down-count mode, the relation
between time-base period and PWM frequency can be written as:
Tpwm 2 x TBPRD x TTBClk (4.3)
fpwM = tv------ (4.4)
J-PWM
where Tpwm stands for PWM period and Ttbclk for time-base clock period. From
the above relations, the value in the time-base period register can be determined as
follows
TBPRD
1 fsYSCLKOUT
2 X Jpwm X CLKDIV x HSPCLKDIV
(4.5)
35


Therefore the only parameters that have be known to compute TBPRD are DSP
system clock frequency and the desired PWM frequency. The parameters that have
been used in this project for the configuration of DSP are PWM frequency of 10
kHz and the system clock frequency of the DSP F28335 is 150MHz. The values for
CLKDIV and HSPLCLKDIV, used in this project are 1 and 1 for convenience. From
the above equation, the value set in the time-base period register can be calculated
directly as shown below.
TBPRD = x = 7500 (4.6)
2 lOhlxl v '
Besides, synchronization between different ePWM modules can also be realized in
the time-base submodules. The three-phase PWM is used to produce a three-phase
alternating voltage, hence the synchronization between the three-phase PWM signals
is very important. Each ePWM module has two signal for synchronization between
different ePWM modules. One is synchronization input EPWMxSYNCI and second
is synchronization output EPWMxSYNCO. The Fig. 4.5 shows time-base counter
synchronization scheme for F28335. It can be seen that the PWM modules are con-
nected in series with the synchronization output EPWMxSYNCO of the previous
one fed onto the synchronization input EPWMxSYNCI of the next one. Only the
input synchronization for the first ePWM module is taken from an external pin.
For each ePWMmodule, once apulse from the synchronization input is detected, the
value in the time-base phase register (TBPHS) will be loaded into time-base counter
(TBCTR), where time-base phase register (TBPHS) will be loaded into time-base
register (TBPHS) is used to store the time-base counter (TBCTR) phase value of the
ePWM module with respect to the time-base of its synchronization input signal. As
we know that the inverter output are three phase voltages which are leading or lagging
each other by 120, this is not going to show up in the project i.e. the three PWM sig-
nals have the same phase at any moment. The ePWM module ePWMl, ePWM2 and
ePWM3 are selected for the three-phase PWM generation. Hence the time-base phase
36


Figure 4.6: Internal modules of ePWM and their connections [3]
register (TBPHS) for the ePWM modules are assigned the value of 0. It means that
there is no phase shift between the output signal ePWMlA, ePWM2A and ePWM3A.
To synchronize between different ePWM modules, the synchronization output select
bit (SYNCOSEL) in the time base control register (TBCTL) is supposed to be con-
figured. ePWMl is defined as the master phase to generate a synchronization output
EPWM1SYNCO pulse each time its time-base counter (TBCTR) equals zero, while
ePWM2 is defined as a slave phase whose synchronization input EPWM2SYNCI
signal is enabled. Meanwhile, ePWM2s synchronization output EPWM2SYNCO sig-
37


U'!U
MJX
Figure 4.7: Time base counter synchronization scheme for F28335
nal is set equal to its synchronization input EPWM2SYNCi signal to drive it into
ePWM3 unit. Except ePWMl, the other modules ePWM2 and ePWM3 have to load
the time-base counter (TBCTR) with the time-base phase register (TBPF1S) when a
synchronization input EPWMxSYNCI pulse appears.
4.1.2.2 Counter-compare submodule
More practically approaching the things, the PWM waveform generation is mainly
achieved by the comparison between a counter (TBCTR) value (carrier wave) and a
set-point (reference wave) which is stored in counter-compare register. Fig. 4.6 shows
the way to generate a PWM waveform. In the PWM waveform generation process, the
counter-compare submodule (CC) takes the part of event generation, while the action
qualifier takes action on other things. In counter-compare submodule, there are two
counter-compare registers: counter-compare A register (CMPA) and the counter-
compare B register (CMPB) to store the values which are used to compare values
against time-base counter (TBCTR) submodule continuously. The time-base counter
(TBCTR) is treated as the input while the generated event TBCTR = CMPA or
TBCTR = CMPB is the expected output. The Fig. 4.6 show the way it is done
38


in this project. Whenever the carrier wave hits the counter-compare (CMPA) value
on the rise, the ePWMxA is set to off and whenever the carrier ePWMxA hits the
counter-compare (CMPA) value on the down-count, ePWMxA is set to on. This
process is explained in action qualifier submodule.
Figure 4.8: Counter-compare event, up-down counter mode
4.1.2.3 Action Qualifier submodule
The action qualifier submodule takes action whenever the generated events from
the previous submodules are available. The previous submodules that have to gener-
ate events are time-base submodule and counter-compare submodule and hence these
two submodule events are the inputs to the action qualifier submodule. The first one
generates event TBCTR = 0 and TBCTR = TBPRD while the second one produces
TBCTR = CMPA and TBCTR = CMPB. Having time-base counter (TBCTR) state
incrementing or decrementing, the four events are expanded into eight event combi-
nations. When a specified event takes place out of the eight events, there are four
possible actions to be triggered whether to set it high, to low, to toggle and to do
nothing, which can determine the shape of the PWM waveform. The action qualifier
39


output control register (AQCTLA) is used to define the actions that should be taken
if specified events occur. The conditions that are selected in this project to be con-
figured such that when TBCTR = CMPA and TBCTR is decrementing, ePWMxA
is set to high; while TBCTR is incrementing, ePWMxA is cleared low. The arrows
in the figure shows the direction of time-base counter.
4.1.2.4 Deadband submodule
By now we have the ePWMxA signal generated by the action qualifier submodule.
We also require a complimentary signal which is required to feed both the upper and
lower IGBTs in the same leg of the inverter. The dead band submodule can be used
to take the ePWMxA as the signal source and then to produce the two mutually
complimentary PWM outputs as ePWMxA and ePWMxB. The structure of dead-
band submodule is shown in Fig. 4.7. The function of dead band submodule depends
on the six switches present in it. Different combinations of the switches generate
different modes for signal pairs. Since there are six switches, many combinations can
be produced. But in this project, we dont use many of them. The reason behind
inserting the dead band into the ideal PWM waveform is to avoid the two IGBTs
on the same bridge leg of the inverter turned on simultaneously. Therefore operating
mode Active High Complementary (AHC) is selected as the desired one for a pair of
power switches in one phase of a 3-phase motor control system, which can be achieved
by setting the states of the switches in Fig. 4.7, which can be configured in dead band
control register (DBCTL). In Fig. 4.7, a rising edges delay block and a falling edges
delay block are used to insert a rising edge delay or a falling edge delay into the
original PWM output. With the switch S4 and S5 set to 0, ePWMxA is chosen as the
input source for both output A and B. By setting switch S2 to 0 and SI to 1, a rising
edge delay is inserted into the original ePWMxA signal; by setting switch S3 and SO
to 1, ePWMxA signal is reversed with a falling edge delay added, which is output as
ePWMxB signal. The generated PWM signal in Active High Complimentary mode is
40


ffWMvVIN
Figure 4.9: Block diagram of ePWM dead band submodule
shown in Fig. 4.8. It can be observed that there is an extremely short period of each
PWM period, when both outputs of the ePWMx module are cleared, which avoids
the mutually complimentary PWM signals are set high at the same time.
4.1.2.5 Event Trigger submodule
The occurrence of events of ADC and PWM should be such that the PWM
output should trigger the ADC start of conversion. But sometimes in a sampling
period, the ADC start of conversion is executed first, then the sampled data is used
to calculate the PWM output. This shouldnt happen which might return in wrong
results. Therefore ADC and PWM signals should be synchronized to function in the
same pace. The event trigger submodule in ePWM is to issue interrupt request or
ADC conversion after receiving event inputs. In order to avoid aliasing from current
ripple, the carrier wave peaks are always chosen as the sampling time instants. Both
TBCTR = 0 and TBCTR = TBPRD can meet this requirement and sampling. In
this project, TBCTR = 0 is defined as the event that triggers ADC start of conversion
A by EPWMxSOCA pulse. It is not required to sample at both at TBCTR = 0 and
41


Original
ePWMxA
Rising ftjgg
Delayed
(RED)
Falling Edge
Delayed
(FED)
Active High
Complemenlarv
(AHC)
Period
RKD
FED
Figure 4.10: Waveform of PWM with dead band inserted
TBCTR = TBPRD.
4.1.2.6 Duty cycle calculation
The most important part of the PWM generation is the duty cycle. The value
entered in the counter-compare register corresponds to the duty cycle of the PWM
period. So the counter-compare event register (CMPA) needs to be updated once in
each PWM period to generate the PWM wave with varying duty cycle. The relation
between the values set in CMPA register and PWM duty cycle can be written as:
CMPA = TBPRD x (1 D) (4.7)
All the submodule roles are introduced in previous sections. The specific output value
of the inverter should be equal to the digital signal given by the DSP, at any point
of time. For instance, let us take an extreme situation case, phase A. The output
voltage for phase A is controlled by switch SI and S4 and the PWM signals imposed
on Si and S4 are mutually complimentary. The Vdc is defined as the DC link voltage
42


for the inverter. During a sampling period of the PWM, the switch SI is turned on
and switch S4 is turned off for the same period. It also can be said in this way that,
the duty cycle of the PWM wave fed to switch SI is 100 percent, the output voltage
of phase A should be +Vdc/2; on the other side, if the switch stays off and switch S4
is turned on for the whole cycle, the duty cycle for switch SI is 0 percent, the output
voltage of phase A turns to be Vdc/2. And if both the switches are on for one half
of the cycle period, the average voltage of phase A is supposed to be 0. From the
principle of PWM, as the carrier wave of the modulation is triangular wave, from the
basic geometrical knowledge it can be found that the relation between the output
phase voltage from the inverter and the corresponding PWM duty cycle is linear. In
general, if the PWM duty cycle stands at any one point in the range from 0 to 1, the
output voltage for phase A, can be written as:
K = (ifb x £> + x (1 Da) (4.8)
where Da is denoted as the duty cycle for the upper IGBT of the bridge leg connected
to phase A. Prom the above relation, the duty cycle can be written as
D
a

(4.9)
The complimentary PWM waveform ePWMxB for the lower IGBT on the bridge leg
can be generated by reversing ePWMxA in the dead band submodule. Hence only one
counter-compare register (CMPA) is required for the generation of one pair of PWM
outputs on the same bridge leg. From the above relations, the value set in CMPA
can be easily calculated. This process applies to other two phases. As a result, the
duty cycles for three phases can be derived as
CMPAa = TBPRDa(0.5 Pic (4.10)
CMPAb = TBPRDb{0.5 ) Vdc (4.11)
43


CMPAC = TBPRDC(0.5 -
Vdc
(4.12)
The subscript implies the phase that the register values belong to.
4.1.3 Encoder Module
The enhanced quadrature encoder pulse (eQEP) module [23] of the F28335 is
used to process the digital signal form the encoder built on top of the motor. There
are four different modes in which the quadrature module is able to run. They are
quadrature mode, direct count mode, up count and down count mode. In quadrature
mode, the eQEP module receives two square wave signals from the encoder. These
two square wave signals (A and B) have 90 phase shift with respect to each other,
which can be used to determine the rotation direction. If square wave A is leading
with respect to square wave B, then the rotation is said to be in clockwise direction
and on the other side, if the square B is leading with respect to square wave A,
then the rotation is said to be in anti-clockwise direction. In direction-count mode,
one square wave signal and one direction signal are sent to the eQEP module. The
counter in the module will increase or decrease depending on the direction. For both
modes, an index pulse signal is used to determine the absolute position of the encoder.
The operating mode of the eQEP module is selected by the type of encoder. As the
incremental encoder is used in this project outputs the quadrature signals, the eQEP
module is set to be working in quadrature-count mode. The general block diagram
of eQEP module is shown in Fig. 4.11 which shows the functionality of the encoder.
Two quadrature waves are sent to the QA pin and QB pin of the decoder block
as shown in the Fig. 4.11. Every falling or rising edge of QA and QB will generate
a clock signal (QCLK), which is passed to the position counter (QPOSCNT) from
the decoder. The QPOSCNT will increase or decrease by 1 unit on each pulse of
QCLK, depending on the direction signal (QDIR). If the rotation is clockwise, the
QPOSCNT will increase by 1 unit for every pulse. If the rotation is anti-clockwise,
the QPOSCNT will decrease by 1 unit for every pulse. The following Table 4.2 show
44


Figure 4.11: Block diagram of eQEP module [4]
the details of the values of QDIR and QPOSCNT. Fig. 4.12 shows the example
waveform of the eQEP, which has the quadrature QA and QB pins, index pulses.
Every time the position counter (QPOSCNT) is reset by the index signal. When it
meets the index signal for the first time, the eQEP module will remember the present
edge and the rotating direction in the first index marker register.
For instance, if the first counter reset happens on the falling edge of QB during
the clockwise direction, then all the later results must be aligned with the falling edge
of QB for the clockwise direction and with the rising edge of QB for the anti-clockwise
direction. The position counter can be reset by the overflow or underflow of itself.
For underflow the limiting value is zero. For the overflow, the upper limiting value
is QPOSMAX, which is the value stored in the QPOSMAX register. This value is
set in the eQEP module in the project. If you do not set the underflow or overflow,
the counter is automatically reset to 0 during the clockwise rotation and reset to
QPOSMAX during the anti-clockwise rotation. If the period of the vector control
loop is set to t, then the rotating speed of the encoder can be calculated as
Speed
x 60rpm
(4.13)
45


Table 4.2: Encoder Truth table
Previous Edge Present Edge QDIR QPOSCNT
QAt QBt 1 increment
QBt 0 decrement
QAt TOGGLE increment or decrement
qa; QBt 1 increment
QBt 0 decrement
QAt TOGGLE increment or decrement
QBt QAt 1 increment
QAt 0 decrement
QBt TOGGLE increment or decrement
QBt QAt 1 increment
QAt 0 decrement
QBt TOGGLE increment or decrement
This condition applies if the encoder rotates one revolution during one control loop
period.
4.1.4 Offset Measurement
Generally, both the current and speed measurements contain a small offset, which
is due to the presence of sensors or the ADC conditioning circuit. These offset of either
the currents or the speed should be measured when the machine is in standstill mode
with all the other modules or devices switched on. The measured offset current from
the three phases should be subtracted from the ADC results in the code to compensate
for the current offset. In order to get the samples of current offset, the DSP is allowed
to settle for some time, allow DSP to run in steady state and then the offset can be
sent to the oscilloscope or can be measured by taking many sample per second and
taking average of them. The speed offset can be done using the same way as the
current offset.
4.2 Hardware Setup
An experimental setup is designed in the Energy and Power lab in order to im-
plement the simulink code on to the DSP. Fig 4.13 shows the setup that has been
46


Figure 4.12: An example waveform of the eQEP (anti-clockwise rotation)
used for the project. The idea of the setup is to have all the equipment namely power
supplies, inverter, DSP board, transformers and the motor on the same platform.
The setup has access to limited input ports and output ports which are used in this
project. There are two switching power supplies in the setup out of which, one acts
Figure 4.13: Plarware Setup in the lab
as the input source for inverter (48V DC) and the other acts as input source for DSK
board (24V DC). Since the input voltage for the inverter is 48V DC the maximum
47


voltage that can be obtained from the inverter is 24V (Vdc/2). The output of the
inverter is then boosted up to 240V using three boost tansformers. The transformer
connections are delta-delta connected. The PWM signals generated digitally and the
analog values in the DSK are sent to the inverter using bus cables as shown in the fig.
4.13. The DSP is emulated using USB JTAG emulator through which, the program
in the computer is sent to the DSP. The DAC pins at the bottom of the figure are
used to receive output signals such as voltages, currents and speed. A serial Commu-
nications interface is setup and connected to computer which enables the serial (one
bit at a time) exchange of data between the DSP and the computer.
4.3 System Initialization and Configuration of CCS V5.5
4.3.1 Initialization
After switching the power supply on, the DSP has to be initialized. The already
installed control SUITE supports any user with initialization functions corresponding
to each function unit. The initialization functions only provide the most basic sup-
ports for running the system, for example to initialize the system clock or to enable
some modules.
4.3.2 Configuration
The modules present in the design can run in different modes depending on the
application. But for this project, to run our application, the module units are con-
figured to suitable operating mode as shown in below sections. Each module is taken
individually and both the C code and the Simulink code are presented to illustrate
the difference in configuration setting. The tables 4.3, 4.4 and 4.5 shows the configu-
rations set in this project in each module.
48


Table 4.3: Configuration of ADC
ADC Clock 12.5MHz
Sampling mode Simultaneous
Operating Mode Start/Stop
No. of Conversions 8
Sampling mode 1 ADC Clock
Sequence mode Cascaded
Trigger Source PWM
Interrupt Post Sequence
5k Source Block Parameters: ADO
C280x/C233x ADC (mask) (link)
Configures the ADC to output a constant stream of data collected
from the ADC pws on the C28ta/C2833x DSP,
AOC Control Input Channels
Module: A
Conversion mode: Sequential
Start of comerson: ePWMxA
Sample time:
o.oooi
Datatype: umtl6
M Post interrupt at the end of converson
5k Source Block Parameters: ADO
C280x/C2833x ADC (mask) (hnk>
Configures the ADC to output a constant stream of data codected
from the ADC pms on the C2S0x/CZ833k DSP.
ADC Control Input Channels
Number of conversions: a
Coraverswn no
Conversion no
Converwm no
Conversion no
Conversion no
Conversion r>o
Conversion r>o
Converaan no
1 ADC3NA0
2 ADCINA1
3 ADONA2
4 ADC1NA3
5 ADC3NA4
6 ADONA5
7 ADQNA6
B ADCINA7
@ Use nvulbple output ports
Apply
(a)
(b)
Figure 4.14: Simulink code configuration for ADC
Table 4.4: eQEP configuration
Maximum position counter value 4294967295
Positive Rotation Clockwise Rotation
Positive counter mode Quadrature-count
Gating option On Index pulse
Position counter reset mode On maximum value


Source Block Parameters: eQEP3
C2SxQCP(mfc)(Mc)
The enhanced quadrature encoder pulse (eQCP) module is used for deed
interface vwth a Inear or rotary incremental encoder lo get posfeon, drecbon,
and speed informs bon from e rotating machine for use in a high-performance
motion and postton-control system.
The tQEP inputs mdude two pm$ for quadrature-dock mode or direction-coon*
mode, an index {or 0 mrfcer), and a strobe input
General Position counter Speed calculation Compare output [ w
Module: eQEPl ________^
Fosftmn counter mode: Quadrature-count *
Posen* rotation: Clockwise _____________________
O Quadrature direction flag output port
O Inert input QEPkA polarity
O Invert input QEPxS polarity
D Invert input QCPxl polarity
O Invert input QCPicS polarity
33 Index pulse gatmg option
Sample time:
Zh Source Block Parameters: eQEP3 ^9
C2BxeQ^(mask}(Mc)
The enhanced quadrature encoder pulse (*QP) module is used for deed
interface vwth a fcnear or rotary incremental encoder to get postton, drecdorv
and speed informabon from a rotating machine for use m a high-performance
modern and popbon-controt system.
The eQEP inputs mdude two pms for quadrature-dock, mode or direction-count
mode, an index (or 0 mrker), and a strobe input.
| General __ PosOon counter l Speed cateutabofTT Compare output _|_ W 4
v Output posmon counter
Manrman postoon counter value (0-4294967235):
42M96729S I
O Enable sat to ind value on index event
Enable set to int value on strobe event
f~] Enable software tradalirahon
Poskhki counter reset mode: Reset on the maamum poabon______________*
|g Output latch pcsoon counter on xidex event
Z. Output latch poadon counter on strobe event
0* ] Caned
MHp L
Ok____| [_ Caned J j_ Mdp___] [_ ApoV _J
(a)
(b)
Figure 4.15: Simulink configuration for eQEP
Table 4.5: ePWM configuration
PWM frequency 10kHz
Operating mode Shadow mode
Synchronization mode series
Phase shift 0
CTR mode Up-down
Load mode CTR=0
ADC trigger CTR=0


5k Sink Block Parameters: ePWM2
C280x/C2833x ePWM (mask) Clink)
Configurer the Event Manager of the C2S0x/C2833x DSP to generate ePWM waveforms.
General ePWMA ePWMB 1 Deadband unit j Event Trigger [ PWM chopper control Trip Zone unit
\D Allow use of 16 HRPWMs (for Q8044) instead of 6 PWMs
Modute: ePWMl
Timer period unrts: Clock cydes
Specify timer period via: Specify via dialog
Timer period:
17S0Q
Reload for time base period register (PROtD): Counter equals to zero
Counting mode: Up-Down
Synchronization action: Set counter to phase value specified via dialog
Counting direction after phase synchronization: Count down after sync
Phase offset value (T8PHS):
0
[ Specify software synchronization via input port (SWF5YNC)
Synchronization output (SYWCO): Pass through (EPWMxSYMCI or SWFSYNC)
Time base dock (TBCIK) prescaier divider: 1
High speed dock (HSPCIKDIV) prescaler divider: 1
V
>
| OK ~| Cancel Help Apply
Figure 4.16: Simulink configuration for ePWM
51


i Sink Block Parameters: ePWM2
C2WC2833X ePWM (mask) (link)
Configures the Event Manager of the C280x/C2833x DSP to generate eFWM waveforms.
General ePWMA ePWMB Deadband unit Event Trigger PWM chopper control Trip Zone unit
E Enable ePWMIA
CMPA units: Clock cydes *
Specify CMPAvia: Input port
CMPA initial value:
0
Reload for compare A Register (SHDWAMODE): Counter equals to zero
Action when counter=ZERO: Do nothing '
Action when counter=penod (PRD): Do nothing '
Action when counter=CMPA on up*count (CAU): Clear '
Action when counter=CMPA on down-count (CAD): Set '
Action when counter=CMPB on up-count (CBU): Do nothing s
Action when counter=CMPB on down-count (CBD): Do nothing '
Compare value reload condition: Load on counter equals to period (CTR=PR0) *
Add continuous software force input port
Continuous software force logic: Forcing disable '
Reload condition for software force: Zero '
E Enable high resolution F.VM (HRPWM)
High resolution PWM (HRPWM) loading mode: Counter equals to period (CTR=PRD) *
High resolution PWM (HRPWM) control mode: Duty control mode 1
< >
[ OK ~| Cancel Help ipph
Figure 4.17: Simulink configuration for ePWM
4.3.3 Configuration of CCS V5.5
As discussed earlier, Code Composer Studio is an Integrated Development En-
vironment (IDE) that supports Texas Instruments Microcontrollers and Embedded
Processors. It consists of all the tools that are used to develop and then debug embed-
ded applications. Code Composer Studio also contains optimizing C/C++ compiler,
source code editor, project build environment, debugger, profiler and many other fea-
tures. The IDE provides a single user interface taking you through each step of the
application development how. Getting familiar with all the tools and features of the
software makes it easier. Code Composer Studio combines advantages of the Eclipse
52


software framework with advanced embedded debug capabilities from TI resulting in
a highly rich development environment for embedded developers.
The figures below and the theory corresponding to the figures helps a new user to
configure CCS v5.5 at any point of time. The early process of configuring CCS v5.5
is to generate a makefile, which is used to automate building and then deploying the
software on target hardware.
4.3.3.1 Makefile Setup
If the control design is done in Simulink, navigate to the command prompt win-
dow, where you can see a command enter signal as >>. If you see that symbol, enter
the command xmakefilesetup in the Matlab command window. The command pops
up the dialog box which is shown in Fig. 4.13
*fc XMakefile User Configuration
Active
Template: gmake T
Configuration: ticcs_c2D00_ocsv5_done @ Display operational configurations only New... Delete
User Templates: C:\Users\BABAlAHB\Documents\MATLAB\ Browse...
User Configurations: C:\Users\BABAlAHB\Documents\MATLAB\ Browse...
Make Utility Compiler j unker j Archiver | Pre-build ] Post-build | Execute
Make utility: C:\Program Files\MATLAB\R2014a\bm\win32\gmake Browse...
Arguments: -f "[| j |MW_XMK_GENERAT£ D_FILE_H AM E [ R] 11|] [|| |MW_XMK_ACTIVEJU10_ACTI0N_REF| 11]
Optional include: Browse...
OK Cancel Help Afin;y
Figure 4.18: Make hie configuration in Matlab
If the dialog box does not show up in the same way as the above figure, then the
53


things that should be taken care are the clone configurations. The instructions for
achieving this configuration are: Firstly, clear the check box for display operational
configurations only and click on the New configurations, which should pop a display
box showing the names of the configurations. Select the appropriate configurations
for the application and then it creates a configuration that can be applied for the
project.
4.3.3.2 Configuration Parameters
In this section, a brief discussion about setting the configuration parameters in
order to generate an output hie, which is appropriate and suitable for the DSP that is
being used in this project. Coming to the solver pane of the configuration parameters,
the values should be selected for the start and stop times of the code and also the solver
type should be selected. The parameters that have been used for this project are the
fixed step solver and discrete solver. Some of the parameters are set by default and are
not necessary to be modified. However, it depends on the application used. Coming
to the hardware section, the hardware that is being implemented in this project is
the Texas Instruments Product and the device is a C2000 family type. Under the
Code generation pane, it should be noticed that the system target hie is selected as
idelink grt.tlc. By doing it that way, the system links the IDE environment to the
target hardware. Also a new pane called coder target pane is available, where all the
parameters about the actual hardware are updated. Later on under the coder target
pane, the build format is set to makefile, since the output format we selected earlier
for the embedded tool was makefile.
The action is set to Build and Execute, which enables the system to build an exe-
cutable hie. This process almost sets the configuration of CCS v5.5 on to the system
and you are ready to go. Before you start building the code on CCS v5.5, just make
sure to have everything correct, in case you had something not hxed. The hrst time
you use embedded coder with Code Composer Studio, you should check that the CCS
54


is installed and configured properly and also has at least one board configured. To
do that, enter the command ccsboardinfo in the Matlab command prompt window.
Matlab, then returns all the boards that are configured and recognized by the CCA
as shown as below.
Also, if necessary check all the third party tools and environment variables that
are set in the configuration using the command checkEnvsetup(ccs, /28335, check).
The Fig.4.14 shows the environment variables set in this project.
checkEnvSetup('cesvS','f2e33S, 'check')
1. CCSv5 (Code Composer Studio)
Your version :
Required version: 5.0 or later
Required for : Code Generation
TI_DIR=""
2. CGT (Texas Instruments C2000 Code Generation Tools)
Your version :
Required version: S.2.1 to 6.0.2
Required for : Code generation
C2 00 0_CGT_INSTA1LDIR= B "
3. DSP/BIOS (Real Time Operating System)
Your version :
Required version: 5.33.05 to 5.41.11.38
Required for : Code generation
CCSV5_DSP3IOS_IN5TALLDIR""
4. XDC Tools (express DSP Components)
Your version ;
Required version: 3.16.02.32 or later
Required for : Code generation
5. Flash Tools (TMS320C2S335 Flash APIs)
Your version :
Required version: 2.10
Required for : Flash Programming
FLASH_2833S_API_INSTALLDIR"""

Figure 4.19: Environment variables defined in the project
The next section explains about the incremental build technology.
55


4.4 Incremental Build Technology
Even though the programming is done by evaluating each block at a time, like
modular programming, sometimes it is difficult to debug if all the modules are lumped
together at a time. Therefore, the program structure is built level by level. Every
time before building a new level, the old level should be working correctly.
4.5 Troubleshooting DSP
Sometimes, there might be errors in the code that leads to damage in the DSK
board, which might be issue in many cases. In this section, brief discussion about some
of the damages that could be done to the DSP and the troubleshooting techniques to
repair the DSP are explained.
For the first case, let us take an example of having excess current flowing in
the circuits of DSK, which might result in the damage od some of the parts in the
DSK. If you experience bad smell from the DSK board or an unpleasant smell from
the board, immediately turn the system off, as there is some problem in the code.
Coming to troubleshooting the DSP, firstly, check the power circuit underneath the
DSK board and you can see the circuit leading from the 24V power supply to the
15V power supply of the PWM signal generation. It can be clearly noticed that the
power supply of the PWM is damaged and has to be replaced. The damaged PWM
power supply is then de soldered and then it should be replaced with a new power
supply. This would hopefully make the DSK work properly.
For the second case, let us take an example of overwriting the DSP default vari-
ables and clearing everything from the memory, which might result in the damage to
the main chip in the DSK. The symptoms to this problem are that you may not be
able to receive correct waveforms from ADC and PWM. This problem can only be
eliminated by replacing the chip on the DSK with a new one and that should work
properly.
56


5. Testing and Evaluation
In this chapter, the testing results are shown. As mentioned before, the control
system is programmed in three levels, namely the open loop system, system with cur-
rent regulator and the system with speed regulator, and its performance is evaluated
for all three levels as well.
5.1 Open loop test with V/F control
The open loop test is carried out by setting different frequency to the V/F con-
troller and observing the corresponding motor speed. The testing data are listed in
Table 5.1 and compared with the actual motor speed.
Table 5.1: Open loop test with V/F control
Frequency set (Hz) 10 15 20 25 30 35 40
Synchronous speed(rpm) 300 450 600 750 900 1050 1200
Machine speed (rpm) 295 440 586 730 862 1000 1110
Slip 1.67% 2.22% 2.33% 2.67% 4.22% 4.76% 7.5%
It can be seen from the table 5.1 that, the induction motor runs slightly slower
than the synchronous speed. With increase in the frequency, the slip is also increasing.
This might be due to the reason that the friction torque becomes larger with increasing
motor speed. Therefore larger slip is needed to generate enough torque.
5.2 Closed loop test with Current Regulator
One of the advantage of the setup we use in this project is that the user is able to
access the DAC memory, while the processor is still running. In order to capture the
dynamic response of d and q currents, two memory locations are allocated and can be
directly accesses using the oscilloscope. Once the step change in current reference is
applied, in each control loop, the value of d and q current is stored in the memory until
the memory if full. In the code, if these variables are converted directly to integer, the
57


resolution will be greatly reduced. To guarantee enough resolution, before converting
a variable, the variable is multiplied by 4095 or 2047, depending on how large its
maximum value is.
Tek JL mpok 1.010s i TRIGGER Tek JL M Pos 1.006s TRIGGER
Type Type
m Sjffl
Source Source
B B
a Slope
Mo* Mode
Hull
Coupling Coupling S3
M 250ms M 250ms
5-Oct-15 12:28 21-0ct-1S 17:20
(a) (b)
Figure 5.1: Step response of the d and q currents.Fig(a) is the step response of the
d current with a reference of 80mA, and fig(b) is the step response of the q current
with a reference of 80mA.
Tek JL M Pos; 1,010s TRIGGER Tek JL a Stop M Pos 1,010s TRIGGER Type
Source Source B
a m
Mode Mode mun
M 250ms 6-Oct-15 09:37 Coupling M 250ms B-Oct-15 0M1 Coupling BB
(a) (b)
Figure 5.2: Response in q current due to a step in i current. Fig. (a) shows q
current with respect to step in d current and Fig. (b) shows q current with respect
to quadrature reference i.e. zero
This analysis part is done in this section.
58


5.2.1 Analysis on Results
From Fig. 5.1(a) and Fig. 5.1(b), it can be seen that the rise time of both id
and iq are same and matches the design specifications. Though there is noise on
both the curves, it can be noticed that the currents arrive at their reference values
without steady-state error. The only problem is that we have a overshoot in the
iq waveform. Since the desired closed-loop system is a first-order system and anti-
windup has been added, there should not be any large overshoot. But other than
that, all other parameters have a satisfying result.
5.3 Closed Loop test with Speed Regulator
As the speed loop has much slower response than the current loop, more data
needs to be stored to study the step response of the speed loop.
5.3.1 Experimental Results
In the first design plan, the bandwidth for the speed control loop au is chosen as
20rad/sec. In order to eliminate the non-linearity and two much fluctuation, a much
smaller bandwidth for the speed control loop and a smaller reference speed are
applied in the experiment to avoid q current hitting its limit.
Tek JL M Pos: 18.40ms TRIGGER
Type
Source
Mode
M 50,0ms
5Oct1510:47
Figure 5.3: Speed step response at 300rpm and very small bandwidth
59


5.3.2 Analysis on Results
Given the speed control loop bandwidth au, the rise time of the speed response
is noticed to be satisfactory. Also, it is approaching steady state as it gets a larger
acceleration which causes an unnoticeable overshoot. But the difference between the
simulation results and the experimental results might be due to inaccurate speed
sensing, incorrect motor parameters like B and J, the motor coefficients. The other
factor might be due to inaccurate flux estimation. The variation in the machine
parameters will greatly affect the flux estimation. The error between the estimated
and the actual flux will lead to a wrong calculation of the q current reference, which
will cause a series of reactions and unexpected results.
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6. Simulink or C: A comparitive study
This chapter discusses the main research contribution to this project. In the past
few years, C language has been a primary language for the interface between the real
time models. But, in this project, unlike various other projects which uses C as their
interfacing language, the conventional C language has been replaced by Simulink,
an environment for simulation and model-based design for dynamic and embedded
systems.
6.1 Introduction to C
Embedded Processors can be programmed using various languages. However, the
most common language used to program embedded processors is C language. The
following figure Fig. 6.1 shows that C is used by more than a four-to-one margin over
its nearest competitor, Assembly language.
A&rmhb C C++ Jsu Other
Figure 6.1: Programming Languages used in Embedded Designs [5]
The reason that C language is used widely in programming embedded machines
is that it is a medium level language, in contrast to other high languages like JAVA or
low languages like Assembly. C, with its medium level of complexity is understandable
61


to humans, executes at a reasonably fast speed, and usually allows programmers to
exercise enough control over the inner working of the embedded processor. This
balance between intelligibility and fundamental control make C language the prime
choice for embedded processor programming. Sometimes, when additional control or
an extremely fast execution speed is needed for a specific instruction, a few lines of
Assembly language may be combined with the main C program.
6.1.1 How does C work?
When a program is written in any language more complex than Assembly (which
can be immediately processed by a computer), several steps are required to convert
that program into an executable hie. C in the form that a programmer writes is called
source code, and must go through the build process to generate functional code. This
source code must first be compiled, once compiled the resulting object code is linked
using a linker program. A linker attempts to find any libraries of code that the object
might need to perform its function (e.g. other object code compiled from other source
code); links these bits of code together; and creates an .exe executable hie that can
be run.
6.1.2 Drawbacks of C
As discussed above, it is understood that the C language is the widely used
programming language globally because of its executing speed and efficiency. In con-
trast to the advantages produced by the old standby computing language that many
would call obsolete: ANSI C, there are some drawbacks that could be encountered in
developing a model for a particular design. C and other higher languages have be-
come popular for modelling DSP algorithms because of the more concise expression of
behavior. However, these languages lack an effective automated path to implementa-
tion. To become implementable, the tradeoff for description languages like C should
become less concise. Sometimes the C becomes so complicated at instances like aug-
menting C with hxed-point quantization capabilities and loop parallelization. Also,
62


C language is considered as difficult to learn in very short period of time. Sometimes,
because of the conciseness in C, the code can be difficult to follow. I does not suite to
applications which require formatting and data hie manipulation. For learning how
to write programs in C, we must first know what alphabets, numbers and symbols are
used, then how constants, variables and keywords are formed, and finally how these
are combined to form an instruction.
6.1.3 Replacement for C
Having mentioned all the drawbacks that will be encountered when developing a
project using C as the main language, this section will explain the alternative language
that should be replaced in place of traditional language C. The main reason that a
different approach is used in this project is to reduce the overall time that takes for the
entire vector control algorithm to be implemented and deployed on target hardware
efficiently.
6.2 Introduction to Simulink
After many discussions and debates on using C language in designing vector
control, in this project, a new approach of using Simulink as the interface between
the software and the hardware. Also, this approach enabled us to create a completely
new technology of using Simulink to execute a makefile to run the hardware, as well
as to generate optimized C code automatically, using Simulinks extension tool called
embeddedcoder. This approach proved beneficial for this project as you can generate
both the Simulink and C code at the same time and in a reduced amount of time.
6.2.1 Flexibility with Simulink
In order to complete this project successfully, we have taken two approaches
into consideration, that can implemented similarly on the target hardware and then,
both the approaches are compared for the time length of the project. The Fig. 6.2
shows the flow chart diagram representing the various steps involved in both the
approaches. As seen from the figure, both the approaches produce the same result.
63


However, approachl does not offer flexibility in transiting to a different approach,
which in our case is appraoch2. But, appraoch2 offers a much flexibility in doing the
same thing.
Figure 6.2: Illustration of two different approaches that can be used in the project
This section covers the advantages of simulink over C
6.3 Advantages of Simulink over C
Simulink provides an interactive graphical environment and a customizable set
of block libraries that let you design, simulate, implement, and test a variety of
64


time-varying systems, including communications, controls, signal processing, video
processing and image processing. Simulink offers the quickest way of developing your
model in contrast to text-based programming language like C. Also, Simulink has
integrated solvers. But, for C, you have write to write the code to create a solver.
Simulink provides an efficient design and simulation framework for creating high-level
algorithm models and limited capabilities that directly assist in implementation. More
specifically, it allows for defining sample rates and fixed-point data types, a discrete-
time modelling engine, and a rich set of mathematical operations and analysis tools.
Furthermore, it includes methods for automatically propagating the fixed-point types
and sample rates through the algorithm data path. This process saves significant
time in capturing algorithm behavior.
65


7. Conclusions
7.1 Results from Present work
The main purpose and objective of this project are generally achieved. The
evaluation board seems to be working well for this project. Considering the interface
board part, the digital signal interfaces, such as PWM and incremental encoder, work
satisfactorily. But, if you observe the current signals from ADC, there is some noise
added to the measured signals. For the vector control design, the control system
on the DSP manages to control the d,q currents and speed accurately. One of the
problems that can be observed from the experimental results is the overshoot in q
current during the current control loop test. It was assumed that the problem might
be due to incorrectness in the parameters.
In the final section of this project, a comparison is done between the old con-
ventional approach and new approach used in this project in designing the vector
control algorithm. It can be concluded that, the approach which uses Simulink as the
interfacing language seems to have higher efficiency and flexibility in terms of time
when compared to the approach which uses C as the interfacing language for those
who are inexperienced in both approaches.
7.2 Future work
There is a room to improve the performance of the present system. Considering
ADC noise, the ADC conditioning circuit needs to be improved. New control strate-
gies could also be considered for control design in order to make system less sensitive
to parameter variation and reduce harmonic distortion. Finally, from many research
papers, it is understood that there is a possibility of controlling several motors simul-
taneously to make full use of F28335 DSPs capacity.
66


REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
Texas Instilments.
Texas Instuments.
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http://www.ti.com/lit/ug/spru812a/spru812a. pages 9-13.
http://www.ti.com/lit/ds/symlink/tms320f28335. pages 31-
Texas Instuments. www.ti.com/lit/pdf/sprufz6. pages 14-18.
Texas Instuments. http://www.ti.com/lit/ug/sprug05a/sprug05a. pages 9-15.
D. Lewis. Fundamentals of embedded software design. Prentice Hall, 2002.
DC or AC drives? A guide for users of variable-speed drives(VSDs). ABB, Tech.
Rep.
K. Aissa and K. D. Eddine. Vector control using series iron loss model of in-
duction, motors and power loss minimization. World Academy of Science, En-
gineering and Technology, 2009.
An887 ac induction motor fundamentals. Microchip, Tech. Rep., 2003.
M. Deicke and Rik W. De Doncker S. Muller. Adjustable speed generators
for wind turbines based on doubly-fed induction machines and 4-quadrant igbt
converters linked to the rotor. IEEE, 2000.
Seung-Ki Sul. Control of Electric Machine Drive Systems. Wiley-IEEE Press,
2011.
[11] L. Harnefors. Control of Variable-Speed Drives. Department of electronics,
Malardalen University, Sweden, Applied Signal Processing and control, 2002.
[12] Frede Blaabjerg and Ion Boldea loan Serban, Dorin Iles-Klumpner. Sensorless
Control of Wound Rotor Induction Generator for wind power applications: the
experimental test platform. IEEE.
[13] B. W. Karl J. Astrom. Computer-Controlled Systems, theory and design. Pren-
tice Hall, 1997.
[14] K. E. Arzen. Real-Time Control System. Lund Institute of Technology, 2008.
[15] R. Krishnan and A. S. Bharadwaj. A Review of Parameter Sensitivity and
Adaptation in Indirect Vector Controlled Induction Motor Drive Systems. IEEE
explore, 1990.
67


[16] Texas Instruments. Code Composer Studio Integrated Development Environ-
ment. vjvmj.ti.com/tool/ccstudio.
[17] Texas Instruments. controlSUITE Software Suite, vjvjvj.ti.com/tool/controlsuite.
[18] Balanced Three-Phase Circuits, http://my.ece.msstate.edu/faculty/donohoe/ece3614three-
phase-power.pdf.
[19] MathWorks. Matlab and Simulink Embedded Coder. R2014b.
[20] Texas Instruments. TMS320x2833x analog-to-digital converter(adc) module ref-
erence guide. Texas Instruments, Tech. Rep., October 2007.
[21] Texas Instruments. F2833x analogue digital converter. Texas Instruments, Tech.
Rep.
[22] Texas Instruments. TMS320x280x, 2801x, 2804x enhanced pulse width modula-
tor(epwm) module. Texas Instruments, Tech. Rep., July 2009.
[23] Texas Instruments. TMS320x280x, 2801x, 2804x enhanced quadrature encoder
pulse (eqep) module. Texas Instruments, Tech. Rep., December 2008.
68


Appendix A. Simulations and Waveforms
A.l Simulations
Figure A.l: Simulink model for V/F
Figure A.2: Simulink model for V/F subsystem
69


Figure A.3: Simulink model for Current control
70


Figure A.4: Simulink model for Speed control
71


A.2 Waveforms
Tek JL QTrig'd M Pos: 0.000s
CH2 Tek JL
Coupling
QTrig'd
+
M Pos: 0.000s
CH2
Coupling
BW Limit BW Limit
CHllOOV CH2 5,00V M 5.00ms CH2/0,00V CHI 5.00V CH2 5,00V M 10.0ms CH2/0,00V
CH3 5,00V 20-0ct-1514:00 62.1597Hz 20-Oct-1514:02 50,0555Hz
(a)
(b)
Figure A.5: (a) shows Stator voltages in abc reference frame and (b) shows Stator
voltages in stationary reference frame
Tek JL i Auto
... ^
M Pos: 0,000s CH2
LOijpling
2+***
BW Limit
K'OMHi
Volts/Div
Probe
10X
Voltage
Invert
;Hi $lv CH2 5.00V M 10,0ms CH2 / 0.00V
20-0ct-1514:07 <10Hz
Figure A.6: Stator voltages in rotating reference frame
72


Tek JL DWd M Pos: 0.000s ci,
Probe
10*
Voltage
Invert
m
CHI 1.00V CH2 10.0V M 5.00ms CH2/ 1.60V
CH3 1,00 V 20-0ct-1513:46 62.1103Hz
(a)
Tek JL DWd M Pos: 0.000s CH2
Coupling
BW Limit
HU
100MHz
10*
Voltage
Invert
W
CHI "5.00V CH2 5,00V M 10.0ms CH2/0,00V
20-Oct-15 14:12 63,1061Hz
(b)
Figure A.7: (a) shows Stator currents in abc reference frame and (b) shows Stator
currents in stationary reference frame
Tek JL DWd M Pos: 0.000s TRIGGER
Type
aa
Source
Big
Mode
Coupling
BB
CH1 i0,0V CH2 10.0V M 10.0ms CH2/ 0,00V
20-0ct-15 14:40 46.4014Hz
Figure A.8: Stator currents in rotating reference frame
73


RIGOL STOP
f 0 680K)U
Figure A.9: Theta varying from II to +11
Figure A. 10: Offset in current
74


Full Text

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DEVELOPMENTOFFIELDORIENTEDVECTORCONTROLLERFORAN INDUCTIONMOTORUSINGMATLABEMBEDDEDCODER by BHANUBABAIAHGARI BachelorofScience,JawaharlalNehruTechnologicalUniversity,2013 Athesissubmittedtothe FacultyoftheGraduateSchoolofthe UniversityofColoradoinpartialfulfllment oftherequirementsforthedegreeof MasterofScience ElectricalEngineering 2015

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ThisthesisfortheMasterofSciencedegreeby BhanuBabaiahgari hasbeenapprovedforthe DepartmentofElectricalEngineering by JaedoPark,Chair TimLei YimingDeng November16,2015 ii

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Babaiahgari,Bhanu(M.S.,ElectricalEngineering) DevelopmentofFieldOrientedvectorcontrollerforaninductionmotorusingMatlab embeddedcoder ThesisdirectedbyAssistantProfessorJaedoPark ABSTRACT Inthisthesisproject,afeldorientedvectorcontrolsystemforaninductionmotor isimplementedonanexperimentalevaluationboard.Bylookingattheperformance pointofview,theTMS320F28335DSPisselectedasthedigitalcontrollerofthevector controlsystem.Alltherequiredperipheralandinterfacingcircuitsaredevelopedfor thethree-phaseinvertercontrol,signalmeasurementandforsystemprotectionaswell. Thisprojectistestedbymeansoflevel-by-levelapproach.Firstly,itistestedusinga simplercontrolleri.e.V/Fcontrol.Secondly,acurrentPIcontrollerisimplemented andnextitistestedbyspeedPIcontroller.Atthestageofthecontrollerdesign, thevectorcontrolsystemissimulatedinMatlab/SimulinkusingSimulinkblocks. Thesimulationresultsmeetthedesignspecifcationswell.Whenthecontrolsystem isverifedbysimulations,theDSPevaluationboardisprogrammedusingthefle generatedbyembeddedcoder(SimulinkTool)andtested.Thetestresultsshowthat thecurrentregulatorandspeedregulatorareabletocontrolthestatorcurrentand themotorspeedaccurately.Finally,aperformancecomparisonisevaluatedbetween theconventionalapproachandtheoneusedinthisproject.Theresultsshowthat theapproachusedinthisprojecthashighereciencyandrexibilityintermsof developmenttime. Theformandcontentofthisabstractareapproved.Irecommenditspublication. iii

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Approved:JaedoPark iv

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ACKNOWLEDGMENT Iwouldliketoexpressmydeepestthankstomyadvisor,Dr.JaeDoPark,for hisvaluableguidanceandsuggestionshehasgivenmeinthisproject.Withouthim, thiswouldhavebeenimpossible.Also,Ithankthecommitteemembers,Dr.TimLei andDr.YimingDengforspendingtheirvaulabletimeforreviewingthisreportand attendingmydefense. IwouldliketoexpressgratitudetomymotherSamanthakamani(Chitti)andmy fatherNagarajufortheirencouragementandsupportthroughouttheproject. IwouldalsoliketothankMuahnnadAlarajforexplainingsomeofthetopics relatedtothisproject. v

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DEDICATION Thethesisisdedicatedtomyfamilyandentouragewhohaveencouragedmetogo furtherduringmylife. vi

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TABLEOFCONTENTS Chapter 1.Introduction...................................1 1.1Background...............................1 1.2Objectives................................2 1.3Scope...................................2 2.InductionMachineVectorControlSystemDescription............3 2.1ACInductionMachine.........................4 2.2Three-phaseInverterandPulseWidthModulation(PWM).....6 2.3VectorControlSystem.........................8 2.3.1ClarkeandParkTransformations................9 2.3.2InverseClarkeandParkTransformations...........11 3.VectorControlDesignforMachineControl..................13 3.1MeasurementandEstimationofParametersofInductionMachine.13 3.1.1RatedvalueofRotorFluxLinkage, e dr .............13 3.1.2StatorTransientInductance, L s ................14 3.1.3MutualInductance, L m .....................15 3.2EquivalentmodelofInductionMachine(T-Model)..........15 3.3CurrentRegulator............................16 3.3.1CurrentReference........................18 3.3.2FeedForward...........................18 3.3.3VoltageLimiter..........................19 3.3.4Anti-windup...........................19 3.4FluxEstimator..............................19 3.5SpeedRegulator.............................21 3.6Simulation................................22 3.7Discretization..............................23 vii

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4.DSPProgrammingandCCSV5.5.......................26 4.1OverviewofDSP............................27 4.1.1ADCModule...........................29 4.1.2PWMmodule...........................33 4.1.2.1Time-basesubmodule...................34 4.1.2.2Counter-comparesubmodule...............38 4.1.2.3ActionQualifersubmodule...............39 4.1.2.4Deadbandsubmodule...................40 4.1.2.5EventTriggersubmodule.................41 4.1.2.6Dutycyclecalculation..................42 4.1.3EncoderModule.........................44 4.1.4OsetMeasurement.......................46 4.2HardwareSetup.............................46 4.3SystemInitializationandConfgurationofCCSV5.5.........48 4.3.1Initialization...........................48 4.3.2Confguration...........................48 4.3.3ConfgurationofCCSV5.5...................52 4.3.3.1MakefleSetup......................53 4.3.3.2ConfgurationParameters................54 4.4IncrementalBuildTechnology.....................56 4.5TroubleshootingDSP..........................56 5.TestingandEvaluation.............................57 5.1OpenlooptestwithV/Fcontrol....................57 5.2ClosedlooptestwithCurrentRegulator................57 5.2.1AnalysisonResults.......................59 5.3ClosedLooptestwithSpeedRegulator................59 5.3.1ExperimentalResults......................59 viii

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5.3.2AnalysisonResults.......................60 6.SimulinkorC:Acomparitivestudy......................61 6.1IntroductiontoC............................61 6.1.1HowdoesCwork?........................62 6.1.2DrawbacksofC..........................62 6.1.3ReplacementforC........................63 6.2IntroductiontoSimulink........................63 6.2.1FlexibilitywithSimulink.....................63 6.3AdvantagesofSimulinkoverC.....................64 7.Conclusions...................................66 7.1ResultsfromPresentwork.......................66 7.2Futurework...............................66 References ......................................67 Appendix A.SimulationsandWaveforms..........................69 A.1Simulations................................69 A.2Waveforms................................72 ix

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LISTOFTABLES Table 4.1 ADCinputchannelsandcorrespondingaddresses .............31 4.2 EncoderTruthtable .............................46 4.3 ConfgurationofADC ............................49 4.4 eQEPconfguration ..............................49 4.5 ePWMconfguration .............................50 5.1 OpenlooptestwithV/Fcontrol .......................57 x

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LISTOFFIGURES Figure 2.1OverviewofInductionMachinevectorcontrolsystem...........3 2.2StructureofanInductionMachine.....................3 2.3OperatingprincipleofInductionMachine.................6 2.4ThreePhasePWMInverterSchematic(OrCAD).............7 2.5PulseWidthModulation(PWM)generationprinciple...........8 2.6ClarkeandParkTransformations......................10 3.1EquivalentTcircuitoftheinductionmotordynamicmodel.......15 3.2OverviewofCurrentRegulator.......................17 3.3StructureofFluxestimator.........................20 3.4SpeedcontrolRegulator...........................21 3.5IntegralofthecomplexnumberinSimulink................22 3.6Saturationofthecomplexnumberinsimulink...............23 3.7ForwardEulerapproximation........................24 3.8IntegralformofForwardEulerapproximation...............24 4.1ProgrammingDesign.............................27 4.2Flowchartoftheprogram..........................28 4.3BlockdiagramofADCmodule[1].....................30 4.4ADCmoduleconfgurationsetupinthisproject[1]............32 4.5BlockDiagramofF28335[2].........................34 4.6InternalmodulesofePWMandtheirconnections[3]...........37 4.7TimebasecountersynchronizationschemeforF28335..........38 4.8Counter-compareevent,up-downcountermode..............39 4.9BlockdiagramofePWMdeadbandsubmodule..............41 4.10WaveformofPWMwithdeadbandinserted................42 4.11BlockdiagramofeQEPmodule[4].....................45 xi

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4.12AnexamplewaveformoftheeQEP(anti-clockwiserotation).......47 4.13HarwareSetupinthelab..........................47 4.14SimulinkcodeconfgurationforADC....................49 4.15SimulinkconfgurationforeQEP......................50 4.16SimulinkconfgurationforePWM......................51 4.17SimulinkconfgurationforePWM......................52 4.18MakefleconfgurationinMatlab......................53 4.19Environmentvariablesdefnedintheproject................55 5.1Stepresponseofthedandqcurrents.Fig(a)isthestepresponseofthed currentwithareferenceof80mA,andfg(b)isthestepresponseoftheq currentwithareferenceof80mA.......................58 5.2Responseinqcurrentduetoastepinicurrent.Fig.(a)showsqcurrent withrespecttostepindcurrentandFig.(b)showsqcurrentwithrespect toquadraturereferencei.e.zero.......................58 5.3Speedstepresponseat300rpmandverysmallbandwidth........59 6.1ProgrammingLanguagesusedinEmbeddedDesigns[5]..........61 6.2Illustrationoftwodierentapproachesthatcanbeusedintheproject.64 A.1SimulinkmodelforV/F...........................69 A.2SimulinkmodelforV/Fsubsystem.....................69 A.3SimulinkmodelforCurrentcontrol.....................70 A.4SimulinkmodelforSpeedcontrol......................71 A.5(a)showsStatorvoltagesin abc referenceframeand(b)showsStator voltagesin stationary referenceframe...................72 A.6Statorvoltagesinrotatingreferenceframe.................72 A.7(a)showsStatorcurrentsin abc referenceframeand(b)showsStator currentsin stationary referenceframe...................73 A.8Statorcurrentsinrotatingreferenceframe.................73 xii

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A.9Thetavaryingfrom )Tj /T1_0 11.955 Tf [(to+.......................74 A.10Osetincurrent...............................74 xiii

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1.Introduction 1.1Background AC(AlternatingCurrent)motorshaveasimplestructureandhashighereciency thantheDCmotorswhenoperatedatahighspeed[6].Inthepast,duetoconvenience oftorqueandspeedcontrol,theDCmachinehadbeenusedwidelyforadjustable speeddrive(ASD).However,recently,withthedevelopmentofpowerelectronics technology,theACmachinedrivesystemsuchastheinductionmachineandthe synchronousmachinedrivenbyavariablevoltagevariablefrequency(VVVF)inverter arebeingused.ACmachinesdonothavethecommutatorandbrushofDCmachine, whichneedregularmaintenancearetheweakpointsofaDCmachine.ACmotors alsoprovidemoredurableservicewithalowercostcomparedtoDCmotors.Besides, ACmotorscaneasilybesupplieddirectlyfromthegridandthereforetheyarewidely usedintheindustry.AndthistrendshiftfromDCmachinetoACmachinehas beencontinuedbecauseofthedevelopmentofnotonlythepreviouslymentioned powerelectronicsbutalsothecontroltheoryofACmachinesuchasfeldorientation control. Foravariable-speedapplication,ifthepowersourceisDC,avariable-speeddriver isneeded,whichisusuallydonewiththreephaseinverter.Withfeedbackorientation, ACmotorscanbemodelledsimilartoseparatelyexcitedDCmotorthroughaseries ofcoordinatetransformations.ForthetransformedACmotormodel,DCmotor controlmethodscanbeappliedtocontrolparameterslikespeed,torque,currentsto obtaingoodtransientperformance[7].Thismethodofcontrollingthetransformed ACmotoriscalledvectorcontrol. Usually,anembeddedmicrocontrollertakescareoftheoveralloperationofAC motorcontroller.Amongvariousmicrocontrollers,DigitalSignalProcessor(DSP) canperformcomplexcomputations,suchascoordinatetransformationsandcontrol algorithms. 1

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1.2Objectives Themainobjectiveofthisprojectistodesignandimplementsensoredvector controlsysteminMatlab/SimulinkontheTMS320F28335boardforaninduction machine.Also,designinganexperimentalsetupforthestudentstoaccesstheentire projectispartofthetask.Theapproachusedinthisprojectismucheasierto understandandimplementthesystem.Inthepast,theprogrammingwasusually doneinClanguage,whichrequiresanexpertknowledgeinC.Buttheapproachused inthisprojectisentirelydoneinMatlab/Simulink,thesoftwarethatmanypeople useinthesedaystoreducethetimetoimplementthesystem.Thefnaloutcomeof thisprojectshouldbesensoredvectorcontrolsystemofaninductionmachineonan evaluationboard. 1.3Scope Thecontentsofthisprojectcoversmanyacademicandpracticalareas,suchas programming,debugging,analoganddigitalcircuitdesignandconstruction,inductionmachinemodellingandvectorcontroltheory. 2

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2.InductionMachineVectorControlSystemDescription Inthischapter,abriefdescriptionofinductionmachinecontrolsystemisgiven. Thebasicoverviewofinductionmachinevectorcontrolsystemusedinthisproject isshowninFig.2.1.Thevectorcontrolsystemincludesafewhardwaredevices namelyinductionmachineandinverter,andtechnicaltheorysuchasvectorcontrol strategyandPulseWidthModulation(PWM).Detailsaboutthedierentpartswill bediscussedinthelatterchapters. Figure2.1:OverviewofInductionMachinevectorcontrolsystem. Figure2.2:StructureofanInductionMachine 3

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2.1ACInductionMachine AninductionorasynchronousmachineisanACelectricmotorinwhichthe electriccurrentintherotorneededtoproducetorqueisobtainedbyelectromagnetic inductionfromthemagneticfeldofthestatorwinding.Aninductionmotortherefore doesnotrequiremechanicalcommutation.Aninductionmotor'srotorcanbeeither woundtypeorsquirrel-cagetype[8].Theinductionmachineiscomposedofastator andarotorasshowninFig.2.2(a)andFig.2.2(b).Thestatorisfxedwhilethe rotorrotatesinsidewithasmallairgapbetweenthem.Therotorcontainsconductor barsandendringsasshowninFig.2.2(b).Therotorcageisaclosedconductor astheconductorbarsareallshort-circuitedbytheendrings.Therotorismounted ontheshaftwithtwobearings[8].Normallyoneofthetwoshaftendsisusedfor drivingtheloadwhiletheotheroneformountingtheshaftpositionorthespeed measurementdevices.Thestatorismadeupofseveralpolepairs.Eachpolepair hasthreewindingsplacedsymmetricallyinspaceasshowninFig.2.2(a).Basedon thearrangementofthethreewindings,theruxlinkages(t A ,t B andt C )generated bythewindingshave120displacementinspace.Themagnitudesofruxlinkages (t A ,t B andt C )couldbeexpressedas (t)= Z (u s (t) )Tj /T1_3 11.955 Tf 11.955 0 Td [(Ri s (t))dt; (2.1) where u s (t)istheappliedvoltagetoeachwinding, R istheresistanceofeachwinding and i s (t)isthecurrentthrougheachwinding.Ifathreephasevoltageisappliedon thestatorwindings,i.e. u a (t)= U pk sin(2ft + 2 )(2.2) u b (t)= U pk sin(2ft + 7 6 )(2.3) u c (t)= U pk sin(2ft + 11 6 )(2.4) where U pk and f arethepeakvalueandthefrequencyoftheappliedvoltagerespectively,thiswillresultinasinusoidalruxlinkageineachphasethatlagsthephase 4

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voltageby90ifthewindingresistanceisneglected,thatis t A (t)=t pk sin(2ft ) (2.5) t B (t)=t pk sin(2ft + 2 3 )(2.6) t C (t)=t pk sin(2 ft + 4 3 )(2.7) ThewaveformsofthethreecurrentsareshowninFig.2.3(a).Ineachperiod,the currentfromeachwindingreachesitsmaximumvalueonce.AsshowntheFig. 2.3(b),theresultantruxcanbeobtainedbyaddingthethreeruxlinkagesandhas amagnitudeof1.5t pk .Fromanalysisofdierentmoments,itcouldbenoticedthat themagnitudeofresultantruxvectordoesn'tchangeanditrotateswithaconstant magnitude.TherotationoftherotorcanbeseeninFig.2.3(c).Themagnitudeof thisrotatingruxvectrois1.5timesofthepeakvalueofeachwinding'sruxlinkage. Therotatingspeed N s (inrpm)oftheresultantruxiscalledsynchronousspeed, calculatedas N s =120 f P (2.8) Where f isthreephasevoltagefrequencyand P isnumberofpoles. Therotatingresultantstatorruxlinkagecutstherotorbars,whichwillinducea voltageintherotorbars.Sincetherotorbarsareshort-circuited,thisinducedvoltage willdriveacurrentintherotorbars.ByLenzslaw,Aninducedcurrentisalwaysin suchadirectionastoopposethemotionorchangeproducingit,theinducedcurrent willgenerateatorquetryingtomaketherotorfollowtherotatingruxgenerated bythestatorwindings.However,iftherotorspeedisexactlyequaltosynchronous speed,therewillnotbeaninducedcurrentandhencenotorque.Otherexternal factorslikefrictiontorqueandloadtorquewillmaketherotorslowdown.Sothe inductionmachinerotorrunsataslightlyslowerspeedthanthesynchronousspeed inordertogetenoughinducedcurrentanddrivingtorque.Therealwaysexistsagap 5

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betweenmachinespeedandsynchronousspeed,whichisreferredtoasslip.Thisis whyinductionmachinehasanothernameasasynchronousmachine. Figure2.3:OperatingprincipleofInductionMachine 2.2Three-phaseInverterandPulseWidthModulation(PWM) Thethree-phaseinvertersuppliestheinductionmachinewiththree-phasealternatingvoltage.Fromtheorcadschematicofthree-phaseinvertershowninFig.2.4, itcanbeseenthatthethree-phaseinverterisfedbyaDCvoltageastheenergy inputandhasthreeparts,eachcontainingtwoIGBTsandtwodiodes.Considerthe DC-linkvoltagefedintothethree-phaseinverteras V dc .ForphaseA,ifU1isturned on,thephasevoltagerelativetogroundwillbeequalto+ V dc =2;whileifswitchU2 isturnedon,itisequalto V dc =2. Thoughitseemslikethethree-phaseinverteronlycangeneratetwopossible voltagevaluesforphasevoltage,+ V dc =2or V dc =2,PulseWidthModulation(PWM) 6

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makesitpossibletoforthethree-phaseinvertertoconverttheDC-linkvoltageto three-phasealternatingvoltagebycontrollingtheon-timesando-timesoftheIGBTs.Byadjustingtheproportionofon-timeinonePWMswitchingperiodforthe samebridge,anyvaluebetween+ V dc =2and V dc =2canbeobtainedasthephasevoltage.Theratioofontimeandthetotalonandotimeisdescribedasdutycycleand canbeformulatedas: D = T on T on + T off (2.9) ThebasicprincipleofPWMgenerationistocomparewaveformsofatriangular Figure2.4:ThreePhasePWMInverterSchematic(OrCAD) wave(carrierwave)andasinewave(referencewave)showninFig.2.5.Whenthe magnitudeofthesinewaveislargerthanthetriangularwave,thePWMsignalwill outputahighvoltageleveltoswitchonthecorrespondingIGBT.Onthecontrary, whenthemagnitudeofthesinewaveissmallerthanthetriangularwave,thePWM 7

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signalwillproducealowvoltageleveltoturnotheIGBT.Thisprocessisillustrated inFig.2.6.Hencethecorrespondingtimemomentsoftheintersectionsofthetwo wavesserveastheturningpointstoswitchonorotheIGBTintheinverter. Toshowtheoperationofathree-phaseinverter,asimulationinFig.2.4byOrCADsoftwareisperformed.Thereferencevoltagesforthethreephasesareassumed tobeconstantandDC-linkvoltageis220V.Theloadsoftheinverterareassumedto beresistiveandconnectedinaY-confguration. Figure2.5:PulseWidthModulation(PWM)generationprinciple 2.3VectorControlSystem Vectorcontrol,alsocalledfeld-orientedcontrol(FOC),isavariable-frequency drive(VFD)controlmethodwherethestatorcurrentsofathree-phaseACelectric motorareidentifedastwoorthogonalcomponentsthatcanbevisualizedwithavector.Onecomponentdefnesthemagneticruxofthemotor,theotherthetorque.The 8

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mainadvantageofvectorcontrolsystemisitgetsridofmachinespeeddependency onpowergridfrequencyandmakeitpossibletoreachdesiredmachinespeedwithin safetyandpowerlimits,althoughitgivesrisetoaconsiderablecomplexcomputation fortheprocessorwherethecontrolalgorithmsareimplemented. Normally,inavectorcontrolsystem,thephasecurrentsofthemachineand machinespeedaretakenascontrolsysteminputs,andphasevoltagestothemachine aretakenasoutputs.Twoimportanttransformationsinvolvedinthevectorcontrol systemallowsittotransformACmachinelikeaseparatelymagnetizedDCmachine, namelyClarkeTransformationandParkTransformation.Thethreephasesinusoidal quantitiescanbeeasilytransformedintoDCquantitiesinsteadystateusingboth thetransformations. 2.3.1ClarkeandParkTransformations Ifthethree-phasestatorcoilsarearrangedsymmetricallyinspacewitha120 displacementasshowninFig.2.6(a),andthesumofthephasecurrentsamplitudeis zero(i a (t)+ i b (t)+ i c (t)=0),neglectingthezerosequencecurrents,theinstantaneous three-phasecurrentscanbeexpressedbyanequivalentspacecurrentvector ~ i a ,with two-phasequadraturequantitiesas ~ i s (t)= 2 3 (i a (t)+ i b (t)e j 2=3 + i c (t)e j 4=3 )(2.10) = 2 3 (i a (t) )Tj /T1_0 11.955 Tf 13.151 8.088 Td (1 2 i b (t) )Tj /T1_0 11.955 Tf 13.15 8.088 Td (1 2 i c (t)+ j p 3 2 (i b (t) )Tj /T1_3 11.955 Tf 11.955 0 Td (i c (t))) (2.11) = i + i f (2.12) whereconstant2/3isplacedinordertomakethetwo-phasequantitiestohavethe sameamplitudeasthethree-phasequantities.AscanbeseenfromtheFig.2.6(a), the -axisofthe f coordinatesystemisalignedwiththedirectionoftheA-phase spacevector.Asthe f coordinatesystemisstationarywithrespecttothecoilsand thecoilsarefxedtothestator,the f coordinatesystemisstationaryaswell. 9

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(a) (b) Figure2.6:ClarkeandParkTransformations Invectorcontroltheory,thethree-phasetotwo-phasecoordinatetransformation isnamedasClarkeTransformation.Thereverseprocessthatturnsthree-phaseback totwo-phaseiscalledInverseClarkeTransformation,whichisexplainedinthelatter sections.ClarkeTransformationcanbeexpressedinthematrixnotationas: 2 6 4 i i f 3 7 5 = 2 6 4 2 3 )Tj /T1_5 7.97 Tf (1 3 )Tj /T1_5 7.97 Tf (1 3 0 1 p 3 )Tj /T1_5 7.97 Tf (1 p 3 3 7 5 2 6 6 6 6 4 i a i b i c 3 7 7 7 7 5 (2.13) respectively.Thistransformationcanbeappliedanyotherthree-phasequantities, suchasrux,voltagesandsoon,inordertogettwo-phasequantities. Ifyounoticethe andthe f componentsoftheserotatingvectors,youcould seethattheyarestillACsinusoidalquantities.Thereforeanewcoordinatesystem isdefned,calledthe dq coordinatesystem,whichhasthesameoriginasthe f coordinatesystembutitrotateswiththespeedwespecify.Usuallywerotate dq coordinatesystemwiththesamespeedasruxrotatestomaketheimaginarypart ofthecoordinatesystemtobezero.Thistransformationofaspacevectorcanbe achievedbymultiplyingthevectorby e )Tj /T1_4 7.97 Tf [(j ,where istheanglebetweenthetwo coordinatesystem.AsseenintheFig.2.6(b),the f coordinatesystemhasbeen 10

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transformedto dz coordinatesystem.Thetransformationcanbeexplainedas: ~ i dq = ~ i f e )Tj /T1_2 7.97 Tf [(j (2.14) ThisTransformationfromthe f coordinatesystemto dq coordinatesystemiscalled ParkTransformationwhileitsreverseprocessiscalledInverseParkTransformation, whichisexplainedinthenextsection.Ifthevectornotationisexpressedintermsof scalarnotation,theaboveequationscanbewrittenas: ~ i s = i + ji f (2.15) ~ i dq = i d + ji q (2.16) and e )Tj /T1_2 7.97 Tf [(j canbeexpandedusingEulersformulaas: e )Tj /T1_2 7.97 Tf [(j =cos )Tj /T1_1 11.955 Tf 11.955 0 Td (j sin (2.17) Thereforeequation2.14canbeexpressedinmatrixformas: 2 6 4 i d i q 3 7 5 = 2 6 4 cos )Tj /T1_0 11.955 Tf 11.291 0 Td (sin sin cos 3 7 5 2 6 4 i i f 3 7 5 (2.18) 2.3.2InverseClarkeandParkTransformations Assaidearlier,theInverseClarkeTransformationandInverseParkTransformationarethereverseprocessofthetransformationsdiscussedabove.Thisinverse transformationsarerequiredinthevectorcontroltheory[9]totransformthemodifed two-phaserotatingquantitiestothree-phasestationaryquantities,whichareinputs tothethreephaseinverter. Thesametheorydiscussedaboveappliestotheinversetransformationtheory aswell,however,weapproachthisinareversedirection.Hencewetakeinverseof equation2.13andthiscanbeexplainedas: 2 6 6 6 6 4 i a i b i c 3 7 7 7 7 5 = 2 6 4 2 3 )Tj /T1_7 7.97 Tf (1 3 )Tj /T1_7 7.97 Tf (1 3 0 1 p 3 )Tj /T1_7 7.97 Tf (1 p 3 3 7 5 )Tj /T1_7 7.97 Tf (1 2 6 4 i i f 3 7 5 (2.19) 11

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2 6 6 6 6 4 i a i b i c 3 7 7 7 7 5 = 2 6 6 6 6 4 10 )Tj /T1_5 7.97 Tf (1 2 p 3 2 )Tj /T1_5 7.97 Tf (1 2 )Tj 6.586 6.598 Td (p 3 2 3 7 7 7 7 5 2 6 4 i i f 3 7 5 (2.20) TheInverseParkTransformationcanbederivedfromequation2.14as: ~ i f = ~ i dq e j (2.21) and e j canbeexpressedusingEulersformulaas: e j =cos + j sin (2.22) Fromtheaboveequations,theInverseParkTransformationcanbeexpressedin Matrixformas: 2 6 4 i i f 3 7 5 = 2 6 4 cos sin )Tj /T1_3 11.955 Tf 11.291 0 Td (sin cos 3 7 5 2 6 4 i d i q 3 7 5 (2.23) 12

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3.VectorControlDesignforMachineControl Thischapterdiscussesaboutdesigningthecontrollerblocksnamelyruxestimations,currentregulatorsandspeedregulators,thathavetobeundergonesucceeding thetransformationsdiscussedinchapter2.Theparametersofthemachineshould beidentifedforsettingthegainsoftheregulators,limitingvaluesofthelimitersof thecontroller,referenceandfeed-forwardingvaluestotheregulator,andsoon.In general,theparametersofthemachinearedeterminedusinglockedrotortestorby theno-loadtest.But,inactualoperatingconditions,thesevaluesmightvarywidely. Thefollowingsectionsdiscussbrieryaboutthevectorcontrolsystem. 3.1MeasurementandEstimationofParametersofInductionMachine Inthissection,someofthemethodstoidentifytheparametersofelectricmachines [10]basedontheextratestsornameplatedataofthemachineryareintroduced. Thoughthemethodbasedonanextratestprovidesreasonablyaccurateparameters, themethodsmayneedsometoolstoapplythetestsignalsorspecialsetupforthe test.Hence,itisdiculttobeusedgenerallyintheindustrysite. 3.1.1RatedvalueofRotorFluxLinkage, e dr Thestatorvoltageequationforrotorrux-orientedvector-controlledinduction machinecanbewrittenformthecalculationpart,as V e ds =( R s + R r L 2 m L 2 r )i e ds + L s di e ds dt )Tj /T1_2 11.955 Tf 11.955 0 Td (! e L s i e qs )Tj /T1_2 11.955 Tf 11.956 0 Td (R r L m L 2 r e dr (3.1) V e qs =( R s + R r L 2 m L 2 r )i e qs + L s di e qs dt + e L s i e ds + r L m L r e dr (3.2) Basedonsomeapproximationsdoneatnearratedoperatingspeedwithnoload,the equation3.2canbewrittenas V e qs = r e dr = e e dr (3.3) Inthismodeofoperation,wehave V e qs V e ds .Thereforethepeakofthephase voltagecanbeapproximatedas V e qs .Hencetheratedruxcanbecalculatedfromthe 13

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ratedvoltageandratedfrequencyoftheinductionmachine.Thisisdonebysimply dividingthepeakoftheratedphasevoltagebytheratedangularfrequency, e ofthe machine. 3.1.2StatorTransientInductance, L s Thestatortransientinductanceoftheinductionmachinecanbedefnedand approximatedas L s = L s )Tj /T1_1 11.955 Tf 13.15 8.088 Td (L 2 m L r (3.4) Itistobenotedthat,thetransientinductancevarieswiththemagnitudeandthe frequencyofthecurrentrowingthroughtheinductance.Ifthestatortransientinductanceisnotaccuratelymeasured,thetorqueofthemachinemightleadtooscillatory response.Thetransientinductancecanbeestimatedbyapplyingashortvoltage pulsetotheinductionmachinethroughaPWMinverterasshowninFig.3.1.The Fig.3.2showstherowofcurrentinthecircuit.Inthistest,thephasevoltage equationcanbederivedas V as =( R s + R r )i as +(L ls + L lr ) di as dt =( R s + R r )i as + L s di as dt (3.5) Ifthewidthofthevoltagepulseissmallenoughcomparedtothestatortimeconstant defnedas T = L s R s +R r ,mostofthevoltagewillbeappliedtothestatortransient inductanceandcanbeapproximatedas V as = L s di as dt (3.6) Hencethetransientinductance, L s ,canbeestimatedas L s = V ad t 2 )Tj /T1_1 11.955 Tf 11.955 0 Td (t 1 i as (t 2 ) )Tj /T1_1 11.955 Tf 11.955 0 Td (i as (t 1 ) (3.7) 14

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3.1.3MutualInductance, L m Themutualinductanceofamachinecanbeidentifedeasilyifno-loadoperation ispossibleforthesystem.Inthiscase,bysimplymeasuringthephasecurrentand thephasevoltage,thesumofthestatorleakagereactanceandthemutualreactance canbeobtainedbydividingvoltagebythecurrent.Thenthemutualinductance canbeapproximatedbydividingthesumbytheoperatingfrequency, e ,under theassumptionthatthestatorleakageinductanceismuchsmallerthanthemutual inductance.Notethattheoperatingfrequencyshouldbeneartheratedvalueto reducetheerrorduetotheresistancevoltagedropofthestatorwinding.Themutual inductanceofthemachinevariesaccordingtothemagnitudeoftherotorruxlinkage decidedbythemagnitudeofthed-axiscurrentofthesynchronousreferenceframe. 3.2EquivalentmodelofInductionMachine(T-Model) Theequivalentmodeloftheinductionmachinecanbedescribedbyusingspace vectors.Althoughtherearemanydynamicmodelsofthemachine,weuseTmodel defnedinthestationary f systeminthismanual.Theequivalentcircuitinthe formofT-circuit[11]isshowninFig.3.1Fromthecircuitshownabove,thestator Figure3.1:EquivalentTcircuitoftheinductionmotordynamicmodel 15

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androtordynamicequationscanbederivedas, ~ V s = R s ~ i s + d ~ s dt (3.8) ~ V r =0= R r ~ i r + d ~ r dt )Tj /T1_1 11.955 Tf 11.955 0 Td [(j! r ~ r (3.9) wherethestatorandrotorruxlinkageequationscanbewrittenas, ~ s = L ls ~ i s + L m ~ i r (3.10) ~ r = L lr ~ i r + L m ~ i s (3.11) Thetorqueequationcanbederivedfnallyas, T e = 3 2 P L m L r Imag ( ~ s ~ i s ) (3.12) Thequantitiesusedintheinductionmotorarelistedbelow. ~ V s = V s + jV sf :Statorvoltage R s :Statorresistance ~ V r = V r + jV rf :Rotorvoltage R r :Rotorresistance ~ i s = i s + ji sf :Statorcurrent L s :Statorinductance ~ i r = i r + ji rf :Rotorcurrent L r :Rotorinductance ~ i m = i s + ji r :Magnetizingcurrent L m :Mutualinductance ~ s = s + j sf :Statorruxlinkage L ls :Statorleakageinductance ~ r = r + j rf :Rotorruxlinkage L lr :Rotorleakageinductance r :Electricalrotorangularspeed P :Polepairs T e :Torque 3.3CurrentRegulator ThemainpartsofthecurrentregulatorarePIregulator[12],feedforwardand anti-windup.TheFig.3.2showsthecompletestructureofacurrentregulator.The inputsignalsforthecurrentregulatorare: ~ i s;ref ,calculatedfromthereferencevalueofthetorqueandtherotorrux. 16

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Figure3.2:OverviewofCurrentRegulator ~ i s ,thestatorcurrentin dq -coordinates,whichisobtainedfromthetransformationsofthemeasuredphasecurrents. Theelectricalrotorangularspeed, r whichisobtainedbymultiplyingthe numberofpolepairswiththemechanicalrotorangularspeed. Theangularspeedandthemagnitudeoftherotorrux,whicharecalculatedby theruxestimator. Theoutputsignalfromthecurrentregulatoris: Statorvoltagesaturatedbythevoltagelimiter.Thislimitedvoltageisthen transformedusingInverseClarkeandParkandthentakentotheinverterand thenisappliedtotheinductionmachineasthree-phasevoltages. 17

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3.3.1CurrentReference Thecurrentreferencetermcanbederivedfromtherotorsideequationinthe equivalentcircuitas, 0= R r i e rd + p e rd )Tj /T1_1 11.955 Tf 11.955 0 Td ((! )Tj /T1_2 11.955 Tf 11.956 0 Td (! r ) e rq (3.13) where p isthedierentialterm.Sincetheterm e rq =0,theequationabovecanbe writtenas p e rd = R r i e rd (3.14) i e rd = e rd )Tj /T1_2 11.955 Tf 11.955 0 Td (L m i e sd L m (3.15) Usingboththeabovetwoequationsandconsideringasingle-orderdelaysystemi.e. p =0,thefnalexpressionwouldbe, i e sd = e rd L m (3.16) 3.3.2FeedForward FromthedynamicequationofthestatorcurrentsintheT-model,wehave V e qs =( R s + R r L 2 m L 2 r )i e qs + L s di e qs dt + e L s i e ds + r L m L r e dr (3.17) Itcouldbefoundthatthelasttermandlastbutonetermneedtoberemovedin ordertogetalinearrelationbetweenvoltageandthecurrent.Thefrstterminthe relationisusuallyknownastheresistivevoltagedropandthesecondterminthe relationisknownastheinductivevoltagedrop.Theexistenceofthethirdtermin therelationintroducesthecross-couplingbetweendandqcomponents.Alsothe fourthtermcomprisesofback-emfturns.Sincethecouplingandback-emfturnsare notexpectedduringthecurrentregulatordesign,afeedforwardsignalisappliedto eliminatethetwotermsanditisshownintheFig.3.2 18

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3.3.3VoltageLimiter Asweknowbasedontheprincipleofthethree-phaseinverterandPWM,the amplitudeoftheequivalentsinusoidalvoltageappliedtothemachineshouldbelimitedtothehalfoftheDC-linkvoltage.Thislimitationofthevoltagecanbedoneby usingvoltagelimiter.ThiscanbeseenintheFig.3.2Itshouldalsobenotedthat theamplitudeofthemodulationvoltageisexpectedtobesmallerthanthehalfofthe DC-linkvoltagebecauseheinverterwilloutputaconstantvoltageifthemagnitude ofthemodulationvoltageislargerthanhalfDC-linkvoltage.Inthisproject,as theDC-linkvoltageis48V,thepeakvalueofthephasevoltageissettobewithin +20Vor-20V.EvenafteryoutransformtheDCvectorstothree-phasesinusoidal quantities,thepeakvalueofthethree-phasequantityremainthesameandwillnever change.Thisiswhywesetthevoltagelimiterinacurrentcontroller. 3.3.4Anti-windup Therearesomeinstanceswhere,theoutputvoltageofthecurrentregulatormay notreachthevaluewhichisneededduetotheexistenceofthevoltagelimiter.Then thecurrenterrorbetweenthereferencecurrentandthefeedbackmightlettheintegratorofthePIregulatorintegratetoaverylargevalue.Eveniftheerrorisfnally reduced,itwouldstilltakelongtimefortheintegratortocometonormalvalue, whichgivesadelay[13]inthesignal.Thisphenomenoniscalledintegratorwindup problem.Inordertoovercomethissituation,thedierencebetweenthevoltagevaluesbeforeandafterthevoltagelimitersfedbacktotheintegratorthroughsomegain whichmakestheintegratorreset[14]everytimeandeliminatestheintegratorwindup problem. 3.4FluxEstimator Therearetwotypesofruxestimators,voltagemodelestimatorcurrentmodel estimator.ThestructureofanexampleruxestimatorcanbeseeninFig.3.3.The 19

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Figure3.3:StructureofFluxestimator currentmodelestimator,ismoresuitableforlowspeedapplicationdespiteofsensitivitytoparametervariations[15]ratherthanthevoltagemodelestimator.Asaresult, theruxestimatorusedinthisprojectisthecurrentmodelestimatorimplemented inIndirectFieldOrientation,whichindicatesthatthequantitiesusedfortherux estimationarecurrentstakenfromthe d )Tj /T1_1 11.955 Tf 10.638 0 Td (q system.Withthestator d and q currents andtheelectricalrotorangularspeedasinputs,theruxdeterminationequationsfor theestimatorcanbederivedas, d R dt = R R i d )Tj /T1_1 11.955 Tf 13.955 8.087 Td (R R L M R (3.18) 0= R R i q )Tj /T1_0 11.955 Tf 11.955 0 Td ((! 1 )Tj /T1_1 11.955 Tf 11.955 0 Td (! r ) R (3.19) where 1 )Tj /T1_1 11.955 Tf 11.592 0 Td (! r isthedierencespeedbetweenthesynchronousspeedandtheelectricalrotorspeed,theslipfrequency.TheFig.3.3illustratesthestructureoftherux estimator. 20

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3.5SpeedRegulator Figure3.4:SpeedcontrolRegulator Thedynamicequationofthemechanicalpartoftheinductionmotorcanbe expressedas d! r dt = )Tj /T1_2 11.955 Tf 10.494 8.088 Td (B J r + T e )Tj /T1_2 11.955 Tf 11.955 0 Td (T L J (3.20) where r :Themechanicalangularspeed T e :Torqueofthemotor T L :Loadtorque B :Frictioncoecient J :MotorInertia Thespeedregulatordesignisverysimilartothecurrentregulatordesign.Likein currentregulatordesign,thespeedregulatoralsohastheanti-windupsetup.But thisregulatordoesnothaveanyfeedforwardtermsbuthasthecurrentlimiteralike voltagelimiterincurrentcontrolregulator.Thecurrentlimiterhasthepeakvalue 21

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oftheratedcurrentofthemachinesincethemachineoperatingcurrentshouldnot exceedtheratedmachinecurrent.Toavoidlargeovershootsinthespeedresponse, anti-windupisadded.ThestructureofthespeedregulatorisshowninFig.3.4 Thespeedregulatorhastheoutputoftorquereferencewhichcanbeconvertedto q-current,whichactsonthemotorimmediatelyanddirectly.Sincetheinnercurrent loophasaveryhighbandwidth,thespeedloopshouldhavesmallerbandwidth. 3.6Simulation ThedesignatedvectorcontrolsystemisimplementedorsimulatedinMatlab/Simulink.Theblockdiagramofthevectorcontroldesignissameasthefgure shownbeforeandthestructuresofsub-blocksofthecurrentregulator,ruxestimator andspeedregulatorarealmostthesameasshowninthepreviousfgures.ButsometimesinSimulink,theintegratorblockaswellasthelimiterblockdoesnotaccept thecomplexvalues.Therefore,thecomplexnumberissplitintorealandimaginary part,whicharethendealtseparately.ThisprocessisillustratedintheFig.3.5For Figure3.5:IntegralofthecomplexnumberinSimulink thelimiter,thecomplexnumberisexpressedinpolarform,andthenthemagnitude ofthelimiterissaturatedasshowninFig.3.6Intheentirestagesofsimulation, thewholevectorcontrolsystemisbuiltwithSimulinkblocks.Theadvantagesof buildingthemodelwithSimulinkblocksisthatitisveryeasytoobserveavariable 22

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Figure3.6:Saturationofthecomplexnumberinsimulink byaddingascopewhereveritisneeded.Moreover,itismorerexibletomodifythe systemstructure. 3.7Discretization Allthedesignaboveisbasedoncontinuoustime.ButtheDSPdoesnotallow toexecutethecontinuoustimevaryingsignals.Therefore,thesignalsofeachblock havetobediscretizedfortheproperexecutionofDSP.Forexample,ifthecontrol loopperiodis0.1msec,thesamplingperiodhforthediscretizedsystemisselectedas 0.1msec.Atacertaintimeinstant t = kh ,inonecycleofthecontrolloopsampling takesplacefrstly,thenthesampledvaluesat t = kh arepasseddownintothe functionblockchain.Theneachblocktakesitsinputsignalsandstoredstatevariables intocalculation,derivesitsoutputtofeedintothenextblockandthengetitsstate variableupdatedforthenextiterationattimeinstant t =( k +1)h. Inthisproject,ForwardEulerapproximationisusedtotransformthecontinuous systemintodiscretesystem.With x(t)defnedasacontinuousvariable, x(kh)asits valueatthecurrenttimeinstantand x[(k +1) h]forthenexttimeinstant,asshown inFig.3.7thederivativescanbeapproximatedwithaforwarddierenceas[13] dx(t) dt = x[(k +1)h] )Tj /T1_2 11.955 Tf 11.955 0 Td (x(kh ) h (3.21) 23

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Figure3.7:ForwardEulerapproximation Figure3.8:IntegralformofForwardEulerapproximation TheintegralformofForwardEulerapproximationisshowninFig.3.8,wherethe areabelowthecurve x(t)canbeapproximatedtotheintegralofvariable x,denoted as X .Overtheintervalbetween kh and(k +1)h,theareabelowthecurveof x(t)is approximatedtotheareaoftherectanglewith x(kh)and h asdimensionofit.The 24

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integralof x(t)canbecalculatedas,byusingtheForwardEulerapproximation, X [(k +1)h]= X [kh]+ hx[kh] (3.22) Alltheequationswhicharecontinuoustimevaryingsignalsarepresentedinintegral formusingForwardEulerapproximation.Fortheblockscontainingdynamicparts likeintegrals,theaboveequationshouldbeusedintotheoriginalequationstoreplace theintegralstomakeitacompletelydiscretesystem. 25

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4.DSPProgrammingandCCSV5.5 TheintegratedinterfaceforanyuserdevelopingcodeinClanguageinthisproject istheCodeComposerStudiov5.5.CodeComposerStudio(CCS)[16]istheIntegratedDevelopmentEnvironment(IDE)forTIsmicrocontrollers.TIalsohasan integratedsolutioncalledthe ControlSUITE [17]whichconsistsofalltheheader fles,sourcefles,libraries,linkercommandflesforexecutingaprogram.Alsothe CodeComposerStudiohasmanyextensiveexamplesandexamplecodesthatmight helpanynewuserforaquickstartofdevelopingcode. ThedesignofinductionmotorvectorcontrolisshowninFig.4.1.Therearesome modifcationsandassumptions,however,intheactualdesign,duringtheimplementation.Someofthemodifcationsarefrstly,onlytwophasecurrentsaremeasured insteadofallthethreephases.Itissucienttotakethemeasurementsoftwophases fortheClarkeTransformation,ifthethreephasecurrentsarebalancedwiththeconditionof i a (t)+ i b (t)+ i c (t)=0[18].Ifthreephasesarebalanced,onephasecanbe calculatedfromtheothertwophases.Atthestartifthetesting,frst,V/Fcontrol isimplementedinordertotestthemotorfunctionalityandtheSimulink[19]blocks. TherowchartofthevariousstepsthattheDSPundergoesafterimplementingthe codeisshowninFig.4.2.Theprogram,asshowninfgure,startswithvariablesdeclarations,initializationsandconfgurationoftheusedhardwareintheDSP,start-up oftheinverterandosetmeasurement.Thelatterprocessisintheimplementation inthehardwarebutthestartingprocessdependsonthesoftware.AftertheDSP isconfgures,thePWMsequenceisstartedandtheprogramentersintoloop.In thisproject,thecontrolstrategyisdesignedsuchthat,thecontrolloopissynchronizedwiththePWMcarrierwave.EverystartofPWMperiodwilltriggeranADC sequence.TheADCsequenceconsistsofeightchannels,whichareusedtomeasure phasecurrents,faultcurrentsandfaultvoltagesandDClinkvoltages.Attheend ofADCsequence,theprogramjumpsintomeasuringthecurrentandspeedvalues, 26

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Figure4.1:ProgrammingDesign wheretheosetcompensationisadded.Followingthemeasurementcalculations,the vectorcontrolalgorithmisexecuted.Finally,thePWMdutycyclesareupdatedwith thenewcalculatedvaluesandtheprogramthenwaitsforthenexttriggerfromthe PWM.Inthefollowingsections,briefintroductiontotheF28335DSPisgivenand alsodescriptionaboutthehardwaremodulesaregiven.Inthissection,introduction totheDSPF28335isbrierystudied,followedbythemodulesdescriptionandalsothe featuresofDSP.ThePWMmoduleplaysanimportantroleinthisprojectbecause ofitsfunctioningtooutputthethree-phasesignalstotheinverter,decidethecontrol loopperiodandtosynchronizetheADC.Thisisthereasonwhymoredetailsare giveninPWMmoduleinthisdocument. 4.1OverviewofDSP ComingtotheperipheralsoftheDSP,theF28335DSPconsistsofa32-bitCPU andasingle-precision32-bitroating-pointunit(FPU),whichenablestheroatingpointcomputationtobeperformedinthehardware.AlsotheCPUoftheF28335 hasa8-stagepipelinestructure,whichmakestheCPUbeabletoexecuteeight 27

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Figure4.2:Flowchartoftheprogram instructionssimultaneouslyononesystemclockperiod.The150MHzsystemclockis providedbyanon-chiposcillatorandaphase-lockedloop(PLL)circuit.Theoscillator generates50MHzclocksignal,whichistripledto150MHzbythePLLcircuit.The F28335hasindependentlogicalmemoryspacesandseparatedmemorybusesforthe programandthedataasseeninFig.4.3.Thememorybusconsistsofaprogramread bus,adatareadbusanddatawritebus.ThephysicalmemoryoftheF28335consists of34Kx16single-accessrandomaccessmemory(SARAM),a256Kx16Flash,an8K x16read-onlymemory(ROM),a1Kx16one-timeprogrammablememory(OTP) 28

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andtheregisters.TheROMhasbeenpre-programmedbytheDSPmanufacturer. TheprogramexistingintheROMhasastandardprogrammingprocedureforDSP bootingaswellassomeoptimizedcodesforthemathematicalfunctions.Theregisters controlthebehavioroftheDSPandeachperipheralmodule.FortheF28335,reading fromorwritingtoregistersappliesthebit-feldaddressstructures.F28335alsohas thefeatureofdirectmemoryaccess(DMA).WiththeDMAbus,thedatacanbe passedfromonepartoftheDSPtotheotherpartwithouttheinteractionofthe CPU,whichincreasesthedatatransmissionspeed.Sinceitisdesignedmainlyfor applicationslikeours,theF28335hasplentyofperipheralcircuits.Forinstance, inourproject,themotorvectorcontroluses16-channel,12-bitADCmodule,the PWMmoduleandtheencodermodule.Alsotherearedierentcommunicationsthat couldbeachievedwiththeF28335,whicharecontrollerareanetwork(CAN)module, theserialcommunicationinterface(SCI)module,theserialperipheralinterface(SPI), themultichannelbueredserialport(McBSP)moduleandtheinter-integratedcircuit (I2C)module.F28335,also,supports96interrupts.Theseinterruptsaregovernedby theperipheralinterruptexpansion(PIE)block,whichhelpsinenablingordisabling theinterrupts,decidetheinterruptprioritiesandinformtheCPUoftheoccurrenceof anewinterrupt.TheF28335hasthejointtestactiongroup(JTAG)interface,which helpsusinreal-timedebugging.WiththehelpofthisJTAG,anyonecanlookand modifythecontentsofthememoryandtheregisterswithoutstoppingtheprocessor. Thissectionexplainsaboutdierentmodules. 4.1.1ADCModule TheblockdiagramforADCmodule[20]confguredinF28335isshowninFig.4.9. Itconsistsof16analoginputchannels,whichareconnectedtoananalogmultiplexer (MUX).Thechanneltobesampledcanbeselectedbysendingitscorresponding4bitaddresstotheMUX.Therelationsbetweenthechannelsandthe4-bitaddresses arelistedinTable.4.1.FromtheFig.4.9,wecanobservethattheanalogMUX 29

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Figure4.3:BlockdiagramofADCmodule[1] consistsoftwo8-to-1multiplexers,MUX1andMUX2.Theoutputsfromthetwo multiplexersareconnectedtotwosampleandhold(S/H)circuits,S/H-AandS/H-B, respectively.ThetwoS/Hcircuitsallowthepossibilityofsamplingtwoanalogsignal simultaneously.AftertheS/Hcircuithasdonethesampling,theanalog-to-digital converterbeginstotransfertheanalogsignalheldontheS/Hcircuitintoa12-bit binarynumber.TheentirefunctioningoftheADCisgovernedbytheADCcontrol registers.TherearesequencerblocksintheADC,Sequencer1andSequencer2.These twosequencersarethenmergedintoacascadedsequencer,wheremaximumsixteen channelscanbeselected.Thesetwosequencersareplacedinanappropriateorderand eachsequencermaximumofeightchannelscanbeselected.InordertostartanADC sequence,astart-of-conversion(SOC)signalisneeded.Forsequencer1andsequencer2 orcascadedsequencer,theSOCsignalcouldbegivenbythePWMmoduleorthe bitS/W,whichcanbesetorresetinthesoftware.Sequencer1andthecascaded sequencercouldalsobetriggeredbyanexternalsignalthroughageneral-purpose 30

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Table4.1: ADCinputchannelsandcorrespondingaddresses Input Address Input Address Channel S 3 S 2 S 1 S 0 Channel S 3 S 2 S 1 S 0 ADCINA0 0000b ADCINB0 1000b ADCINA1 0001b ADCINB1 1001b ADCINA2 0010b ADCINB2 1010b ADCINA3 0011b ADCINB3 1011b ADCINA4 0100b ADCINB4 1100b ADCINA5 0101b ADCINB5 1101b ADCINA6 0110b ADCINB6 1110b ADCINA7 0111b ADCINB7 1111b input/output(GPIO)pin.TheADCclockfrequencydecidesthetimetotakeforone conversion.TheADCclockisobtainedbyprescalingthesystemclock.Thisisdone indefaultifyousettheDSPasF28335.Thetotalprescalingfactorisequaltothe productoftheprescalingfactorsofthehigh-speedprescalar,theADCclockprescalar andtheextraprescalar.Theconversionresultswillbewillbewrittenintotheresult registers,througharesultselectionMUX.Foreachsequence,theresultselection MUXwillsendthefrstconversionresulttoResultReg0,thesecondonetoResult Reg1andsoon,untilthissequenceisfnished.Wheneverthecomplexconversions occurlikeanalog-to-digitalconversionsareneededintwodierentmomentsduring onecontrol,thedual-sequencemodecanbeapplied.Inthisproject,alltheanalog signalsaresampledatthesamemomentandthenumberofanalogsignalsisless thaneight.Duetothis,onesequenceofconversionpercontrolloopisenough.But cascadedmodeofoperationisstillapplied,whichcanleaverexibilitytothechannels andDSPpinsassignment.Sometimesitisrequiredthatalltheanalogsignalsare 31

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Figure4.4:ADCmoduleconfgurationsetupinthisproject[1] sampledatexactlywhenthePWMcarrierwavereachesitspeak.Butsincethere areonlytwoS/Hcircuits,inthepracticalimplementation,thetwophasecurrents phaseAandphaseBaresampledfrstlyandthentheotherparametersaresampled. ThesamplingmodeoftheADCmoduleshouldbesimultaneous.TheADCclock frequencyisbettertobehigh,fromthepointofconversionspeed.ButtoohighADC clockfrequencymightcausesomenon-linearitytotheconversionresults[21].So 12.5MHz,thehighestADCclockfrequencyisrecommendedandisbeingsetinthis project.Anotherissuethatmightbenoticedisthewidthofthesamplingwindow, whichisdefnedasthenumberofclocksthattheS/Hcircuitspendsonsamplingthe signal.Forthesignalsthatchangeveryslowly,awidersamplingwindowmightwork perfectbringingtheadvantageofremovingthenoisebyaveragingtheinputsignal. Butinthisproject,sincethecurrentschangeveryfast,widesamplingdoesnot 32

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work,insteadsmallestsamplingwindowofoneADCclockisapplied.ThentheADC moduleshouldworkinstart/stopmode,whichmeansthattheconversionisstarted bytheSOCsignalandstopswhenthesequenceisfnished,waitingforthenextSOC signal.TheSOCsignalistriggeredbythePWMmodule.Finally,aninterruptservice routinehastobegeneratedbytheADC,oncethesequenceisfnished.Thevector controlalgorithmwillbeexecutedintheInterruptServiceRoutines(ISR).Theblock diagrambasedontheADCmoduleconfgurationsdescribedaboveinthetheoryis showninFig.4.10.Insimultaneoussamplingmode,apairofconversionscountsfor one.AlsotheADCcountsfrom0insteadof1,sothevalueofthe MAX CONV should becalculatedas MAX CONV =[ No:ofConversions 2 ] )Tj /T1_0 11.955 Tf 11.955 0 Td [(1(4.1) ThissectionexplainsaboutPWMmodule. 4.1.2PWMmodule TherearesixindependentenhancedPWM(ePWM)modulesintheDSP.The enhancedPWMmeansthatitcangeneratecomplexPWMwaveformwiththeleast CPUresourcesoccupied[22].EachoftheePWMmodulehastwooutputchannels: ePWMxAandePWMxBbelongingtotheePWMxmodule.EachePWMmodule containssevensubmodules,whichcanrealizedierentfunctionsinthegeneration ofPWMwaveforms.Theyaretime-base(TB)submodule,counter-compare(CC) submodule,action-qualifer(AQ)submodule,dead-band(DB)submodule,PWMchopper(PC)submodule,tripzone(TZ)submoduleandevent-trigger(ET)submodule.TheFig.4.4showsthecompletestructureofasingleePWMmodulewitheach submodulebetweenthesubsections.Inthisproject,notallbutsomeofthemare usedforvariousaccomplishments.Thefollowingsectionswillbrierydescribethe ePWMmodulesindividuallytogetaclearideaofhowtheePWMfunctions. 33

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Figure4.5:BlockDiagramofF28335[2] 4.1.2.1Time-basesubmodule Thefunctionoftime-basemoduleistotakechargeoftheeventtimingforits ownePWMmodule.Thestructureandblockdiagramofthetime-basesubmodule containingregistersisshowninFig.4.4.Themainfunctionofthetime-basesubmoduleistofndthePWMtime-baseblockrelativetothesystemclock.ThePWM time-baseclockistoregulatethetimingofalltheeventsinthePWMmodule.The systemclockperiodisdefnedas T SYSCLKOUT andthetime-baseclockisdefnedas T TBCLK .Thetime-baseclockperiodcanbescaledtomanytimesofthesystemclock 34

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periodas: T TBCLK = T SYSCLKOUT CLKDIV HSPCLKDIV (4.2) where CLKDIV and HSPCLKDIV arebitsinthetime-basecontrolregister (TBCTL)thathelpstosetthetime-baseclockpre-scale. Thetime-basesubmoduleisalsousedtospecifytheperiodofthetime-base counter(TBCTR)dependinginwhichmodeitisoperating.Therearethreemodes ofoperationforthetime-basesubmodule,whichcanbeselectedintime-basecontrol register(TBCTL),namelyup-countmode,down-countmodeandup-downmode.In thefrstmodeandthesecondmode,TBCTRalwayskeepincrementingordecrementingallthetimegivingasawtoothcarrierwave.Butthethirdonei.e.up-down mode,theTBCTRincrementsinthefrsthalfofthePWMperiodandthendecrementsthesecondhalfpartofthePWMperiodgivingatriangularcarrierwave.The maindierenceoftheup-downmodeisthatinoneperiodthecounterchangesina symmetricalfashion,wherethecorrespondingmovementtothePWMcarrierpeak timeiseasilyfound.ThepeaktimeofthePWMcarrierwavehastobeknownfor signalsamplingandthatisthereasonwhyup-downmodecountmodeisusedinthis project.ToobtainthedesiredPWMfrequency,thevalueintime-baseperiodregister(TBPRD)issupposedtobedetermined.Forup-down-countmode,therelation betweentime-baseperiodandPWMfrequencycanbewrittenas: T PWM =2 TBPRD T TBCLK (4.3) f PWM = 1 T PWM (4.4) where T PWM standsforPWMperiodand T TBCLK fortime-baseclockperiod.From theaboverelations,thevalueinthetime-baseperiodregistercanbedeterminedas follows TBPRD = 1 2 f SYSCLKOUT f PWM CLKDIV HSPCLKDIV (4.5) 35

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ThereforetheonlyparametersthathavebeknowntocomputeTBPRDareDSP systemclockfrequencyandthedesiredPWMfrequency.Theparametersthathave beenusedinthisprojectfortheconfgurationofDSParePWMfrequencyof10 kHzandthesystemclockfrequencyoftheDSPF28335is150MHz.Thevaluesfor CLKDIVandHSPLCLKDIV,usedinthisprojectare1and1forconvenience.From theaboveequation,thevaluesetinthetime-baseperiodregistercanbecalculated directlyasshownbelow. TBPRD = 1 2 150M 10k 1 1 =7500 (4.6) Besides,synchronizationbetweendierentePWMmodulescanalsoberealizedin thetime-basesubmodules.Thethree-phasePWMisusedtoproduceathree-phase alternatingvoltage,hencethesynchronizationbetweenthethree-phasePWMsignals isveryimportant.EachePWMmodulehastwosignalforsynchronizationbetween dierentePWMmodules.OneissynchronizationinputEPWMxSYNCIandsecond issynchronizationoutputEPWMxSYNCO.TheFig.4.5showstime-basecounter synchronizationschemeforF28335.ItcanbeseenthatthePWMmodulesareconnectedinserieswiththesynchronizationoutputEPWMxSYNCOoftheprevious onefedontothesynchronizationinputEPWMxSYNCIofthenextone.Onlythe inputsynchronizationforthefrstePWMmoduleistakenfromanexternalpin. ForeachePWMmodule,onceapulsefromthesynchronizationinputisdetected,the valueinthetime-basephaseregister(TBPHS)willbeloadedintotime-basecounter (TBCTR),wheretime-basephaseregister(TBPHS)willbeloadedintotime-base register(TBPHS)isusedtostorethetime-basecounter(TBCTR)phasevalueofthe ePWMmodulewithrespecttothetime-baseofitssynchronizationinputsignal.As weknowthattheinverteroutputarethreephasevoltageswhichareleadingorlagging eachotherby120,thisisnotgoingtoshowupintheprojecti.e.thethreePWMsignalshavethesamephaseatanymoment.TheePWMmoduleePWM1,ePWM2and ePWM3areselectedforthethree-phasePWMgeneration.Hencethetime-basephase 36

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Figure4.6:InternalmodulesofePWMandtheirconnections[3] register(TBPHS)fortheePWMmodulesareassignedthevalueof0.Itmeansthat thereisnophaseshiftbetweentheoutputsignalePWM1A,ePWM2AandePWM3A. TosynchronizebetweendierentePWMmodules,thesynchronizationoutputselect bit(SYNCOSEL)inthetimebasecontrolregister(TBCTL)issupposedtobeconfgured.ePWM1isdefnedasthemasterphasetogenerateasynchronizationoutput EPWM1SYNCOpulseeachtimeitstime-basecounter(TBCTR)equalszero,while ePWM2isdefnedasaslavephasewhosesynchronizationinputEPWM2SYNCI signalisenabled.Meanwhile,ePWM2ssynchronizationoutputEPWM2SYNCOsig37

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Figure4.7:TimebasecountersynchronizationschemeforF28335 nalissetequaltoitssynchronizationinputEPWM2SYNCisignaltodriveitinto ePWM3unit.ExceptePWM1,theothermodulesePWM2andePWM3havetoload thetime-basecounter(TBCTR)withthetime-basephaseregister(TBPHS)whena synchronizationinputEPWMxSYNCIpulseappears. 4.1.2.2Counter-comparesubmodule Morepracticallyapproachingthethings,thePWMwaveformgenerationismainly achievedbythecomparisonbetweenacounter(TBCTR)value(carrierwave)anda set-point(referencewave)whichisstoredincounter-compareregister.Fig.4.6shows thewaytogenerateaPWMwaveform.InthePWMwaveformgenerationprocess,the counter-comparesubmodule(CC)takesthepartofeventgeneration,whiletheaction qualifertakesactiononotherthings.Incounter-comparesubmodule,therearetwo counter-compareregisters:counter-compareAregister(CMPA)andthecountercompareBregister(CMPB)tostorethevalueswhichareusedtocomparevalues againsttime-basecounter(TBCTR)submodulecontinuously.Thetime-basecounter (TBCTR)istreatedastheinputwhilethegeneratedeventTBCTR=CMPAor TBCTR=CMPBistheexpectedoutput.TheFig.4.6showthewayitisdone 38

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inthisproject.Wheneverthecarrierwavehitsthecounter-compare(CMPA)value ontherise,theePWMxAissettooandwheneverthecarrierePWMxAhitsthe counter-compare(CMPA)valueonthedown-count,ePWMxAissettoon.This processisexplainedinactionqualifersubmodule. Figure4.8:Counter-compareevent,up-downcountermode 4.1.2.3ActionQualifersubmodule Theactionqualifersubmoduletakesactionwheneverthegeneratedeventsfrom theprevioussubmodulesareavailable.Theprevioussubmodulesthathavetogenerateeventsaretime-basesubmoduleandcounter-comparesubmoduleandhencethese twosubmoduleeventsaretheinputstotheactionqualifersubmodule.Thefrstone generateseventTBCTR=0andTBCTR=TBPRDwhilethesecondoneproduces TBCTR=CMPAandTBCTR=CMPB.Havingtime-basecounter(TBCTR)state incrementingordecrementing,thefoureventsareexpandedintoeighteventcombinations.Whenaspecifedeventtakesplaceoutoftheeightevents,therearefour possibleactionstobetriggeredwhethertosetithigh,tolow,totoggleandtodo nothing,whichcandeterminetheshapeofthePWMwaveform.Theactionqualifer 39

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outputcontrolregister(AQCTLA)isusedtodefnetheactionsthatshouldbetaken ifspecifedeventsoccur.TheconditionsthatareselectedinthisprojecttobeconfguredsuchthatwhenTBCTR=CMPAandTBCTRisdecrementing,ePWMxA issettohigh;whileTBCTRisincrementing,ePWMxAisclearedlow.Thearrows inthefgureshowsthedirectionoftime-basecounter. 4.1.2.4Deadbandsubmodule BynowwehavetheePWMxAsignalgeneratedbytheactionqualifersubmodule. Wealsorequireacomplimentarysignalwhichisrequiredtofeedboththeupperand lowerIGBTsinthesamelegoftheinverter.Thedeadbandsubmodulecanbeused totaketheePWMxAasthesignalsourceandthentoproducethetwomutually complimentaryPWMoutputsasePWMxAandePWMxB.ThestructureofdeadbandsubmoduleisshowninFig.4.7.Thefunctionofdeadbandsubmoduledepends onthesixswitchespresentinit.Dierentcombinationsoftheswitchesgenerate dierentmodesforsignalpairs.Sincetherearesixswitches,manycombinationscan beproduced.Butinthisproject,wedontusemanyofthem.Thereasonbehind insertingthedeadbandintotheidealPWMwaveformistoavoidthetwoIGBTs onthesamebridgelegoftheinverterturnedonsimultaneously.Thereforeoperating modeActiveHighComplementary(AHC)isselectedasthedesiredoneforapairof powerswitchesinonephaseofa3-phasemotorcontrolsystem,whichcanbeachieved bysettingthestatesoftheswitchesinFig.4.7,whichcanbeconfguredindeadband controlregister(DBCTL).InFig.4.7,arisingedgesdelayblockandafallingedges delayblockareusedtoinsertarisingedgedelayorafallingedgedelayintothe originalPWMoutput.WiththeswitchS4andS5setto0,ePWMxAischosenasthe inputsourceforbothoutputAandB.BysettingswitchS2to0andS1to1,arising edgedelayisinsertedintotheoriginalePWMxAsignal;bysettingswitchS3andS0 to1,ePWMxAsignalisreversedwithafallingedgedelayadded,whichisoutputas ePWMxBsignal.ThegeneratedPWMsignalinActiveHighComplimentarymodeis 40

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Figure4.9:BlockdiagramofePWMdeadbandsubmodule showninFig.4.8.Itcanbeobservedthatthereisanextremelyshortperiodofeach PWMperiod,whenbothoutputsoftheePWMxmodulearecleared,whichavoids themutuallycomplimentaryPWMsignalsaresethighatthesametime. 4.1.2.5EventTriggersubmodule TheoccurrenceofeventsofADCandPWMshouldbesuchthatthePWM outputshouldtriggertheADCstartofconversion.Butsometimesinasampling period,theADCstartofconversionisexecutedfrst,thenthesampleddataisused tocalculatethePWMoutput.Thisshouldnthappenwhichmightreturninwrong results.ThereforeADCandPWMsignalsshouldbesynchronizedtofunctioninthe samepace.TheeventtriggersubmoduleinePWMistoissueinterruptrequestor ADCconversionafterreceivingeventinputs.Inordertoavoidaliasingfromcurrent ripple,thecarrierwavepeaksarealwayschosenasthesamplingtimeinstants.Both TBCTR=0andTBCTR=TBPRDcanmeetthisrequirementandsampling.In thisproject,TBCTR=0isdefnedastheeventthattriggersADCstartofconversion AbyEPWMxSOCApulse.ItisnotrequiredtosampleatbothatTBCTR=0and 41

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Figure4.10:WaveformofPWMwithdeadbandinserted TBCTR=TBPRD. 4.1.2.6Dutycyclecalculation ThemostimportantpartofthePWMgenerationisthedutycycle.Thevalue enteredinthecounter-compareregistercorrespondstothedutycycleofthePWM period.Sothecounter-compareeventregister(CMPA)needstobeupdatedoncein eachPWMperiodtogeneratethePWMwavewithvaryingdutycycle.Therelation betweenthevaluessetinCMPAregisterandPWMdutycyclecanbewrittenas: CMPA = TBPRD (1 )Tj /T1_2 11.955 Tf 11.956 0 Td (D )(4.7) Allthesubmodulerolesareintroducedinprevioussections.Thespecifcoutputvalue oftheinvertershouldbeequaltothedigitalsignalgivenbytheDSP,atanypoint oftime.Forinstance,letustakeanextremesituationcase,phaseA.Theoutput voltageforphaseAiscontrolledbyswitchS1andS4andthePWMsignalsimposed onS1andS4aremutuallycomplimentary.TheVdcisdefnedastheDClinkvoltage 42

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fortheinverter.DuringasamplingperiodofthePWM,theswitchS1isturnedon andswitchS4isturnedoforthesameperiod.Italsocanbesaidinthiswaythat, thedutycycleofthePWMwavefedtoswitchS1is100percent,theoutputvoltage ofphaseAshouldbe+ V d c=2;ontheotherside,iftheswitchstaysoandswitchS4 isturnedonforthewholecycle,thedutycycleforswitchS1is0percent,theoutput voltageofphaseAturnstobe Vdc= 2.Andifboththeswitchesareonforonehalf ofthecycleperiod,theaveragevoltageofphaseAissupposedtobe0.Fromthe principleofPWM,asthecarrierwaveofthemodulationistriangularwave,fromthe basicgeometricalknowledgeitcanbefoundthattherelationbetweentheoutput phasevoltagefromtheinverterandthecorrespondingPWMdutycycleislinear.In general,ifthePWMdutycyclestandsatanyonepointintherangefrom0to1,the outputvoltageforphaseA,canbewrittenas: V a =( +V dc 2 ) D a +( )Tj /T1_1 11.955 Tf (V dc 2 ) (1 )Tj /T1_1 11.955 Tf 11.955 0 Td (D a )(4.8) where D a isdenotedasthedutycyclefortheupperIGBTofthebridgelegconnected tophaseA.Fromtheaboverelation,thedutycyclecanbewrittenas D a = V a + V dc 2 V dc (4.9) ThecomplimentaryPWMwaveformePWMxBforthelowerIGBTonthebridgeleg canbegeneratedbyreversingePWMxAinthedeadbandsubmodule.Henceonlyone counter-compareregister(CMPA)isrequiredforthegenerationofonepairofPWM outputsonthesamebridgeleg.Fromtheaboverelations,thevaluesetinCMPA canbeeasilycalculated.Thisprocessappliestoothertwophases.Asaresult,the dutycyclesforthreephasescanbederivedas CMPA a = TBPRD a (0:5 )Tj /T1_1 11.955 Tf 14.915 8.088 Td (V a V dc )(4.10) CMPA b = TBPRD b (0:5 )Tj /T1_1 11.955 Tf 15.352 8.087 Td (V b V dc )(4.11) 43

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CMPA c = TBPRD c (0:5 )Tj /T1_0 11.955 Tf 15.33 8.088 Td (V c V dc )(4.12) Thesubscriptimpliesthephasethattheregistervaluesbelongto. 4.1.3EncoderModule Theenhancedquadratureencoderpulse(eQEP)module[23]oftheF28335is usedtoprocessthedigitalsignalformtheencoderbuiltontopofthemotor.There arefourdierentmodesinwhichthequadraturemoduleisabletorun.Theyare quadraturemode,directcountmode,upcountanddowncountmode.Inquadrature mode,theeQEPmodulereceivestwosquarewavesignalsfromtheencoder.These twosquarewavesignals(AandB)have90phaseshiftwithrespecttoeachother, whichcanbeusedtodeterminetherotationdirection.IfsquarewaveAisleading withrespecttosquarewaveB,thentherotationissaidtobeinclockwisedirection andontheotherside,ifthesquareBisleadingwithrespecttosquarewaveA, thentherotationissaidtobeinanti-clockwisedirection.Indirection-countmode, onesquarewavesignalandonedirectionsignalaresenttotheeQEPmodule.The counterinthemodulewillincreaseordecreasedependingonthedirection.Forboth modes,anindexpulsesignalisusedtodeterminetheabsolutepositionoftheencoder. TheoperatingmodeoftheeQEPmoduleisselectedbythetypeofencoder.Asthe incrementalencoderisusedinthisprojectoutputsthequadraturesignals,theeQEP moduleissettobeworkinginquadrature-countmode.Thegeneralblockdiagram ofeQEPmoduleisshowninFig.4.11whichshowsthefunctionalityoftheencoder. TwoquadraturewavesaresenttotheQApinandQBpinofthedecoderblock asshownintheFig.4.11.EveryfallingorrisingedgeofQAandQBwillgenerate aclocksignal(QCLK),whichispassedtothepositioncounter(QPOSCNT)from thedecoder.TheQPOSCNTwillincreaseordecreaseby1unitoneachpulseof QCLK,dependingonthedirectionsignal(QDIR).Iftherotationisclockwise,the QPOSCNTwillincreaseby1unitforeverypulse.Iftherotationisanti-clockwise, theQPOSCNTwilldecreaseby1unitforeverypulse.ThefollowingTable4.2show 44

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Figure4.11:BlockdiagramofeQEPmodule[4] thedetailsofthevaluesofQDIRandQPOSCNT.Fig.4.12showstheexample waveformoftheeQEP,whichhasthequadratureQAandQBpins,indexpulses. Everytimethepositioncounter(QPOSCNT)isresetbytheindexsignal.Whenit meetstheindexsignalforthefrsttime,theeQEPmodulewillrememberthepresent edgeandtherotatingdirectioninthefrstindexmarkerregister. Forinstance,ifthefrstcounterresethappensonthefallingedgeofQBduring theclockwisedirection,thenallthelaterresultsmustbealignedwiththefallingedge ofQBfortheclockwisedirectionandwiththerisingedgeofQBfortheanti-clockwise direction.Thepositioncountercanberesetbytheoverroworunderrowofitself. Forunderrowthelimitingvalueiszero.Fortheoverrow,theupperlimitingvalue isQPOSMAX,whichisthevaluestoredintheQPOSMAXregister.Thisvalueis setintheeQEPmoduleintheproject.Ifyoudonotsettheunderroworoverrow, thecounterisautomaticallyresetto0duringtheclockwiserotationandresetto QPOSMAXduringtheanti-clockwiserotation.Iftheperiodofthevectorcontrol loopissettot,thentherotatingspeedoftheencodercanbecalculatedas Speed = 1s t 60rpm (4.13) 45

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Table4.2: EncoderTruthtable Previous Presen t QDIR QPOSCNT Edge Edge QB" 1 incremen t QA" QB# 0 decremen t QA# TOGGLE incremen tordecrement QB# 1 incremen t QA# QB" 0 decremen t QA" TOGGLE incremen tordecrement QA" 1 incremen t QB" QA# 0 decremen t QB# TOGGLE incremen tordecrement QA# 1 incremen t QB# QA" 0 decremen t QB" TOGGLE incremen tordecrement Thisconditionappliesiftheencoderrotatesonerevolutionduringonecontrolloop period. 4.1.4OsetMeasurement Generally,boththecurrentandspeedmeasurementscontainasmalloset,which isduetothepresenceofsensorsortheADCconditioningcircuit.Theseosetofeither thecurrentsorthespeedshouldbemeasuredwhenthemachineisinstandstillmode withalltheothermodulesordevicesswitchedon.Themeasuredosetcurrentfrom thethreephasesshouldbesubtractedfromtheADCresultsinthecodetocompensate forthecurrentoset.Inordertogetthesamplesofcurrentoset,theDSPisallowed tosettleforsometime,allowDSPtoruninsteadystateandthentheosetcanbe senttotheoscilloscopeorcanbemeasuredbytakingmanysamplepersecondand takingaverageofthem.Thespeedosetcanbedoneusingthesamewayasthe currentoset. 4.2HardwareSetup AnexperimentalsetupisdesignedintheEnergyandPowerlabinordertoimplementthesimulinkcodeontotheDSP.Fig4.13showsthesetupthathasbeen 46

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Figure4.12:AnexamplewaveformoftheeQEP(anti-clockwiserotation) usedfortheproject.Theideaofthesetupistohavealltheequipmentnamelypower supplies,inverter,DSPboard,transformersandthemotoronthesameplatform. Thesetuphasaccesstolimitedinputportsandoutputportswhichareusedinthis project.Therearetwoswitchingpowersuppliesinthesetupoutofwhich,oneacts Figure4.13:HarwareSetupinthelab astheinputsourceforinverter(48VDC)andtheotheractsasinputsourceforDSK board(24VDC).Sincetheinputvoltagefortheinverteris48VDC,themaximum 47

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voltagethatcanbeobtainedfromtheinverteris24V(Vdc/2).Theoutputofthe inverteristhenboostedupto240Vusingthreeboosttansformers.Thetransformer connectionsaredelta-deltaconnected.ThePWMsignalsgenerateddigitallyandthe analogvaluesintheDSKaresenttotheinverterusingbuscablesasshowninthefg. 4.13.TheDSPisemulatedusingUSBJTAGemulatorthroughwhich,theprogram inthecomputerissenttotheDSP.TheDACpinsatthebottomofthefgureare usedtoreceiveoutputsignalssuchasvoltages,currentsandspeed.AserialCommunicationsinterfaceissetupandconnectedtocomputerwhichenablestheserial(one bitatatime)exchangeofdatabetweentheDSPandthecomputer. 4.3SystemInitializationandConfgurationofCCSV5.5 4.3.1Initialization Afterswitchingthepowersupplyon,theDSPhastobeinitialized.Thealready installed controlSUITE supportsanyuserwithinitializationfunctionscorresponding toeachfunctionunit.Theinitializationfunctionsonlyprovidethemostbasicsupportsforrunningthesystem,forexampletoinitializethesystemclockortoenable somemodules. 4.3.2Confguration Themodulespresentinthedesigncanrunindierentmodesdependingonthe application.Butforthisproject,torunourapplication,themoduleunitsareconfguredtosuitableoperatingmodeasshowninbelowsections.Eachmoduleistaken individuallyandboththeCcodeandtheSimulinkcodearepresentedtoillustrate thedierenceinconfgurationsetting.Thetables4.3,4.4and4.5showstheconfgurationssetinthisprojectineachmodule. 48

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Table4.3: ConfgurationofADC ADC Clock 12.5MHz Sampling mode Sim ultaneous Op eratingMode Start/Stop No. ofConversions 8 Sampling mode 1 ADCClock Sequence mode Cascaded T riggerSource PWM In terrupt P ostSequence (a) (b) Figure4.14:SimulinkcodeconfgurationforADC Table4.4: eQEPconfguration Maximumpositioncountervalue 4294967295 PositiveRotation ClockwiseRotation Positivecountermode Quadrature-count Gatingoption OnIndexpulse Positioncounterresetmode Onmaximumvalue 49

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(a) (b) Figure4.15:SimulinkconfgurationforeQEP Table4.5: ePWMconfguration PWM frequency 10kHz Op eratingmode Shado wmode Sync hronizationmode series Phase shift 0 CTR mode Up-do wn Load mode CTR=0 ADC trigger CTR=0 50

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Figure4.16:SimulinkconfgurationforePWM 51

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Figure4.17:SimulinkconfgurationforePWM 4.3.3ConfgurationofCCSV5.5 Asdiscussedearlier,CodeComposerStudioisanIntegratedDevelopmentEnvironment(IDE)thatsupportsTexasInstrumentsMicrocontrollersandEmbedded Processors.Itconsistsofallthetoolsthatareusedtodevelopandthendebugembeddedapplications.CodeComposerStudioalsocontainsoptimizingC/C++compiler, sourcecodeeditor,projectbuildenvironment,debugger,proflerandmanyotherfeatures.TheIDEprovidesasingleuserinterfacetakingyouthrougheachstepofthe applicationdevelopmentrow.Gettingfamiliarwithallthetoolsandfeaturesofthe softwaremakesiteasier.CodeComposerStudiocombinesadvantagesoftheEclipse 52

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softwareframeworkwithadvancedembeddeddebugcapabilitiesfromTIresultingin ahighlyrichdevelopmentenvironmentforembeddeddevelopers. Thefguresbelowandthetheorycorrespondingtothefgureshelpsanewuserto confgureCCSv5.5atanypointoftime.TheearlyprocessofconfguringCCSv5.5 istogenerateamakefle,whichisusedtoautomatebuildingandthendeployingthe softwareontargethardware. 4.3.3.1MakefleSetup IfthecontroldesignisdoneinSimulink,navigatetothecommandpromptwindow,whereyoucanseeacommandentersignalas >>.Ifyouseethatsymbol,enter thecommandxmakeflesetupintheMatlabcommandwindow.Thecommandpops upthedialogboxwhichisshowninFig.4.13 Figure4.18:MakefleconfgurationinMatlab Ifthedialogboxdoesnotshowupinthesamewayastheabovefgure,thenthe 53

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thingsthatshouldbetakencarearethecloneconfgurations.Theinstructionsfor achievingthisconfgurationare:Firstly,clearthecheckboxfordisplayoperational confgurationsonlyandclickonthe New confgurations,whichshouldpopadisplay boxshowingthenamesoftheconfgurations.Selecttheappropriateconfgurations fortheapplicationandthenitcreatesaconfgurationthatcanbeappliedforthe project. 4.3.3.2ConfgurationParameters Inthissection,abriefdiscussionaboutsettingtheconfgurationparametersin ordertogenerateanoutputfle,whichisappropriateandsuitablefortheDSPthatis beingusedinthisproject.Comingtothesolverpaneoftheconfgurationparameters, thevaluesshouldbeselectedforthestartandstoptimesofthecodeandalsothesolver typeshouldbeselected.Theparametersthathavebeenusedforthisprojectarethe fxedstepsolveranddiscretesolver.Someoftheparametersaresetbydefaultandare notnecessarytobemodifed.However,itdependsontheapplicationused.Coming tothehardwaresection,thehardwarethatisbeingimplementedinthisprojectis theTexasInstrumentsProductandthedeviceisaC2000familytype.Underthe Codegenerationpane,itshouldbenoticedthatthesystemtargetfleisselectedas idelink )Tj /T1_1 11.955 Tf 11.579 0 Td [(grt:tlc.Bydoingitthatway,thesystemlinkstheIDEenvironmenttothe targethardware.Alsoanewpanecalledcodertargetpaneisavailable,whereallthe parametersabouttheactualhardwareareupdated.Lateronunderthecodertarget pane,thebuildformatissettomakefle,sincetheoutputformatweselectedearlier fortheembeddedtoolwasmakefle. TheactionissettoBuildandExecute,whichenablesthesystemtobuildanexecutablefle.ThisprocessalmostsetstheconfgurationofCCSv5.5ontothesystem andyouarereadytogo.BeforeyoustartbuildingthecodeonCCSv5.5,justmake suretohaveeverythingcorrect,incaseyouhadsomethingnotfxed.Thefrsttime youuseembeddedcoderwithCodeComposerStudio,youshouldcheckthattheCCS 54

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isinstalledandconfguredproperlyandalsohasatleastoneboardconfgured.To dothat,enterthecommand ccsboardinfo intheMatlabcommandpromptwindow. Matlab,thenreturnsalltheboardsthatareconfguredandrecognizedbytheCCA asshownasbelow. Also,ifnecessarycheckallthethirdpartytoolsandenvironmentvariablesthat aresetintheconfgurationusingthecommand checkEnvsetup(ccs;f 28335;check ). TheFig.4.14showstheenvironmentvariablessetinthisproject. Figure4.19:Environmentvariablesdefnedintheproject Thenextsectionexplainsabouttheincrementalbuildtechnology. 55

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4.4IncrementalBuildTechnology Eventhoughtheprogrammingisdonebyevaluatingeachblockatatime,like modularprogramming,sometimesitisdiculttodebugifallthemodulesarelumped togetheratatime.Therefore,theprogramstructureisbuiltlevelbylevel.Every timebeforebuildinganewlevel,theoldlevelshouldbeworkingcorrectly. 4.5TroubleshootingDSP Sometimes,theremightbeerrorsinthecodethatleadstodamageintheDSK board,whichmightbeissueinmanycases.Inthissection,briefdiscussionaboutsome ofthedamagesthatcouldbedonetotheDSPandthetroubleshootingtechniquesto repairtheDSPareexplained. Forthefrstcase,letustakeanexampleofhavingexcesscurrentrowingin thecircuitsofDSK,whichmightresultinthedamageodsomeofthepartsinthe DSK.IfyouexperiencebadsmellfromtheDSKboardoranunpleasantsmellfrom theboard,immediatelyturnthesystemo,asthereissomeprobleminthecode. ComingtotroubleshootingtheDSP,frstly,checkthepowercircuitunderneaththe DSKboardandyoucanseethecircuitleadingfromthe24Vpowersupplytothe 15VpowersupplyofthePWMsignalgeneration.Itcanbeclearlynoticedthatthe powersupplyofthePWMisdamagedandhastobereplaced.ThedamagedPWM powersupplyisthendesolderedandthenitshouldbereplacedwithanewpower supply.ThiswouldhopefullymaketheDSKworkproperly. Forthesecondcase,letustakeanexampleofoverwritingtheDSPdefaultvariablesandclearingeverythingfromthememory,whichmightresultinthedamageto themainchipintheDSK.Thesymptomstothisproblemarethatyoumaynotbe abletoreceivecorrectwaveformsfromADCandPWM.Thisproblemcanonlybe eliminatedbyreplacingthechipontheDSKwithanewoneandthatshouldwork properly. 56

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5.TestingandEvaluation Inthischapter,thetestingresultsareshown.Asmentionedbefore,thecontrol systemisprogrammedinthreelevels,namelytheopenloopsystem,systemwithcurrentregulatorandthesystemwithspeedregulator,anditsperformanceisevaluated forallthreelevelsaswell. 5.1OpenlooptestwithV/Fcontrol TheopenlooptestiscarriedoutbysettingdierentfrequencytotheV/Fcontrollerandobservingthecorrespondingmotorspeed.Thetestingdataarelistedin Table5.1andcomparedwiththeactualmotorspeed. Table5.1: OpenlooptestwithV/Fcontrol F requencyset(Hz) 10 15 20 25 30 35 40 Sync hronousspeed(rpm) 300 450 600 750 900 1050 1200 Mac hinespeed(rpm) 295 440 586 730 862 1000 1110 Slip 1.67% 2.22% 2.33% 2.67% 4.22% 4.76% 7.5% Itcanbeseenfromthetable5.1that,theinductionmotorrunsslightlyslower thanthesynchronousspeed.Withincreaseinthefrequency,theslipisalsoincreasing. Thismightbeduetothereasonthatthefrictiontorquebecomeslargerwithincreasing motorspeed.Thereforelargerslipisneededtogenerateenoughtorque. 5.2ClosedlooptestwithCurrentRegulator Oneoftheadvantageofthesetupweuseinthisprojectisthattheuserisableto accesstheDACmemory,whiletheprocessorisstillrunning.Inordertocapturethe dynamicresponseof d and q currents,twomemorylocationsareallocatedandcanbe directlyaccessesusingtheoscilloscope.Oncethestepchangeincurrentreferenceis applied,ineachcontrolloop,thevalueof d and q currentisstoredinthememoryuntil thememoryiffull.Inthecode,ifthesevariablesareconverteddirectlytointeger,the 57

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resolutionwillbegreatlyreduced.Toguaranteeenoughresolution,beforeconverting avariable,thevariableismultipliedby4095or2047,dependingonhowlargeits maximumvalueis. (a) (b) Figure5.1:Stepresponseofthedandqcurrents.Fig(a)isthestepresponseofthe dcurrentwithareferenceof80mA,andfg(b)isthestepresponseoftheqcurrent withareferenceof80mA. (a) (b) Figure5.2:Responseinqcurrentduetoastepinicurrent.Fig.(a)showsq currentwithrespecttostepindcurrentandFig.(b)showsqcurrentwithrespect toquadraturereferencei.e.zero Thisanalysispartisdoneinthissection. 58

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5.2.1AnalysisonResults FromFig.5.1(a)andFig.5.1(b),itcanbeseenthattherisetimeofboth i d and i q aresameandmatchesthedesignspecifcations.Thoughthereisnoiseon boththecurves,itcanbenoticedthatthecurrentsarriveattheirreferencevalues withoutsteady-stateerror.Theonlyproblemisthatwehaveaovershootinthe i q waveform.Sincethedesiredclosed-loopsystemisafrst-ordersystemandantiwinduphasbeenadded,thereshouldnotbeanylargeovershoot.Butotherthan that,allotherparametershaveasatisfyingresult. 5.3ClosedLooptestwithSpeedRegulator Asthespeedloophasmuchslowerresponsethanthecurrentloop,moredata needstobestoredtostudythestepresponseofthespeedloop. 5.3.1ExperimentalResults Inthefrstdesignplan,thebandwidthforthespeedcontrolloop ischosenas 20rad/sec.Inordertoeliminatethenon-linearityandtwomuchructuation,amuch smallerbandwidth forthespeedcontrolloopandasmallerreferencespeedare appliedintheexperimenttoavoidqcurrenthittingitslimit. Figure5.3:Speedstepresponseat300rpmandverysmallbandwidth 59

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5.3.2AnalysisonResults Giventhespeedcontrolloopbandwidth ,therisetimeofthespeedresponse isnoticedtobesatisfactory.Also,itisapproachingsteadystateasitgetsalarger accelerationwhichcausesanunnoticeableovershoot.Butthedierencebetweenthe simulationresultsandtheexperimentalresultsmightbeduetoinaccuratespeed sensing,incorrectmotorparameterslike B and J ,themotorcoecients.Theother factormightbeduetoinaccurateruxestimation.Thevariationinthemachine parameterswillgreatlyaecttheruxestimation.Theerrorbetweentheestimated andtheactualruxwillleadtoawrongcalculationofthe q currentreference,which willcauseaseriesofreactionsandunexpectedresults. 60

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6.SimulinkorC:Acomparitivestudy Thischapterdiscussesthemainresearchcontributiontothisproject.Inthepast fewyears,Clanguagehasbeenaprimarylanguagefortheinterfacebetweenthereal timemodels.But,inthisproject,unlikevariousotherprojectswhichusesCastheir interfacinglanguage,theconventionalClanguagehasbeenreplacedbySimulink, anenvironmentforsimulationandmodel-baseddesignfordynamicandembedded systems. 6.1IntroductiontoC EmbeddedProcessorscanbeprogrammedusingvariouslanguages.However,the mostcommonlanguageusedtoprogramembeddedprocessorsisClanguage.The followingfgureFig.6.1showsthatCisusedbymorethanafour-to-onemarginover itsnearestcompetitor,Assemblylanguage. Figure6.1:ProgrammingLanguagesusedinEmbeddedDesigns[5] ThereasonthatClanguageisusedwidelyinprogrammingembeddedmachines isthatitisamediumlevellanguage,incontrasttootherhighlanguageslikeJAVAor lowlanguageslikeAssembly.C,withitsmediumlevelofcomplexityisunderstandable 61

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tohumans,executesatareasonablyfastspeed,andusuallyallowsprogrammersto exerciseenoughcontrolovertheinnerworkingoftheembeddedprocessor.This balancebetweenintelligibilityandfundamentalcontrolmakeClanguagetheprime choiceforembeddedprocessorprogramming.Sometimes,whenadditionalcontrolor anextremelyfastexecutionspeedisneededforaspecifcinstruction,afewlinesof AssemblylanguagemaybecombinedwiththemainCprogram. 6.1.1HowdoesCwork? WhenaprogramiswritteninanylanguagemorecomplexthanAssembly(which canbeimmediatelyprocessedbyacomputer),severalstepsarerequiredtoconvert thatprogramintoanexecutablefle.Cintheformthataprogrammerwritesiscalled sourcecode,andmustgothroughthebuildprocesstogeneratefunctionalcode.This sourcecodemustfrstbecompiled,oncecompiledtheresultingobjectcodeislinked usingalinkerprogram.Alinkerattemptstofndanylibrariesofcodethattheobject mightneedtoperformitsfunction(e.g.otherobjectcodecompiledfromothersource code);linksthesebitsofcodetogether;andcreatesan.exeexecutableflethatcan berun. 6.1.2DrawbacksofC Asdiscussedabove,itisunderstoodthattheClanguageisthewidelyused programminglanguagegloballybecauseofitsexecutingspeedandeciency.Incontrasttotheadvantagesproducedbytheoldstandbycomputinglanguagethatmany wouldcallobsolete:ANSIC,therearesomedrawbacksthatcouldbeencounteredin developingamodelforaparticulardesign.CandotherhigherlanguageshavebecomepopularformodellingDSPalgorithmsbecauseofthemoreconciseexpressionof behavior.However,theselanguageslackaneectiveautomatedpathtoimplementation.Tobecomeimplementable,thetradeofordescriptionlanguageslikeCshould becomelessconcise.SometimestheCbecomessocomplicatedatinstanceslikeaugmentingCwithfxed-pointquantizationcapabilitiesandloopparallelization.Also, 62

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Clanguageisconsideredasdiculttolearninveryshortperiodoftime.Sometimes, becauseoftheconcisenessinC,thecodecanbediculttofollow.Idoesnotsuiteto applicationswhichrequireformattinganddataflemanipulation.Forlearninghow towriteprogramsinC,wemustfrstknowwhatalphabets,numbersandsymbolsare used,thenhowconstants,variablesandkeywordsareformed,andfnallyhowthese arecombinedtoformaninstruction. 6.1.3ReplacementforC Havingmentionedallthedrawbacksthatwillbeencounteredwhendevelopinga projectusingCasthemainlanguage,thissectionwillexplainthealternativelanguage thatshouldbereplacedinplaceoftraditionallanguageC.Themainreasonthata dierentapproachisusedinthisprojectistoreducetheoveralltimethattakesforthe entirevectorcontrolalgorithmtobeimplementedanddeployedontargethardware eciently. 6.2IntroductiontoSimulink AftermanydiscussionsanddebatesonusingClanguageindesigningvector control,inthisproject,anewapproachofusingSimulinkastheinterfacebetween thesoftwareandthehardware.Also,thisapproachenabledustocreateacompletely newtechnologyofusingSimulinktoexecutea makefile torunthehardware,aswell astogenerateoptimizedCcodeautomatically,usingSimulinksextensiontoolcalled embeddedcoder .Thisapproachprovedbenefcialforthisprojectasyoucangenerate boththeSimulinkandCcodeatthesametimeandinareducedamountoftime. 6.2.1FlexibilitywithSimulink Inordertocompletethisprojectsuccessfully,wehavetakentwoapproaches intoconsideration,thatcanimplementedsimilarlyonthetargethardwareandthen, boththeapproachesarecomparedforthetimelengthoftheproject.TheFig.6.2 showstherowchartdiagramrepresentingthevariousstepsinvolvedinboththe approaches.Asseenfromthefgure,boththeapproachesproducethesameresult. 63

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However,approach1doesnotoerrexibilityintransitingtoadierentapproach, whichinourcaseisappraoch2.But,appraoch2oersamuchrexibilityindoingthe samething. Figure6.2:Illustrationoftwodierentapproachesthatcanbeusedintheproject ThissectioncoverstheadvantagesofsimulinkoverC 6.3AdvantagesofSimulinkoverC Simulinkprovidesaninteractivegraphicalenvironmentandacustomizableset ofblocklibrariesthatletyoudesign,simulate,implement,andtestavarietyof 64

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time-varyingsystems,includingcommunications,controls,signalprocessing,video processingandimageprocessing.Simulinkoersthequickestwayofdevelopingyour modelincontrasttotext-basedprogramminglanguagelikeC.Also,Simulinkhas integratedsolvers.But,forC,youhavewritetowritethecodetocreateasolver. Simulinkprovidesanecientdesignandsimulationframeworkforcreatinghigh-level algorithmmodelsandlimitedcapabilitiesthatdirectlyassistinimplementation.More specifcally,itallowsfordefningsampleratesandfxed-pointdatatypes,adiscretetimemodellingengine,andarichsetofmathematicaloperationsandanalysistools. Furthermore,itincludesmethodsforautomaticallypropagatingthefxed-pointtypes andsampleratesthroughthealgorithmdatapath.Thisprocesssavessignifcant timeincapturingalgorithmbehavior. 65

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7.Conclusions 7.1ResultsfromPresentwork Themainpurposeandobjectiveofthisprojectaregenerallyachieved.The evaluationboardseemstobeworkingwellforthisproject.Consideringtheinterface boardpart,thedigitalsignalinterfaces,suchasPWMandincrementalencoder,work satisfactorily.But,ifyouobservethecurrentsignalsfromADC,thereissomenoise addedtothemeasuredsignals.Forthevectorcontroldesign,thecontrolsystem ontheDSPmanagestocontrolthe d,q currentsandspeedaccurately.Oneofthe problemsthatcanbeobservedfromtheexperimentalresultsistheovershootin q currentduringthecurrentcontrollooptest.Itwasassumedthattheproblemmight beduetoincorrectnessintheparameters. Inthefnalsectionofthisproject,acomparisonisdonebetweentheoldconventionalapproachandnewapproachusedinthisprojectindesigningthevector controlalgorithm.Itcanbeconcludedthat,theapproachwhichusesSimulinkasthe interfacinglanguageseemstohavehighereciencyandrexibilityintermsoftime whencomparedtotheapproachwhichusesCastheinterfacinglanguageforthose whoareinexperiencedinbothapproaches. 7.2Futurework Thereisaroomtoimprovetheperformanceofthepresentsystem.Considering ADCnoise,theADCconditioningcircuitneedstobeimproved.Newcontrolstrategiescouldalsobeconsideredforcontroldesigninordertomakesystemlesssensitive toparametervariationandreduceharmonicdistortion.Finally,frommanyresearch papers,itisunderstoodthatthereisapossibilityofcontrollingseveralmotorssimultaneouslytomakefulluseofF28335DSP'scapacity. 66

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REFERENCES [1]TexasInstuments.http://www.ti.com/lit/ug/spru812a/spru812a.pages9{13. [2]TexasInstuments.http://www.ti.com/lit/ds/symlink/tms320f28335.pages31{ 35. [3]TexasInstuments.www.ti.com/lit/pdf/sprufz6.pages14{18. [4]TexasInstuments.http://www.ti.com/lit/ug/sprug05a/sprug05a.pages9{15. [5]D.Lewis.Fundamentalsofembeddedsoftwaredesign. PrenticeHall,2002. [6]DCorACdrives?Aguideforusersofvariable-speeddrives(VSDs). ABB,Tech. Rep. [7]K.AissaandK.D.Eddine.Vectorcontrolusingseriesironlossmodelofinduction,motorsandpowerlossminimization. WorldAcademyofScience,EngineeringandTechnology,2009. [8]An887acinductionmotorfundamentals. Microchip,Tech.Rep. ,2003. [9]M.DeickeandRikW.DeDonckerS.Muller.Adjustablespeedgenerators forwindturbinesbasedondoubly-fedinductionmachinesand4-quadrantigbt converterslinkedtotherotor. IEEE,2000. [10]Seung-KiSul.ControlofElectricMachineDriveSystems. Wiley-IEEEPress, 2011. [11]L.Harnefors.ControlofVariable-SpeedDrives. Departmentofelectronics, MalardalenUniversity,Sweden ,AppliedSignalProcessingandcontrol,2002. [12]FredeBlaabjergandIonBoldeaIoanSerban,DorinIles-Klumpner.Sensorless ControlofWoundRotorInductionGeneratorforwindpowerapplications:the experimentaltestplatform. IEEE. [13]B.W.KarlJ.Astrom.Computer-ControlledSystems,theoryanddesign. PrenticeHall,1997. [14]K.E.Arzen.Real-TimeControlSystem. LundInstituteofTechnology,2008. [15]R.KrishnanandA.S.Bharadwaj.AReviewofParameterSensitivityand AdaptationinIndirectVectorControlledInductionMotorDriveSystems. IEEE explore,1990. 67

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[16]TexasInstruments.CodeComposerStudioIntegratedDevelopmentEnvironment. www.ti.com/tool/ccstudio. [17]TexasInstruments.controlSUITESoftwareSuite. www.ti.com/tool/controlsuite. [18]BalancedThree-PhaseCircuits. http://my.ece.msstate.edu/faculty/donohoe/ece3614threephase-power.pdf. [19]MathWorks.MatlabandSimulinkEmbeddedCoder.R2014b. [20]TexasInstruments.TMS320x2833xanalog-to-digitalconverter(adc)modulereferenceguide. TexasInstruments,Tech.Rep. ,October2007. [21]TexasInstruments.F2833xanaloguedigitalconverter. TexasInstruments,Tech. Rep. [22]TexasInstruments.TMS320x280x,2801x,2804xenhancedpulsewidthmodulator(epwm)module. TexasInstruments,Tech.Rep. ,July2009. [23]TexasInstruments.TMS320x280x,2801x,2804xenhancedquadratureencoder pulse(eqep)module. TexasInstruments,Tech.Rep. ,December2008. 68

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AppendixA.SimulationsandWaveforms A.1Simulations FigureA.1:SimulinkmodelforV/F FigureA.2:SimulinkmodelforV/Fsubsystem 69

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FigureA.3:SimulinkmodelforCurrentcontrol 70

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FigureA.4:SimulinkmodelforSpeedcontrol 71

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A.2Waveforms (a) (b) FigureA.5:(a)showsStatorvoltagesin abc referenceframeand(b)showsStator voltagesin stationary referenceframe FigureA.6:Statorvoltagesinrotatingreferenceframe 72

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(a) (b) FigureA.7:(a)showsStatorcurrentsin abc referenceframeand(b)showsStator currentsin stationary referenceframe FigureA.8:Statorcurrentsinrotatingreferenceframe 73

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FigureA.9:Thetavaryingfrom )Tj /T1_0 11.955 Tf [(to+ FigureA.10:Osetincurrent 74