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Open circuit fault detection and localization through state observer in modular multilevel inverter

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Open circuit fault detection and localization through state observer in modular multilevel inverter
Creator:
Sen, Mustafa ( author )
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English
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1 electronic file (64 pages). : ;

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theses ( marcgt )
non-fiction ( marcgt )

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Abstract:
Modular multilevel converters (MMC) have become attractive since being pro- posed by Marquardt in 2001 [1] by means of being available for medium and high voltage/power applications in the way of such properties as modularity, eciency, high output voltage and power quality apart from being alternative approach for conventional power converters. According to proposed multilevel converter topologies, MMCs are comprised of many submodules (SMs) which are made of semiconductors such as isolated gate bipolar transistors (IGBTs) and diodes. However, because of its design reliability is still problem to be handled. One of the biggest problems that threatens sustainability of MMC system operation is open circuit faults in IGBTs in SMs. In this thesis state observer which is used in small scale "5 level" MMC inverter system to observe, detect and locate the fault related with SM capacitor voltages. Phase shifted pulse width modulation (PS{PWM), voltage balancing (sorting) algorithm which is similar with reduced switching frequency (RSF) method and circulating current suppression controller (CCSC) [2] are applied to get result in open loop condition. The method is implemented via detailed Matlab/Simulink computer simulations.
Thesis:
Thesis (M.S.)--University of Colorado Denver.
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Includes bibliographic references
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Department of Electrical Engineering
Statement of Responsibility:
by Mustafa Sen.

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University of Colorado Denver
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952058749 ( OCLC )
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Full Text
OPEN CIRCUIT FAULT DETECTION AND LOCALIZATION THROUGH
STATE OBSERVER IN MODULAR MULTILEVEL INVERTER
by
MUSTAFA SEN
Bachelor of Science, Yildiz Technical University, 2011
A thesis submitted to the
Faculty of the Graduate School of the
University of Colorado in partial fulfillment
of the requirements for the degree of
Master of Science
Electrical Engineering
2016


2016
MUSTAFA SEN
ALL RIGHTS RESERVED


This thesis for the Master of Science degree by
Mustafa Sen
has been approved for the
Department of Electrical Engineering
by
Jaedo Park, Chair
Jan Bialasiewicz
Dan Connors
March 11, 2016
iii


Sen, Mustafa (M.S., Electrical Engineering)
Open Circuit Fault Detection and Localization Through State Observer In Modular
Multilevel Inverter
Thesis directed by Assistant Professor Jaedo Park
ABSTRACT
Modular multilevel converters (MMC) have become attractive since being pro-
posed by Marquardt in 2001 [1] by means of being available for medium and high
voltage/power applications in the way of such properties as modularity, efficiency,
high output voltage and power quality apart from being alternative approach for con-
ventional power converters. According to proposed multilevel converter topologies,
MMCs are comprised of many submodules (SMs) which are made of semiconductors
such as isolated gate bipolar transistors (IGBTs) and diodes. However, because of
its design reliability is still problem to be handled. One of the biggest problems that
threatens sustainability of MMC system operation is open circuit faults in IGBTs
in SMs. In this thesis state observer which is used in small scale 5 level MMC
inverter system to observe, detect and locate the fault related with SM capacitor
voltages. Phase shifted pulse width modulation (PS-PWM), voltage balancing (sort-
ing) algorithm which is similar with reduced switching frequency (RSF) method and
circulating current suppression controller (CCSC) [2] are applied to get result in open
loop condition. The method is implemented via detailed Matlab/Simulink computer
simulations.
The form and content of this abstract are approved. I recommend its publication.
Approved: Jaedo Park
IV


ACKNOWLEDGEMENT
At first, I would like to thank to my advisor, Dr. Jaedo Park, for his guidance,
valuable advice and support during the whole period of the study.
Also, I greatly thank and acknowledge the invaluable supports and guidance of
Turkish Petroleum Corporation.
I express my gratitude to my friends Muhannad Alaraj and Ersin Canak their
advice and help on my research.
I greatly appreciate Dr. Jan Bialasiewicz and Dr. Dan Connors for forming my
dissertation defense committee, their valuable discussions.
Finally, and most importantly, I would like to thank my family; they were always
there cheering me up and stood by me through the good and bad times.
v


DEDICATION
The thesis is dedicated to my family and entourage who have encouraged me to go
further during my life.
vi


TABLE OF CONTENTS
Chapter
1. Introduction................................................................ 1
2. System Modeling and Principles of Operation ............................... 10
2.1 Structure of MMC.................................................... 10
2.2 Operation Principles................................................ 12
3. MMC Control............................................................. 19
3.1 Modulation Methods ................................................. 19
3.1.1 Phase Shifted PWM (PS-PWM) ................................... 20
3.1.2 Phase Disposition PWM (PD-PWM)........................ 22
3.2 Voltage Balancing Algorithm......................................... 27
3.3 Circulating Current Suppression Controller (CCSC)................... 29
4. Fault Detection and Localization .................................... 33
4.1 Fault Types and Characteristics..................................... 33
4.2 Proposed Fault Detection Method..................................... 35
4.3 Proposed Fault Localization Method.................................. 35
4.3.1 Design of State Observer...................................... 36
5. Design Guideline and Simulation .................................... 39
5.1 Circuit Parameters ................................................. 39
5.2 Circulating Current PI Controller Gain Selection.................... 39
5.3 Simulation Results.................................................. 39
5.3.1 Ke=50......................................................... 40
5.3.2 Ke=0.1........................................................ 43
5.4 Discussion.......................................................... 45
6. Conclusion................................................................. 46
7. Future Work................................................................ 47
References................................................................. 48
vii


Appendix
A. Park Transformation.................................................. 52
viii


LIST OF TABLES
Table
1.1 Fault Types................................................................. 7
2.1 Operation of SM............................................................ 15
4.1 Failure Characteristics of Type 1......................................... 34
4.2 Failure Characteristics of Type 2......................................... 34
4.3 Failure Characteristics of Type 3......................................... 34
5.1 Simulation Parameters...................................................... 39
IX


LIST OF FIGURES
Figure
1.1 Two Level Three Phase VSC Topology............................................. 2
1.2 Three Level NPC Converter...................................................... 4
1.3 Flying Capacitor Multilevel Converter.......................................... 5
1.4 Cascaded Half-Bridge Multilevel Converter...................................... 6
1.5 MMC Inverter Topology.......................................................... 7
2.1 Voltage Waveform of 2 Level Converter......................................... 10
2.2 Single Module of MMC ......................................................... 12
2.3 MMC Output Voltage Synthesis.................................................. 13
2.4 Overall System Structure ..................................................... 14
2.5 Switching States of SM ....................................................... 15
3.1 Sinusoidal PWM and Output Waveforms For 2 Level VSC...................... 19
3.2 PS-PWM Reference vs Carriers.................................................. 21
3.3 Activated Number of SMs....................................................... 21
3.4 PD-PWM Reference vs Carriers.................................................. 22
3.5 Reference for Number of ON State SMs.......................................... 23
3.6 POD-PWM Reference vs Carriers................................................. 23
3.7 Reference for Number of ON State SMs.......................................... 24
3.8 APOD-PWM Reference vs Carriers................................................ 24
3.9 Reference for Number of ON State SMs.......................................... 25
3.10 Phase C Arm and Inner Difference Currents for PS-PWM.......................... 26
3.11 3 Phase Circulating Currents for PS-PWM....................................... 26
3.12 Phase C Arm and Inner Difference Currents for PD-PWM.......................... 27
3.13 3 Phase Circulating Currents for PD-PWM....................................... 27
3.14 Reduced Switching Frequency Voltage Balancing Algorithm............... 28
3.15 Transfer Function of the Circulating Currents in dq Reference Frame........... 30
x


3.16 Closed Loop d-q Axis Circulating Current Controllers............................... 31
3.17 Overall Circulating Current Suppression Controller................................. 32
4.1 Fault Types....................................................................... 33
4.2 Fault Detection Flowchart......................................................... 36
4.3 Fault Localization Flowchart...................................................... 37
5.1 Phase C Upper-Lower Arm Capacitor Voltages......................................... 40
5.2 3 Phase Circulating Currents ...................................................... 41
5.3 Phase C Vuci and Vuciest.............................................. 41
5.4 Phase C Vuc2 and Vuc2est.............................................. 42
5.5 Phase C Vuc3 and Vuc3est.............................................. 42
5.6 Phase C VUC4 and VUC4est.............................................. 43
5.7 Fault Status of SMs............................................................... 43
5.8 Phase C VMCi and Vuciest for Ke=0.1.............................................. 44
5.9 Fault Status of SMs for Ke=0.1..................................................... 44
A.l The stationary abc reference frame and the rotating dq reference frame ... 52
xi


1. Introduction
Developments for the new technologies in the last century increased the atten-
tion in electric power systems. Studies on electric power generation, conversion and
transmission devices have become more and more important day by day. Also, to
protect and preserve the environment from the pollution which is caused by nuclear
and fossil energy sources like oil, coal and natural gas the interest in electrical power
generation from green energy (renewable) sources such as wind power and solar sys-
tems has been enhanced and they are supposed to play important role in world-wide
energy production in the following years. Not only industrial applications even the
electrical network requirements display the importance of energy supply and control
in the recent researches. As a consequence, power conversion and control in power
transmission process has to be reliable, safe and available in order to accomplish all
the requirements.
In [3] it is stated that in a power transmission system the most important process
is to control active and reactive power flow to keep the system voltage stable. This
goal can be accomplished by use of power converters through its ability to convert
energy from DC to AC or vice versa. So far there has been two types of configurations
as regards three phase power converters which high voltage direct current (HVDC)
transmission system can utilize. These are conventional voltage source converters
(VSCs) which is commonly used in the area and shown in Figure 1.1 and current
source converters (CSCs). Main characteristic of VSCs is that as it is shown in Figure
1.1 it is a composition of three identical half-bridge converters and it operates with
specified vector control strategy which can perform active and reactive power control
separately [4], This makes it convenient for connection to weak AC networks without
local voltage sources. Also, during the power reversal the DC voltage polarity remains
the same for VSCs based transmission system and the power transfer depends on only
the direction of the DC current.On the other hand, in a Current Source Converter the
1


DC current is fixed with a small ripple using a large inductor, thus forming a current
source on the DC side. The direction of power flow through a CSCs is determined by
the polarity of the DC voltage while the direction of current flow remains the same.
Figure 1.1: Two Level Three Phase VSC Topology
Although these power converters have lately been used in high voltage direct
current (HVDC) power transmission applications, However, according to [5] there
are some drawbacks for both. CSCs require large reactive power quantities during
the process and it is inconvenient to control active and reactive power independently.
Also, because of generating low frequency harmonics it causes losses and expensive
Liters needed. Additionally, conventional 2 level VSCs produce large high frequency
harmonics which result in bigger losses to compare with CSCs due to higher switching
frequencies. Moreover, its design need a large number of switches that are connected
in series.Thus, this situation may cause multiple failure points.
To overcome these problems several different multilevel topologies have been pro-
posed and the main reason for the interest on multilevel converters instead conven-
2


tional two-level converters lies in the improved quality of their output waveform,
possibility to achieve higher power levels and higher efficiency [6]. Some of the most
common multilevel topologies are:
* Neutral-Point Clamped (NPC)
* Flying Capacitor (FC)
* Cascaded H-Bridge (CHB)
* Modular Multilevel Converters (MMC)
The NPC multilevel converter was initially proposed as a three-level inverter as
shown in Figure 1.2. The midpoint of the switches is connected to the neutral point
of the converter over the clamping diodes, so it enables zero voltage level generation.
Thanks to this, for the same DC-link voltage, the voltage which the devices in the
converter have to tolerate is reduced to half in comparison with the two-level topol-
ogy. On the contrary, this topology has several disadvantages such as under certain
operating conditions the NPC converter may experience unbalanced capacitor volt-
ages, creating a potential between the neutral point and ground and causing distorted
output waveforms.
In FC converter topology which is shown in Figure 1.3, each capacitor in the
phase is charged to a different voltage level, therefore by changing the states of the
switches, various output voltage levels can be obtained [7]. This topology can have
phase redundant switching states that can be used for capacitor voltage regulation
and it brings sort of advantage compared to the NPC converter topology. In the way
of the energy storage in the capacitors, the converter can ride through short duration
outages. As a disadvantage, before the start-up, capacitors have to be pre-charged
which is known as initialisation as requirement. Also this topology presents unequal
duty distribution between the switches. Even though the FC converter topology can
3


fa fb Vc
Figure 1.2: Three Level NPC Converter
be extended to an arbitrary number of cells, the addition of capacitors leads to an
increase in cost. Thus the number of level is usually limited with four [6,8].
The CHB topology is based on the series connection of single-phase full-bridge
inverter cells with isolated DC supplies. It is demonstrated below in Figure 1.4. The
main advantages of the CHB topology over the NPC and FC ones are its modular
structure and the possibility to have an independent control over the zero-sequence
component in the current. In case of rectifier applications, the need of many isolated
DC sources in series limits the number of cells in the leg, keeping this topology
unfavourable for bidirectional power applications [4,6]. However, a proposal for CHB
approach in HVDC applications using a re-injection circuit can be found in [8].
Since MMCs were proposed to be alternative approach for existing ones, they
have become commercially attractive for medium and high power applications and
brought many advantages over conventional types of converters [9-12],In Figure 1.5
n + 1 level MMC Inverter topology is shown. These benefits are mainly
4


Figure 1.3: Flying Capacitor Multilevel Converter
* modularity and scalability
* lower switching frequency of individual levels, so in comparison with tradi-
tional VSCs obtaining the same waveform properties with lower switching losses
* improved reliability in case some modules have fault as converter can function
* magnitude of harmonics is significantly reduced or possibly eliminated, there-
fore no need for filter banks
* flexible control of the voltage level and simple realization of redundancy if
required
* no requirement for expensive transformers
On the other hand, one of the biggest challenges about MMCs is reliability. MMCs
consist of a large number of power switching devices such as IGBTs in SMs depends
5


n
Figure 1.4: Cascaded Half-Bridge Multilevel Converter
on volume of the application and these switches have to be taken into consideration
as potential failure points. According to table 1.1 which shows SM and converter
level faults respectively and also is given in [13],in SM level, faults which are related
with IGBTs such as open circuit and intermittent gate misfiring faults are shown as
one of the most common fault types which may disrupt the operation of MMC or
even destroy it due to effect on current and voltage in MMC [14], So it is clear that
fault detection and localization in a short time after occurrence are really vital for
sustainability of the MMC operation.
There are several methods that are proposed on open circuit fault detection in
MMC. In [15], Kalman Fitering (iv) is being recommended to detect the fault con-
dition by means of comparison between the measured and estimated inner difference
6


Klc
Figure 1.5: MMC Inverter Topology
Table 1.1: Fault Types
Sub-module level Capacitor Fault in capacitor structure
Diode Open diode faults
Short Circuit Faults
IGBT Open circuit faults
Intermittent eate misfiring; faults
Converter level Capacitor voltage unbalance
Circulating current among three phase unit
Unbalance between upper and lower arm voltage
Control of energy stored in the leg
Single phase to ground fault
Double phase to ground fault
Triple phase to ground fault
current based on specified current difference threshold for some certain period. After
fault is detected, SM capacitor voltages in the concerned phase which is identified as
7


faulty are compared with minimum capacitor voltage value in the same arm for some
threshold period and value to locate faulty SM in the upper\lower arm. Another
proposed method is based on sliding mode observer (SMO) which has been presented
in [16]. In here, voltage and current relationships between the both sides of SMs are
calculated under normal and open circuit fault case in each switch. Through SMO
estimated and actual states are compared if difference between them is more than
threshold value for certain period which is already specified in terms of systems sen-
sitivity, fault is detected in this way. According to [17], it is stated that this SMO
method is accurate, but not fast for MMCs with high number of SMs. In this case, it
may be encountered with additional damages because of instant increase of faulty SM
capacitor voltages. So, it suggests different method which is based on voltage across
inductor and arm current observation in the upper\lower arms in any phase instead
of using observer to make this process faster. Another presented approach relies on
adaptive backstepping observer to take place of sensors and reduce the complexity of
implementation which is given in [18].
Apart from these methods, state observers can be designed to detect and locate
the open circuit faults in SMs by reducing number of measurement sensors in parallel
with total cost by estimating capacitor voltages and output currents [19]. In this thesis
study, design of state observer approach for linear systems is benehtted to estimate
capacitor voltages in SMs locate the faulty module to be alternative for existing
approaches. To obtain proper results in open loop condition PS-PWM technique
and voltage balancing algorithm which is similar with the way expressed in [2] are
employed in 5 Level MMC inverter. In [20], PS-PWM is presented and technical
aspects are discussed.
The thesis is organized in following way; in chapter 2, structure modelling and
operational principles of MMC are explained. Afterwards, chapter 3 is about control
approach related with the preferred PWM technique, the capacitor voltage balancing
8


algorithm and circulating current suppression control (CCSC). In chapter 4, fault
types, characteristics on SMs with proposed fault detection and localization meth-
ods are explained. Chapter 5 is including design guideline and simulation results.
Conclusion is added in chapter 6.
9


2. System Modeling and Principles of Operation
2.1 Structure of MMC
It can be stated that MMCs are sort of VSC and the related principles of operation
for VSCs can be applied to it. Because if only 2 SMs were used in MMC (we could
say that one for positive DC connection and the other one is negative), synthesized
output voltage waveform would be in Figure 2.1 which is like 2 level voltage source
converter. So, operation of this MMC would be equivalent to VSC. Also, It can be
used as rectifier and inverter in back to back HVDC power transmission systems that
Siemens has a plan of putting this converter into practical applications with the trade
name HVDC-plus. The system configuration of the HVDC-plus has a power of 400
MVA, a dc link voltage of 200 kV, and each arm composed of 200 SMs [21].

Fn ___________ _____________________
-tv
2 ---------------------------
Figure 2.1: Voltage Waveform of 2 Level Converter
Additionally, The MMC configuration also offers more advantages over the tra-
ditional VSCs [5]. These are
* Not all the switches in a leg are opened or closed at the same time as they
would in a two-level VSC, but they are operated at different time instants to
follow the sinusoidal reference command more closely, the switching frequency
of each switch can thus be low, while still generating a large apparent switching
frequency.
* The voltage blocking requirements of an individual switch is limited to the
voltage across the modules capacitor.
10


* If enough modules are used, the voltage across each switch can be low enough
not to require series connected switches. In a 2-level VSC, each arm (valve)
must be able to block several hundreds of kVs while open. An IGBT is usually
rated for a few kVs only, so multiple switches must be connected in series
to achieve the desired blocking capabilities. During switching, all these devices
must operate together. If one IGBT operation is delayed, it is exposed to a high
voltage, which could damage it. In the case of the MMC, the high number of
modules, each only blocking the voltage across its internal capacitor eliminates
this drawback and improves the failure rate.
* The modular concept allows operation even if some modules have failed. Failed
modules can simply be bypassed, and kept bypassed until it is possible to replace
them, and operation can continue. The DC bus voltage is then divided among
the remaining N-l modules and normal operation can continue.
* It is possible to design a MMC converter with spare modules which can be
used if one module were to fails. If spare modules are available, they can be
inserted in the arm as needed.
As it can be seen from the Figure 2.4 that demonstrates the overall system, SM
is the basic building cell for MMC. There may be hundreds or thousands of SMs in
MMC in terms of required power level depends on application [22], SMs consist of
two IGBTs (Si,S2), two diodes (Di,D2) which are connected in parallel with them
and a submodule capacitor (C^m). Also these diodes are used due to protection of
IGBT switches. Figure 2.2 shows SM diagram.
In a three-phase MMC system, for each phase there are phase legs which are
composed of upper and lower arms. These arms are formed by series connected n
number of SMs. There is also an inductor in each arm, Larm, in order to smooth
the voltage difference (to reduce circulating currents between phase units) that is
11


[
produced when a SM is connected or disconnected [23].
2.2 Operation Principles
The general concept of multilevel converter is the synthesis of a sinusoidal voltage
by several levels of voltages. In case of MMC, these voltage levels are obtained from
the capacitor voltages, Vc, of each SM. At any instant, a number of SMs that are
switched on equals n totally which is including upper and lower arm in any phase,
so that the voltage at the converter terminals equals the instantaneous value of the
voltage to be synthesized [24] as it is shown in in Figure 2.3 which are output voltages
of 3, 5 and 9 level MMCs varies between Vdc/2 respectively. As it is seen if number
of voltage level is increased, resolution of sinusoidal waveform for the output voltage
gets better. Besides, average Vc is denoted as
Vc = (2.1)
n
As regards gate signal of related IGBT switch SM has two states in normal
operation. These are ON and OFF states. Figure 2.5 indicates the concerned
states respectively.
*ON State Si is switched on, S2 is switched off
As upper IGBT is in the conducting mode in any SM in any phase, Vc equals to
12


i
Vd£
\ 1 1 1
t

Vdc
2 '
Vd£
2
t
Figure 2.3: MMC Output Voltage Synthesis
the SM output voltage (Vc = Tdm) regardless of current direction. If the current
is positive it freewheels through anti-parallel diode D1 and Vc increases or when
current polarity is negative it flows through the Si and discharges the C^m.
*Off State Si is switched off, S2 is switched on
In here, the Td,m doesnt change. Because related SM is bypassed. Arm current
either flows through the S2 or the D2 depending on its direction. Thereby, Td,m
is zero.
Table 2.1 shows the operational status of the SM in terms of complementary
switching states of IGBTs. Also, the relation between V^m and Vc can be formulated
in the following way:
13


MMC VSI
Figure 2.4: Overall System Structure


SM SWITCHED ON
SM SWITCHED OFF
Figure 2.5: Switching States of SM
bsm,i.jk SijkVc,ijk
(2/2)
Table 2.1: Operation of SM
SM State S Si s2 ^sm Arm Current n wsm vc
ON 1 ON OFF uc Positive Charge Increased
Negative Discharge Decreased
OFF 0 OFF ON 0 Positive Bypass Unchanged
Negative
The arm voltage can be computed considering the status of the SMs switches,
Syk, as follows [25]:
Vn =
k= 1
SVjkl/o)ijk
(2.3)
15


where i = u,£ represents the upper and lower arm, respectively; j = a,b,c is the
phase; and k = 1,2,..., n denotes the SM. The arm currents can be determined as
luj = + Idiffj (2-4)
hi = -y- + biff, (2.5)
According to [26] Idiffj has two components. These are one third of dc source
current (/<&/3) and the other part is circulating current (ICirc,j) So the previous
equation can be written in the following way.
4uj = + -^ + 4circj, (2.6)
Aj = + icircj (2.7)
where IcirCj is the circulating current for phase j, and /CirCa + /CirCb + /CirCc = 0. These
circulating currents have no effect on the ac side or dc side voltages. It can be proved
based on arm current equations as it is demonstrated below [5]. On the other hand,
they have significant impact on SMs capacitor voltages and the rating values of the
MMC components [25].
So Lima becomes
IQ, I dc r
' g ~T~ -^circ,a
g \ -^circja
Iua I
la.
lie j Ala Ila
3~ + ua 2
Adc
'~3~
Alia, + Ii
la
(2,8)
(2,9)
Icirc,b and ICirc,c can also be defined as in the following.
16


Iarct=-If+1^^- (2.10)
(2.11)
By summing all three circulating currents it is obtained that
Icirc,a I Icirc,b I Icirc,c
IirrM I hzrrj
Idc Va ~L I (.a,
~3~ + 2
Vc Vb "h lib
~3~ + 2
Vc Vc "h I(,c
~3~ + 2
Idc
Vc
0
Via + Vib + Vic + Va + lib + Vc
Vdc "h Vdc
(2.12)
Simultaneously, correlation between ac side and dc side voltages of the MMC is ex-
tracted through Kirchoffs Voltage and Current Laws (KYL-KCL).
Vic
2
Vdc
V
vdiffj
Ki + L iIai
Vj + La
dt
dlf.\
V -RarmVij I Vj
^ + Raimiij Vj
d
dt
Kj + Vj+ harm (+ ~7rl + -Rarm(Vj + Vj)
dt dt
1 dlj
^(Vj Kj harm Varm/j)
d/ciiflf;
+ i?arm/diffj
dt 1
i(W Kj vy
(2.13)
where V^ represents inner voltage difference between phase units in MMC and i?arm
is the equivalent resistance of the SMs in an arm. It is related to number of the SMs
in an arm via the resistance of one of SMs IGBT switch, Rsm,
17


-Rarm = nRsm. (2.14)
Equivalent converter arm capacitance (C^m) when n modules are inserted in the
related converter arm equals to the total capacitance of the n series connected sub-
module capacitors as it is shown in equation 2.15.
n
v~/arm
Csm/^
(2.15)
18


3. MMC Control
3.1 Modulation Methods
If two level VSC which is in the form of half bridge circuit as it is shown in Figure
1.1 is considered, conventional pulse width modulation which is using one modulating
signal and one carrier waveforms to generate gate signals for complimentary IGBT
switches in the same phase [4]. Figure 3.1 pictures an example for sinusoidal pulse
width modulation and the result. As it is seen from the Figure 3.1 modulating signal
is compared with triangular carrier wave signal. As a result of it, in case modulating
signal is higher than carrier, this means upper IGBT in VSC is on, otherwise if it is
lower than carrier, lower one is on. This PWM method is repeated with proper phase
shifts in terms of other phases when 3 phase two level VSC is used.
For modular multilevel converters, there are several of these half-bridge circuits
(SMs) that all of them has to be individually controlled. The solution for this is to
use multi-carrier PWM methods which means that one carrier waveform for each SM
in MMC.
Time (sec)
-0 5 -------1------------1----------i-----------I---------1----------
0.3 0 0 3 05 0.37 0.375 0.38 0.38 5 0.39
Time (sec)
Figure 3.1: Sinusoidal PWM and Output Waveforms For 2 Level VSC
In [10] and [27] details about multilevel converter PWM methods are given. There
are two specified methods in terms of MMC multi-carrier modulation techniques.
These are phase-shifted and phase disposition PWM methods. For both methods
19


there is one carrier waveform for each SM in the upper\lower arm of the MMC
phase leg. In both methods, multiple carrier waveforms for number of SMs in the
related arm are compared with single arm voltage reference signal (modulating) and
this comparison dictates how many submodules need to be switched on or bypassed.
Apart from these methods there are other multilevel modulation techniques such as
Nearest Level Modulation (NLM) and Space Vector Modulation (SVM). However,
these methods have some drawbacks [28]. For instance, NLM technique is suitable
with the converters which have large number of SMs due to small voltage steps. This
means if it is used with small scale MMC which means low number of switchings
this may cause larger voltage fluctuation in the capacitor voltages and SVM brings
implementation complexity.
3.1.1 Phase Shifted PWM (PS-PWM)
Phase-shifted PWM for modular multilevel converters use one carrier for each
submodule in the MMC and these carrier waveforms have the same amplitude and
frequency which are shifted by A0 which depends on number of SMs in the arm. This
angle A6 is calculated using the equation 3.1.
A0
360
(3.1)
n
n indicates number of SMs in an arm. Two key parameters are the amplitude and
frequency modulation index in this method [20]. The equations to calculate these
parameters are shown in equations 3.2 and 3.3. The frequency modulation index
(nrif) relates the frequency of the carrier wave (/c) to the frequency of the reference
sine wave (/r).
m, = £ (3.2)
Jr
The amplitude modulation index is the ratio of the amplitude of the carrier waveform
and reference waveform.
20


(3-3)
Ar
771(1 = X
2
Figure 3.2 shows an example of PSC-PWM with 4 carrier and 1 reference wave-
forms which dictates how many submodules need to be inserted in the arm in order
to achieve the desired voltage level as it is reflected in Figure 3.3. Also there is 27t/4
phase shift between each carrier waveform which satisfies equation 3.1.
.Q 2 I____I________I________I_______I________I_______I________I_______I________I_______I
0.33 0.332 0.334 0.336 0.338 0.34 0.342 0.344 0.346 0.348 0.35
Time (sec)
Figure 3.2: PS-PWM Reference vs Carriers
Figure 3.3: Activated Number of SMs
21


3.1.2 Phase Disposition PWM (PD-PWM)
Phase Disposed PWM is similar to the previously described methods in that again
the number of carrier waveforms is equal to the number of submodules in each arm.
Also the same amplitude. The differences are that there is no phase shift between
the carriers and they are displaced with respect to zero axis. Also amplitude of them
(Ac) depends on the equation shown in equation 3.4
Ac = - (3.4)
n
In [29] it is stated that there are various types of phase disposed PWM techniques
which depend on whether or not the carrier waveforms are 0 degrees out of phase or
180 degrees out of phase. The first is phase-disposition PWM. Figure 3.4 shows an
example of phase-disposition PWM by showing 4 carrier waveforms superimposed
with a single sinusoidal reference waveform. Figure 3.5 shows the reference signal
using PD-PWM.
Here, each carrier waveform has the same frequency and phase but amplitude of
carriers is 0.25 which is calculated by using the equation 3.4.
Time (sec)
Figure 3.4: PD-PWM Reference vs Carriers
22


Figure 3.5: Reference for Number of ON State SMs
The next level-shifted technique discussed is phase opposite disposition PWM
which is identical to phase-disposition PWM except that the lower half carrier wave-
forms are 180 degrees out of phase. Figure 3.6 shows the carrier waveforms for phase
opposite disposition PWM and we can see that the bottom half carrier waveforms are
180 degrees out of phase. Figure 3.7 then shows the resultant waveform.
Time (sec)
Figure 3.6: POD-PWM Reference vs Carriers
23


3.5 -
CZJ
CO
£2
o
0>1
'i
£
0.33 0.332 0.334 0.336 0.338 0.34 0.342 0.344 0.346 0.348 0.35
Time (sec)
Figure 3.7: Reference for Number of ON State SMs
The final level-shifted technique to be investigated is alternating phase opposite
disposition PWM in which every other carrier waveform is phase shifted 180 degrees
out of phase. Figure 3.8 shows the carrier waveforms for APOD-PWM and Figure
3.9 shows the resultant waveform.
Time (sec)
Figure 3.8: APOD-PWM Reference vs Carriers
In this thesis, PS-PWM method is chosen based on the assumptions given in the
[30] which says concisely PS-PWM can automatically suppress low order harmonics
24


3.5 -
CO
Pi 2
O
CL
'i
0.33 0.332 0.334 0.336 0.338 0.34 0.342 0.344 0.346 0.348 0.35
Time (sec)
Figure 3.9: Reference for Number of ON State SMs
for MMCs. Also when the simulation which is used in the theis study is run with
PS-PWM and PD-PWM seperately, Figures 3.10 and 3.11 show that phase C arm
currents, inner difference current which is including circulating current as explained in
chapter 2 have less oscillation in comparison with the Figures 3.12 and 3.13 obtained
by use of PD-PWM method. Also modulating signals (MUjref = VUjref, Mgjref =
Vejref)which means voltage references for the upper and lower arms as input for PWM
block in any phase of MMC is calculated in the following way [31];
VUjref ~ ~^ ^diffJref ~ ^Jre/ (^-b)
= Vdiff,jref + Vjrf,f (3-6)
Vjref represents the desired output phase voltage of MMC [32] and can be expressed
as
V
V
-^(mcos(ut + ref 2
VK = (mcosiujt + tp- y ))
(3.7)
(3.8)
25


(3.9)
V., = ^j-{mcos(ut + ip + y))
m demonstrates amplitude of modulation index which varies between 0 and 1. u
and

reference inner unbalance voltage as explained in chapter 2 and it is obtained from
CCSC block as it is shown in Figure 3.17.
Figure 3.10: Phase C Arm and Inner Difference Currents for PS-PWM
i i i i i i i r 1 lel^l_
-
1 1 1 1 1 1 1 L 1
iiiiii ' icbo|_
-

Time (fee) 03 D3
1 1 1 1 1 1 r~ 1wl-
Figure 3.11: 3 Phase Circulating Currents for PS-PWM
26


150
Figure 3.12: Phase C Arm and Inner Difference Currents for PD-PWM
100
50
0
-1D0
0 0.1 0.2 03 0.4 05 06 07 O.S 03
Tim. (W)
Figure 3.13: 3 Phase Circulating Currents for PD-PWM
3.2 Voltage Balancing Algorithm
Another important concept to be understood for MMC is the balancing of the
capacitor voltages. Importance of the voltage balancing in MMC is about preventing
27


SM capacitor voltage variation and as a result of it phase units have the same voltages.
Otherwise, it causes circulating currents (ICirc,j) that flow through the six arms and
distort the sinusoidal arm current waveforms. Also, because of it the rms value of
the arm currents and the converter losses increase [25]. In MMC, capacitor voltage
of each SM should be monitored and kept equal for stable operation. To achieve it,
proper voltage balancing algorithm needs to be used. In this study, the algorithm
based on the algorithm stated in [2] which is arm specific is used. In Figure 3.14
flowchart of the voltage balancing algorithm is shown.
Switch on AJVon
SMs with the
lowest voltages
among (Non Nonold)
off state SMs
Switch on ANon
SMs with the
highest voltages
among (Non NOIlold)
off state SMs
Switch off ANon
SMs with the
highest voltages
among (Non NOIlold)
on state SMs
Switch off A Aon
SMs with the
lowest voltages
among (Non NOIlold )
on state SMs
Figure 3.14: Reduced Switching Frequency Voltage Balancing Algorithm
According to this approach, number of SMs in the same arm that needs to be
switched on or off signal which is dictated by PWM block, SM capacitor voltage
measurements (Vhqjk) and arm current (ly) directions are used as inputs. If ly is
positive and extra switches (AN > 0) needs to be ON, there is no switching
applied to SMs which are currently inserted. This algorithm sorts V^yk and chooses
SMs with the lowest voltages among the off state ones. If AN < 0 which means some
28


of the SMs which are already in on state need to be bypassed, SMs with the highest
voltages among the on state ones are chosen and switched off. In case of negative arm
current this algorithm works in the reverse way in terms of choosing SMs based on
their voltage measurement. Additionally, by the time AN = 0, so this means recent
status for the SMs is kept. One of the biggest advantageous of this approach is that it
reduces the average device switching frequency and the total MMC switching losses
in comparison with conventional method. So it is called reduced switching frequency
(RSF) voltage balancing algorithm.
3.3 Circulating Current Suppression Controller (CCSC)
In [33] it is stated that circulating currents (ICirc,j) which is caused by voltage un-
balances between the phase units of MMC and contains second harmonic component
distorts not only arm currents, but also increase the ripple on SM capacitor voltages.
It can be eliminated by adding parallel capacitor which is resonant filter between the
midpoints of the uppper and lower arm inductances [34] on each phase or using an
active control over AC voltage reference [35]. In this study CCSC is based on the
approach given in [2,33].
Inner difference current (hiffj) equation which has two parts as mentioned in chapter
2 is defined as
Idiffj g + -^circj (3.10)
and according to [36] Idrc,j are composed of negative sequence component with twice
the fundamental frequency. So 3 phase Idiffj can be rewritten as
Idiffa = "gp + Ic\rc,a.COs{2ut + 9)
Idiffi = 5 /circ,bCOs(2u;f + d 4 ) (3-11)
Idiffc = 5 Icirc,cCOs(2u)t + 9-------)
29


uj is the fundamental frequency and 9 is the initial phase angle. Inner unbalance
(Vdiffj) voltage which is voltage across the arm inductance and arm resistor is shown
in the following
Ihiffj
did iff.
LL
dt
bhrm-hliffj
(3.12)
and if Park transformation which is given in the appendix is applied, dq components
of three phase Vcuffj are obtained as follows
bdiffa
La
La
dl
u,J-circd
1 dt
dl
^-^CirCq
1 dt
-Rarm-^circd 2cc,-t/arm/cirCq
(3.13)
"P Pan11 b in I 2cuZ/arm/ci
arm^circd
Transfer functions of the ICirc,dq is shown in Figure 3.15. Also to design control
loop, two new control inputs (Ud,uq) can be introduced to obtain two decoupled first
order differential equation as it is suggested in [4],
Figure 3.15: Transfer Function of the Circulating Currents in dq Reference Frame
Ud
bdiflfd T 2(jjL arm-^circQ
dl -
T aicircd r> T
, \ -Llarrr\-Lc\r
dt
^arm-^circd
(3.14)
30


Uq Vdiffq 2 OjL arm dc\r
^arm-^circd
L
dl -
Li nir
(3.15)
arm 7,
dt
^arm^circo
Finally, to eliminate ICirc,dq two identical PI controllers with zero reference values for
dq components separately are applied as it is shown in Figure 3.16. Transfer function
of the PI control is
PIcirc,dq(s') KPcirc,dq T
Ki
circ,dq
vdiffdqref equations become
(3.16)
Ki
bdiffd,ref (0 Itirc,di){KP 3 ~) 2aiLarm/c
Vdiffq,ref (0 Icircyq ) (ATp T ) T 2ojLarmICirCd
Ki
s
(3.17)
d-axis closed-loop circulating current control
1
circ,dref
q-axis closed-loop circulating current control
^circ,qref 0
Figure 3.16: Closed Loop d-q Axis Circulating Current Controllers
After obtaining reference values for inner unbalance voltage in dq reference frame,
inverse Park transformation which is given in appendix is applied to have it in three
phase. Eventually, These values are used to attain reference arm voltages as it is
31


shown in equations 3.5 and 3.6. Overall control system to obtain Vdiff,jref is shown
in Figure 3.17.
Figure 3.17: Overall Circulating Current Suppression Controller
32


4. Fault Detection and Localization
There are various types of faults in MMC as it is given in table 1.1. Because
of MMC structure there are many potential failure points based on semiconductor
devices such as IGBT and diodes in SMs as it shown in Figure 2.2 and it is so vital
to detect and locate the fault after the occurrence within a short time in the way of
system reliability [14]. In this study, only IGBT based open circuit fault is considered
among them.
4.1 Fault Types and Characteristics
In SM, IGBTs can have three types of fault, which are called Type 1, 2 and
3 [15]. Type 1 and 2 faults are when S\ and S2 act as open circuit, respectively.
Both switches are open circuit simultaneously in Type 3 fault. Type 1 fault happens
only when concerned arm current is negative (/ < 0) and gate signal of S\ (Sijk)
is 1. Due to the fact that upper switch is open circuit, current is forced to circulate
through complementary switch diode (D2). Thus, SM is bypassed and Vsm becomes
0 instead of Vc. Type 2 occurs when arm current is positive (/ > 0) and gate signal
for S-2 (S^k) is 1. In this case arm current flows through Di and charges Csm. Unlike
the expected Vsm is 0, Vsm equals to Vc. Other situations SM runs normally. What
about Type 3 is it shows both characteristics of type 1 and 2 faults. Fault scenarios
are depicted in Figure 4.1 respectively. In this paper, to illustrate the fault detection
and localization method only single Type 1 fault is considered.
33


Table 4.1: Failure Characteristics of Type 1
Plealthy Operation Type 1 Fault
Iarm Gate signal for S- L Direction of Iarm V.srn Direction of Iarm V.srn
1 D i and Csm Vc D i and Csm Vc
Positive 0 s2 0 S2 0
1 Csm and Si Vc D2 0
Negative 0 d2 0 d2 0
Table 4.2: Failure Characteristics of Type 2
Plealthy Operation Type 2 Fault
Iarm Gate signal for S- l Direction of Iarm V.srn Direction of Iarm V.srn
1 Di and Csm Vc Di and Csm Vc
Positive 0 s2 0 D i and Csm Vc
1 Csm and Si Vc Csm and Si Vc
Negative 0 d2 0 d2 0
Table 4.3: Failure Characteristics of Type 3
Plealthy Operation Type 3 Fault
Iarm Gate signal for S- l Direction of Iarm V.srn Direction of Iarm V.srn
1 Di and Csm Vc Di and Csm Vc
Positive 0 S2 0 Di and Csm Vc
1 Csm and Si Vc d2 0
Negative 0 d2 0 d2 0
From the tables 4.1, 4.2 and 4.3 that show characteristics of SMs in MMC system
it can be deduced that under all types of open circuit fault circumstances faulty SM
capacitor voltages Vsm become higher than the healthy ones.
34


4.2 Proposed Fault Detection Method
As soon as Type 1 fault happens in one of the SMs in any arm of the MMC,
Vdiffj between the healthy phase units and faulty one gets larger. When PWM block
dictates all SMs in the the same arm to be switched on after the fault occurrence
healthy capacitor voltages increase to recover faulty module. In this period, arm
current negative polarity is suppressed because of circulating current boosted by fault
free phase units.
In normal operation each capacitor voltage is
Vc =
n
(4.1)
which is already shown in equation 2.1. Hereby, in case of fault healthy SM capacitor
voltages are expected to increase to reach the voltage which can be shown as follows
Vr
cth r&shold
Vdc
Tl n faulty
(4.2)
To detect the fault in any phase unit of the MMC system this voltage can be used
as threshold (Ithreshold)- If healthy SM Vc reach or exceed this Vthreshoid for a certain
period of time itmin), so that arm can be labeled as faulty and it can be proceeded to
locate the faulty module in the arm. Simultaneously, it can be extracted from here
that if real life applications in which hundreds of SMs are used depends on the volume
of the application are considered, by benehtting equation 4.2 threshold voltage for
fault detection becomes less. This might affect the fault detection period favourably.
Flowchart of the fault detection process is shown in Figure 4.2.
4.3 Proposed Fault Localization Method
To locate the faulty module, state observer to estimate capacitor voltages can be
used in terms of comparison between the direct measurement of it and observation.
SM capacitor voltage equation is defined as
35


Figure 4.2: Fault Detection Flowchart
br ^ b3*1* (4-3)
As it can be seen from the equation 4.3 it is first order differential equation and can
be considered as state equation for the case. V^yk is considered as state and ly is
input. Flowchart of the fault localization is demonstrated in Figure 4.3.
4.3.1 Design of State Observer
The State observers has been commonly used in industries as an effective method
to provide estimation of a real system [37-39]. To build up the observer the first and
most essential rule is checking the observability of system [40]. But in our case this
is not necessary because of having the first order system. If we consider the plant
defined by
x = Ax + Bu
y = Cx
observer state and output equation will be as follows;
(4.4)
36


Figure 4.3: Fault Localization Flowchart
x = Ax + Bu + Ke(y y)
(4.5)
y = Cx
Ke is observer gain which is correction term between system output and estimated
output as it is shown in equation 4.5. It should be chosen properly in terms of
system performance to make estimated state (£) converge to system state variable (x)
regardless of its initial value (£(0)). In [40] it is stated that dynamic behaviour of the
error vector which is obtained by subtracting system and estimated state equations
from each other determined by the eigenvalues of matrice A KeC as it is shown in
equation .
e= (A KeC)e (4.6)
If it is stable matrice error vector will converge to zero for any initial error value
(e(0)). If the system is low order which means system order can be third order at
most, direct substitution method can be applied to find observer gain. To do that,
37


the desired characteristic polynomial which is extracted from equation 4.5 is used and
shown below.
| si A + KeC | (s fj,\) (4.7)
Hi is the desired observer pole location which is within the left half of ju axis in s
domain. If SM capacitor voltage equation (equation 4.3) which is state equation in
here is considered, it is seen that A which is state matrice is 0 and C which is output
matrice is 1. As a result of it from the equation 4.7 it is deduced that Ke > 0 is the
condition for the stability as it is shown below in equation 4.8. What makes difference
in here is different gain values effecting faulty module localization time when open
circuit fault is generated.
s + Ke\ = (s Hi)
(4.8)
38


5. Design Guideline and Simulation
5.1 Circuit Parameters
To run MMC inverter with RL load in open loop condition, circuit parameters
are taken from the [15]. They are shown in table 5.1.
Table 5.1: Simulation Parameters
Vac ^sm n sm Larm Rload Lload fcarrier fload modulation index
(V) (rnF) (mH) (ohm) (mH) (Hz) (Hz) (U)
3600 4 3.5 3 10 10 1650 50 0.7
5.2 Circulating Current PI Controller Gain Selection
In both circulating current control loops shown in Figure 3.16, Kp and Ki are
derived as follows [4]:
Kp Tarm/'n
Ki Rarm/^i
(5.1)
where t\ is the time constant of the circulating current control loop. t\ is a design
choice, and it is generally selected in the range of 0.5-5 ms [4]. In our study it is
chosen 0.2 ms to have faster response. So Kp which is used here equals 15 and Ki
becomes 20.
5.3 Simulation Results
Main parameter to implement fault localization algorithm is observer gain (Ke) as
mentioned in the previous chapter. To show how it affects the duration to locate faulty
module two different gains are used here. Necessity for observer stability is shown in
equation 4.8. If Ke is chosen high enough, it is expected to see that estimation follows
measurement after generating the fault and when capacitor voltages in the same arm
39


reach Vthreshoid it starts to diverge slightly. So, it takes much time to exceed AV
between Vc^jk and Vc^jk&et to locate faulty SM. To sample this scenario open circuit
fault in Al of first SM in the upper arm of phase C is generated at 0.8 sec. Also,
CCSC is activated at 0.3 sec to show how to minimize it.
5.3.1 A'e=50
In Figure 5.1 it is seen that until the fault happens both upper-lower arm ca-
pacitor voltages are slightly varying around 900 V which is VdJ4 and it proves that
balancing algorithm is able to equalize the SM capacitor voltages.
Figure 5.1: Phase C Upper-Lower Arm Capacitor Voltages
Figure 5.2 shows the circulating currents in 3 phase of MMC system. It is observed
from the figure that controller suppresses the circulating currents when it is activated
at 0.3 sec. Capacitor voltage variation becomes smaller by means of it. As soon as
fault happens because of Vdiffj it gets higher.
Figures 5.3, 5.4, 5.5 and 5.6 depict the comparison between the estimation and
measurement of phase C upper arm capacitor voltages respectively. From the figures
it is deduced that observed states reach measurement from its initial value which is 500
V in here and in case of fault faulty module capacitor voltage estimation diverges from
40


Figure 5.2: 3 Phase Circulating Currents
measurement because of the error after reaching Vthreshoid. as shown in equation 4.2.
In Figure 5.3, first SM in the upper arm of phase C is compared with its estimation.
Figure 5.3: Phase C Vv£\ and Vucieat
Unlike the others this is slightly diverging from measurement and it shows us
this is faulty one, but for localization difference voltage which is specified as 100 V
41


isnt enough. So we understand that because of high observation gain it is recovering
the error which is caused by open circuit fault in the module. Rest of the figures
estimation follows the measurement for healthy ones perfectly.
Figure 5.4: Phase C Vuc2 and Vuc2eet
Figure 5.5: Phase C Fwc3 and Vuc3est
It is understood from the Figure 5.7 that even all SM capacitor voltages exceed
Vthreshoid, for fault detection because of high gain selection observed state doesnt show
42


1400
Figure 5.6: Phase C Vuca and VUCAeat
Time (sec)
Figure 5.7: Fault Status of SMs
divergent behaviour to locate the fault within reasonable time. Thus fault status of
all SMs stays 0.
5.3.2 I If observer gain is chosen small enough which still needs to be greater than zero,
it is seen that the divergence between measurement and estimation of state becomes
43


more clear and it helps us to detect and address the fault faster. Related figures
which are 5.8 and 5.9 are shown below.
i___________________________i___________________________i___________________________i___________________________i___________________________i__________________________i___________________________i___________________________i___________________________i___________________________i
0 0.2 0.4 D6 0.8 1 12 14 1.6 10 2
Time (sec)
Figure 5.9: Fault Status of SMs for Ke=0.1
44


5.4 Discussion
If the Figures 5.3 and 5.8 are considered, it is detected that observer gain selection
plays an important role to locate the faulty module within a reasonable time. For
small observer gain error between the measurement and estimation for each error step
increments. Also it is selective design criteria that observer response for smaller gain
is sluggish.
As it is seen from the Figure 5.9 fault is located within approximately 0.4 sec
which can be considered high for real system applications, but as it is mentioned in
chapter 4 fault detection part, for the real MMC systems which contain hundreds
of MMCs this fault detection level (Ithreshold) can be kept within the small range.
For instance, in this study if 10 SMs per arm were used instead 4 SMs at the same
switching frequency, fault detection voltage level which is extracted from the equation
4.2 and given below would be 400 V for each SM instead of 1200 V. Thus, that means
it takes smaller time to detect and locate it.
Vr
cth r&shold
Vdc
IT' IT* faulty
3600
10 I
400(F)
45


6. Conclusion
In this thesis, 5 level three phase MMC inverter with RL load is designed to
propose the fault detection and localization algorithms based on SM capacitor voltage
measurement and estimation. The various components involved in the realization of
power circuit are described and the control approach is explained in parts. In addition,
the design guideline of the system parameters and tuning methods for PI controllers
used in circulating current suppression controller are expressed. The proposed system
is implemented via detailed Matlab/Simulink computer simulations.
It is shown in the MMC control part that employed capacitor voltage balancing
algorithm which is similar to reduced switching frequency approach given in refer-
ence papers operates as desired by equalizing the arm capacitor voltages. PS-PWM
modulation which is preferred multi-carrier PWM technique in this study provides
less oscillatory current waveforms than PD-PWM method in comparison. Addi-
tionally, implemented circulating current controller minimizes circulating currents in
three phase by narrowing voltage variation of capacitor voltages and provides inner
unbalance voltage reference to be used in arm modulating signal reference calculation.
To detect the fault and locate the faulty module state observer approach based
on comparison between SM capacitor voltage measurement and estimation is used.
Design of observer and how observer gain (Ke) selection effects localization period as
a critical point is explained. Moreover, by comparing the simulation results for two
different gain values it is verified.
As contribution apart from the other methods which is already proposed in the
papers, different approach is suggested for open circuit fault detection and localization
in MMC system.
46


7. Future Work
The possible future works can be listed as follows:
Study on the observer gain (Ke) selection which matters for fault detection and
localization period in case of healthy and faulty conditions.
The observer approach for fault detection and localization can be applied for
the other types of faults in SM or converter level.
47


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51


Appendix A. Park Transformation
Park transformation theory is used to transform three-phase abc reference frame
quantities to the dq reference frame quantities. In this transform theory, it is assumed
that the dq reference frame is rotating at synchronous speed with respect to the abc
reference frame with a phase angle 9. The reference frames are shown in Figure
A.l. Also, Park transformation can be reversed, which means dq quantities can be
transform back to abc quantities.
Figure A.l: The stationary abc reference frame and the rotating dq reference frame
The dq quantities relate to the abc counterparts according to
V _____ rpdq -y-
^dq ^abc^abc)
___ rriabc y
abc -^dq -^-dqj
where T^c represents the Park transformation matrix,
rn dq
1 abc
cos(0) cos[9 -
- sin(0) sin(0
2tt. 2vr.
) cos{9 + )
27i". . 2tt.
) -sm(9 + y)j
52


stands for the inverse Park transformation matrix
and T^c
rnabc
1dq
cos {()) sin(0)
cos(0 y) -sin(0 y)
cos(0 V7~) sin(0 V7~)
3 'J
53


Full Text

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OPENCIRCUITFAULTDETECTIONANDLOCALIZATIONTHROUGH STATEOBSERVERINMODULARMULTILEVELINVERTER by MUSTAFASEN BachelorofScience,YildizTechnicalUniversity,2011 Athesissubmittedtothe FacultyoftheGraduateSchoolofthe UniversityofColoradoinpartialfulllment oftherequirementsforthedegreeof MasterofScience ElectricalEngineering 2016

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c 2016 MUSTAFASEN ALLRIGHTSRESERVED

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ThisthesisfortheMasterofSciencedegreeby MustafaSen hasbeenapprovedforthe DepartmentofElectricalEngineering by JaedoPark,Chair JanBialasiewicz DanConnors March11,2016 iii

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Sen,MustafaM.S.,ElectricalEngineering OpenCircuitFaultDetectionandLocalizationThroughStateObserverInModular MultilevelInverter ThesisdirectedbyAssistantProfessorJaedoPark ABSTRACT ModularmultilevelconvertersMMChavebecomeattractivesincebeingproposedbyMarquardtin2001[1]bymeansofbeingavailableformediumandhigh voltage/powerapplicationsinthewayofsuchpropertiesasmodularity,eciency, highoutputvoltageandpowerqualityapartfrombeingalternativeapproachforconventionalpowerconverters.Accordingtoproposedmultilevelconvertertopologies, MMCsarecomprisedofmanysubmodulesSMswhicharemadeofsemiconductors suchasisolatedgatebipolartransistorsIGBTsanddiodes.However,becauseof itsdesignreliabilityisstillproblemtobehandled.Oneofthebiggestproblemsthat threatenssustainabilityofMMCsystemoperationisopencircuitfaultsinIGBTs inSMs.Inthisthesisstateobserverwhichisusedinsmallscale"5level"MMC invertersystemtoobserve,detectandlocatethefaultrelatedwithSMcapacitor voltages.PhaseshiftedpulsewidthmodulationPS{PWM,voltagebalancingsortingalgorithmwhichissimilarwithreducedswitchingfrequencyRSFmethodand circulatingcurrentsuppressioncontrollerCCSC[2]areappliedtogetresultinopen loopcondition.ThemethodisimplementedviadetailedMatlab/Simulinkcomputer simulations. Theformandcontentofthisabstractareapproved.Irecommenditspublication. Approved:JaedoPark iv

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ACKNOWLEDGEMENT Atrst,Iwouldliketothanktomyadvisor,Dr.JaedoPark,forhisguidance, valuableadviceandsupportduringthewholeperiodofthestudy. Also,Igreatlythankandacknowledgetheinvaluablesupportsandguidanceof TurkishPetroleumCorporation. IexpressmygratitudetomyfriendsMuhannadAlarajandErsinCanaktheir adviceandhelponmyresearch. IgreatlyappreciateDr.JanBialasiewiczandDr.DanConnorsforformingmy dissertationdefensecommittee,theirvaluablediscussions. Finally,andmostimportantly,Iwouldliketothankmyfamily;theywerealways therecheeringmeupandstoodbymethroughthegoodandbadtimes. v

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DEDICATION Thethesisisdedicatedtomyfamilyandentouragewhohaveencouragedmetogo furtherduringmylife. vi

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TABLEOFCONTENTS Chapter 1.Introduction...................................1 2.SystemModelingandPrinciplesofOperation................10 2.1StructureofMMC............................10 2.2OperationPrinciples...........................12 3.MMCControl..................................19 3.1ModulationMethods..........................19 3.1.1PhaseShiftedPWMPS-PWM................20 3.1.2PhaseDispositionPWMPD-PWM..............22 3.2VoltageBalancingAlgorithm......................27 3.3CirculatingCurrentSuppressionControllerCCSC.........29 4.FaultDetectionandLocalization.......................33 4.1FaultTypesandCharacteristics....................33 4.2ProposedFaultDetectionMethod...................35 4.3ProposedFaultLocalizationMethod..................35 4.3.1DesignofStateObserver.....................36 5.DesignGuidelineandSimulation.......................39 5.1CircuitParameters...........................39 5.2CirculatingCurrentPIControllerGainSelection...........39 5.3SimulationResults............................39 5.3.1 K e =50...............................40 5.3.2 K e =0.1..............................43 5.4Discussion................................45 6.Conclusion....................................46 7.FutureWork...................................47 References ......................................48 vii

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Appendix A.ParkTransformation..............................52 viii

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LISTOFTABLES Table 1.1FaultTypes..................................7 2.1OperationofSM...............................15 4.1FailureCharacteristicsofType1......................34 4.2FailureCharacteristicsofType2......................34 4.3FailureCharacteristicsofType3......................34 5.1SimulationParameters............................39 ix

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LISTOFFIGURES Figure 1.1 TwoLevelThreePhaseVSCTopology ....................2 1.2 ThreeLevelNPCConverter ..........................4 1.3 FlyingCapacitorMultilevelConverter .....................5 1.4 CascadedHalf-BridgeMultilevelConverter ..................6 1.5 MMCInverterTopology ............................7 2.1 VoltageWaveformof2LevelConverter ....................10 2.2 SingleModuleofMMC ............................12 2.3 MMCOutputVoltageSynthesis ........................13 2.4 OverallSystemStructure ...........................14 2.5 SwitchingStatesofSM ............................15 3.1 SinusoidalPWMandOutputWaveformsFor2LevelVSC ..........19 3.2 PS-PWMReferencevsCarriers ........................21 3.3 ActivatedNumberofSMs ...........................21 3.4 PD-PWMReferencevsCarriers ........................22 3.5 ReferenceforNumberofONStateSMs ....................23 3.6 POD-PWMReferencevsCarriers .......................23 3.7 ReferenceforNumberofONStateSMs ....................24 3.8 APOD-PWMReferencevsCarriers ......................24 3.9 ReferenceforNumberofONStateSMs ....................25 3.10 PhaseCArmandInnerDierenceCurrentsforPS{PWM ..........26 3.11 3PhaseCirculatingCurrentsforPS{PWM ..................26 3.12 PhaseCArmandInnerDierenceCurrentsforPD{PWM ..........27 3.13 3PhaseCirculatingCurrentsforPD{PWM ..................27 3.14 ReducedSwitchingFrequencyVoltageBalancingAlgorithm ..........28 3.15 TransferFunctionoftheCirculatingCurrentsindqReferenceFrame .....30 x

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3.16 ClosedLoopd-qAxisCirculatingCurrentControllers .............31 3.17 OverallCirculatingCurrentSuppressionController ..............32 4.1 FaultTypes ..................................33 4.2 FaultDetectionFlowchart ...........................36 4.3 FaultLocalizationFlowchart ..........................37 5.1 PhaseCUpper{LowerArmCapacitorVoltages ................40 5.2 3PhaseCirculatingCurrents .........................41 5.3 PhaseC V uc 1 and V uc 1 est ............................41 5.4 PhaseC V uc 2 and V uc 2 est ............................42 5.5 PhaseC V uc 3 and V uc 3 est ............................42 5.6 PhaseC V uc 4 and V uc 4 est ............................43 5.7 FaultStatusofSMs ..............................43 5.8 PhaseC V uc 1 and V uc 1 est for K e =0.1 ......................44 5.9 FaultStatusofSMsfor K e =0.1 ........................44 A.1 Thestationaryabcreferenceframeandtherotatingdqreferenceframe ...52 xi

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1.Introduction Developmentsforthenewtechnologiesinthelastcenturyincreasedtheattentioninelectricpowersystems.Studiesonelectricpowergeneration,conversionand transmissiondeviceshavebecomemoreandmoreimportantdaybyday.Also,to protectandpreservetheenvironmentfromthepollutionwhichiscausedbynuclear andfossilenergysourceslikeoil,coalandnaturalgastheinterestinelectricalpower generationfromgreenenergyrenewablesourcessuchaswindpowerandsolarsystemshasbeenenhancedandtheyaresupposedtoplayimportantroleinworld-wide energyproductioninthefollowingyears.Notonlyindustrialapplicationseventhe electricalnetworkrequirementsdisplaytheimportanceofenergysupplyandcontrol intherecentresearches.Asaconsequence,powerconversionandcontrolinpower transmissionprocesshastobereliable,safeandavailableinordertoaccomplishall therequirements. In[3]itisstatedthatinapowertransmissionsystemthemostimportantprocess istocontrolactiveandreactivepowerowtokeepthesystemvoltagestable.This goalcanbeaccomplishedbyuseofpowerconvertersthroughitsabilitytoconvert energyfromDCtoACorviceversa.Sofartherehasbeentwotypesofcongurations asregardsthreephasepowerconverterswhichhighvoltagedirectcurrentHVDC transmissionsystemcanutilize.Theseareconventionalvoltagesourceconverters VSCswhichiscommonlyusedintheareaandshowninFigure1.1andcurrent sourceconvertersCSCs.MaincharacteristicofVSCsisthatasitisshowninFigure 1.1itisacompositionofthreeidenticalhalf{bridgeconvertersanditoperateswith speciedvectorcontrolstrategywhichcanperformactiveandreactivepowercontrol separately[4].ThismakesitconvenientforconnectiontoweakACnetworkswithout localvoltagesources.Also,duringthepowerreversaltheDCvoltagepolarityremains thesameforVSCsbasedtransmissionsystemandthepowertransferdependsononly thedirectionoftheDCcurrent.Ontheotherhand,inaCurrentSourceConverterthe 1

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DCcurrentisxedwithasmallrippleusingalargeinductor,thusformingacurrent sourceontheDCside.ThedirectionofpowerowthroughaCSCsisdeterminedby thepolarityoftheDCvoltagewhilethedirectionofcurrentowremainsthesame. Figure1.1: TwoLevelThreePhaseVSCTopology Althoughthesepowerconvertershavelatelybeenusedinhighvoltagedirect currentHVDCpowertransmissionapplications,However,accordingto[5]there aresomedrawbacksforboth.CSCsrequirelargereactivepowerquantitiesduring theprocessanditisinconvenienttocontrolactiveandreactivepowerindependently. Also,becauseofgeneratinglowfrequencyharmonicsitcauseslossesandexpensive ltersneeded.Additionally,conventional2levelVSCsproducelargehighfrequency harmonicswhichresultinbiggerlossestocomparewithCSCsduetohigherswitching frequencies.Moreover,itsdesignneedalargenumberofswitchesthatareconnected inseries.Thus,thissituationmaycausemultiplefailurepoints. Toovercometheseproblemsseveraldierentmultileveltopologieshavebeenproposedandthemainreasonfortheinterestonmultilevelconvertersinsteadconven2

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tionaltwo-levelconvertersliesintheimprovedqualityoftheiroutputwaveform, possibilitytoachievehigherpowerlevelsandhighereciency[6].Someofthemost commonmultileveltopologiesare: Neutral-PointClampedNPC FlyingCapacitorFC CascadedH-BridgeCHB ModularMultilevelConvertersMMC TheNPCmultilevelconverterwasinitiallyproposedasathree-levelinverteras showninFigure1.2.Themidpointoftheswitchesisconnectedtotheneutralpoint oftheconverterovertheclampingdiodes,soitenableszerovoltagelevelgeneration. Thankstothis,forthesameDC-linkvoltage,thevoltagewhichthedevicesinthe converterhavetotolerateisreducedtohalfincomparisonwiththetwo-leveltopology.Onthecontrary,thistopologyhasseveraldisadvantagessuchasundercertain operatingconditionstheNPCconvertermayexperienceunbalancedcapacitorvoltages,creatingapotentialbetweentheneutralpointandgroundandcausingdistorted outputwaveforms. InFCconvertertopologywhichisshowninFigure1.3,eachcapacitorinthe phaseischargedtoadierentvoltagelevel,thereforebychangingthestatesofthe switches,variousoutputvoltagelevelscanbeobtained[7].Thistopologycanhave phaseredundantswitchingstatesthatcanbeusedforcapacitorvoltageregulation anditbringssortofadvantagecomparedtotheNPCconvertertopology.Intheway oftheenergystorageinthecapacitors,theconvertercanridethroughshortduration outages.Asadisadvantage,beforethestart-up,capacitorshavetobepre-charged whichisknownasinitialisationasrequirement.Alsothistopologypresentsunequal dutydistributionbetweentheswitches.EventhoughtheFCconvertertopologycan 3

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Figure1.2: ThreeLevelNPCConverter beextendedtoanarbitrarynumberofcells,theadditionofcapacitorsleadstoan increaseincost.Thusthenumberoflevelisusuallylimitedwithfour[6,8]. TheCHBtopologyisbasedontheseriesconnectionofsingle-phasefull-bridge invertercellswithisolatedDCsupplies.ItisdemonstratedbelowinFigure1.4.The mainadvantagesoftheCHBtopologyovertheNPCandFConesareitsmodular structureandthepossibilitytohaveanindependentcontroloverthezero-sequence componentinthecurrent.Incaseofrectierapplications,theneedofmanyisolated DCsourcesinserieslimitsthenumberofcellsintheleg,keepingthistopology unfavourableforbidirectionalpowerapplications[4,6].However,aproposalforCHB approachinHVDCapplicationsusingare-injectioncircuitcanbefoundin[8]. SinceMMCswereproposedtobealternativeapproachforexistingones,they havebecomecommerciallyattractiveformediumandhighpowerapplicationsand broughtmanyadvantagesoverconventionaltypesofconverters[9{12].InFigure1.5 n +1"levelMMCInvertertopologyisshown.Thesebenetsaremainly 4

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Figure1.3: FlyingCapacitorMultilevelConverter modularityandscalability lowerswitchingfrequencyofindividuallevels,soincomparisonwithtraditionalVSCsobtainingthesamewaveformpropertieswithlowerswitchinglosses improvedreliabilityincasesomemoduleshavefaultasconvertercanfunction magnitudeofharmonicsissignicantlyreducedorpossiblyeliminated,thereforenoneedforlterbanks exiblecontrolofthevoltagelevelandsimplerealizationofredundancyif required norequirementforexpensivetransformers Ontheotherhand,oneofthebiggestchallengesaboutMMCsisreliability.MMCs consistofalargenumberofpowerswitchingdevicessuchasIGBTsinSMsdepends 5

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Figure1.4: CascadedHalf-BridgeMultilevelConverter onvolumeoftheapplicationandtheseswitcheshavetobetakenintoconsideration aspotentialfailurepoints.Accordingtotable1.1whichshowsSMandconverter levelfaultsrespectivelyandalsoisgivenin[13],inSMlevel,faultswhicharerelated withIGBTssuchasopencircuitandintermittentgatemisringfaultsareshownas oneofthemostcommonfaulttypeswhichmaydisrupttheoperationofMMCor evendestroyitduetoeectoncurrentandvoltageinMMC[14].Soitisclearthat faultdetectionandlocalizationinashorttimeafteroccurrencearereallyvitalfor sustainabilityoftheMMCoperation. Thereareseveralmethodsthatareproposedonopencircuitfaultdetectionin MMC.In[15],KalmanFitering iv isbeingrecommendedtodetectthefaultconditionbymeansofcomparisonbetweenthemeasuredandestimatedinnerdierence 6

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Figure1.5: MMCInverterTopology Table1.1:FaultTypes Sub-modulelevel Capacitor Faultincapacitorstructure Diode Opendiodefaults ShortCircuitFaults IGBT Opencircuitfaults Intermittentgatemisringfaults Converterlevel Capacitorvoltageunbalance Circulatingcurrentamongthreephaseunit Unbalancebetweenupperandlowerarmvoltage Controlofenergystoredintheleg Singlephasetogroundfault Doublephasetogroundfault Triplephasetogroundfault currentbasedonspeciedcurrentdierencethresholdforsomecertainperiod.After faultisdetected,SMcapacitorvoltagesintheconcernedphasewhichisidentiedas 7

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faultyarecomparedwithminimumcapacitorvoltagevalueinthesamearmforsome thresholdperiodandvaluetolocatefaultySMintheupper n lowerarm.Another proposedmethodisbasedonslidingmodeobserverSMOwhichhasbeenpresented in[16].Inhere,voltageandcurrentrelationshipsbetweenthebothsidesofSMsare calculatedundernormalandopencircuitfaultcaseineachswitch.ThroughSMO estimatedandactualstatesarecomparedifdierencebetweenthemismorethan thresholdvalueforcertainperiodwhichisalreadyspeciedintermsofsystemssensitivity,faultisdetectedinthisway.Accordingto[17],itisstatedthatthisSMO methodisaccurate,butnotfastforMMCswithhighnumberofSMs.Inthiscase,it maybeencounteredwithadditionaldamagesbecauseofinstantincreaseoffaultySM capacitorvoltages.So,itsuggestsdierentmethodwhichisbasedonvoltageacross inductorandarmcurrentobservationintheupper n lowerarmsinanyphaseinstead ofusingobservertomakethisprocessfaster.Anotherpresentedapproachrelieson adaptivebacksteppingobservertotakeplaceofsensorsandreducethecomplexityof implementationwhichisgivenin[18]. Apartfromthesemethods,stateobserverscanbedesignedtodetectandlocate theopencircuitfaultsinSMsbyreducingnumberofmeasurementsensorsinparallel withtotalcostbyestimatingcapacitorvoltagesandoutputcurrents[19].Inthisthesis study,designofstateobserverapproachforlinearsystemsisbenettedtoestimate capacitorvoltagesinSMslocatethefaultymoduletobealternativeforexisting approaches.ToobtainproperresultsinopenloopconditionPS{PWMtechnique andvoltagebalancingalgorithmwhichissimilarwiththewayexpressedin[2]are employedin5LevelMMCinverter.In[20],PS{PWMispresentedandtechnical aspectsarediscussed. Thethesisisorganizedinfollowingway;inchapter2,structuremodellingand operationalprinciplesofMMCareexplained.Afterwards,chapter3isaboutcontrol approachrelatedwiththepreferredPWMtechnique,thecapacitorvoltagebalancing 8

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algorithmandcirculatingcurrentsuppressioncontrolCCSC.Inchapter4,fault types,characteristicsonSMswithproposedfaultdetectionandlocalizationmethodsareexplained.Chapter5isincludingdesignguidelineandsimulationresults. Conclusionisaddedinchapter6. 9

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2.SystemModelingandPrinciplesofOperation 2.1StructureofMMC ItcanbestatedthatMMCsaresortofVSCandtherelatedprinciplesofoperation forVSCscanbeappliedtoit.Becauseifonly2SMswereusedinMMCwecould saythatoneforpositiveDCconnectionandtheotheroneisnegative,synthesized outputvoltagewaveformwouldbeinFigure2.1whichislike2levelvoltagesource converter.So,operationofthisMMCwouldbeequivalenttoVSC.Also,Itcanbe usedasrectierandinverterinbacktobackHVDCpowertransmissionsystemsthat Siemenshasaplanofputtingthisconverterintopracticalapplicationswiththetrade nameHVDC-plus".ThesystemcongurationoftheHVDC-plushasapowerof400 MVA,adclinkvoltageof200kV,andeacharmcomposedof200SMs[21]. Figure2.1: VoltageWaveformof2LevelConverter Additionally,TheMMCcongurationalsooersmoreadvantagesoverthetraditionalVSCs[5].Theseare Notalltheswitchesinalegareopenedorclosedatthesametimeasthey wouldinatwo-levelVSC,buttheyareoperatedatdierenttimeinstantsto followthesinusoidalreferencecommandmoreclosely,theswitchingfrequency ofeachswitchcanthusbelow,whilestillgeneratingalargeapparentswitching frequency. Thevoltageblockingrequirementsofanindividualswitchislimitedtothe voltageacrossthemodule'scapacitor. 10

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Ifenoughmodulesareused,thevoltageacrosseachswitchcanbelowenough nottorequireseriesconnectedswitches.Ina2-levelVSC,eacharmvalve mustbeabletoblockseveralhundredsofkVswhileopen.AnIGBTisusually ratedforafewkVsonly,somultipleswitchesmustbeconnectedinseries toachievethedesiredblockingcapabilities.Duringswitching,allthesedevices mustoperatetogether.IfoneIGBToperationisdelayed,itisexposedtoahigh voltage,whichcoulddamageit.InthecaseoftheMMC,thehighnumberof modules,eachonlyblockingthevoltageacrossitsinternalcapacitoreliminates thisdrawbackandimprovesthefailurerate. Themodularconceptallowsoperationevenifsomemoduleshavefailed.Failed modulescansimplybebypassed,andkeptbypasseduntilitispossibletoreplace them,andoperationcancontinue.TheDCbusvoltageisthendividedamong theremainingN-1modulesandnormaloperationcancontinue. ItispossibletodesignaMMCconverterwithsparemoduleswhichcanbe usedifonemoduleweretofails.Ifsparemodulesareavailable,theycanbe insertedinthearmasneeded. AsitcanbeseenfromtheFigure2.4thatdemonstratestheoverallsystem,SM isthebasicbuildingcellforMMC.TheremaybehundredsorthousandsofSMsin MMCintermsofrequiredpowerleveldependsonapplication[22].SMsconsistof twoIGBTs S 1 ;S 2 ,twodiodes D 1 ;D 2 whichareconnectedinparallelwiththem andasubmodulecapacitor C sm .Alsothesediodesareusedduetoprotectionof IGBTswitches.Figure2.2showsSMdiagram. Inathree{phaseMMCsystem,foreachphasetherearephaselegswhichare composedofupperandlowerarms.Thesearmsareformedbyseriesconnectedn" numberofSMs.Thereisalsoaninductorineacharm, L arm ,inordertosmooth thevoltagedierencetoreducecirculatingcurrentsbetweenphaseunitsthatis 11

PAGE 23

Figure2.2: SingleModuleofMMC producedwhenaSMisconnectedordisconnected[23]. 2.2OperationPrinciples Thegeneralconceptofmultilevelconverteristhesynthesisofasinusoidalvoltage byseverallevelsofvoltages.IncaseofMMC,thesevoltagelevelsareobtainedfrom thecapacitorvoltages, V c ,ofeachSM.Atanyinstant,anumberofSMsthatare switchedonequalsn"totallywhichisincludingupperandlowerarminanyphase, sothatthevoltageattheconverterterminalsequalstheinstantaneousvalueofthe voltagetobesynthesized[24]asitisshownininFigure2.3whichareoutputvoltages of3,5and9levelMMCsvariesbetween V dc = 2respectively.Asitisseenifnumber ofvoltagelevelisincreased,resolutionofsinusoidalwaveformfortheoutputvoltage getsbetter.Besides,average V c isdenotedas V c = V dc n .1 AsregardsgatesignalofrelatedIGBTswitchSMhastwostatesinnormal operation.TheseareON"andOFF"states.Figure2.5indicatestheconcerned statesrespectively. ONState| S 1 isswitchedon, S 2 isswitchedo AsupperIGBTisintheconductingmodeinanySMinanyphase, V c equalsto 12

PAGE 24

Figure2.3: MMCOutputVoltageSynthesis theSMoutputvoltage V c = V sm regardlessofcurrentdirection.Ifthecurrent ispositiveitfreewheelsthroughanti-paralleldiode D 1 and V c increasesorwhen currentpolarityisnegativeitowsthroughthe S 1 anddischargesthe C sm OState| S 1 isswitchedo, S 2 isswitchedon Inhere,the V sm doesn'tchange.BecauserelatedSMisbypassed.Armcurrent eitherowsthroughthe S 2 orthe D 2 dependingonitsdirection.Thereby, V sm iszero. Table2.1showstheoperationalstatusoftheSMintermsofcomplementary switchingstatesofIGBTs.Also,therelationbetween V sm and V c canbeformulated inthefollowingway: 13

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Figure2.4: OverallSystemStructure 14

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Figure2.5: SwitchingStatesofSM V sm ; ijk = S ijk V c ; ijk .2 Table2.1:OperationofSM SMStateS S 1 S 2 V sm ArmCurrent C sm V c ON1ONOFF V c PositiveChargeIncreased NegativeDischargeDecreased OFF0OFFON0PositiveBypassUnchanged Negative ThearmvoltagecanbecomputedconsideringthestatusoftheSM'sswitches, s ijk ,asfollows[25]: V ij = n X k =1 S ijk V c ; ijk .3 15

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where i = u;` representstheupperandlowerarm,respectively; j = a;b;c isthe phase;and k =1 ; 2 ;:::;n denotestheSM.Thearmcurrentscanbedeterminedas I uj = I j 2 + I diff j .4 I `j = )]TJ/F18 11.9552 Tf 10.494 8.088 Td [(I j 2 + I diff j .5 Accordingto[26] I diff j hastwocomponents.Theseareonethirdofdcsource current I dc = 3andtheotherpartiscirculatingcurrent I circ;j .Sotheprevious equationcanbewritteninthefollowingway. I uj = I j 2 + I dc 3 + I circ ; j ; .6 I ` j = )]TJ/F18 11.9552 Tf 10.494 8.088 Td [(I j 2 + I dc 3 + I circ ; j .7 where I circ j isthecirculatingcurrentforphase j ,and I circ a + I circ b + I circ c =0.These circulatingcurrentshavenoeectontheacsideordcsidevoltages.Itcanbeproved basedonarmcurrentequationsasitisdemonstratedbelow[5].Ontheotherhand, theyhavesignicantimpactonSM'scapacitorvoltagesandtheratingvaluesofthe MMCcomponents[25]. I ua = I a 2 + I dc 3 + I circ ; a = I dc 3 + I circ ; a + I ua )]TJ/F18 11.9552 Tf 11.956 0 Td [(I ` a 2 .8 So I circ;a becomes I circ;a = )]TJ/F18 11.9552 Tf 10.494 8.088 Td [(I dc 3 + I ua )]TJ/F18 11.9552 Tf 13.151 8.088 Td [(I ua )]TJ/F18 11.9552 Tf 11.955 0 Td [(I ` a 2 = )]TJ/F18 11.9552 Tf 10.494 8.088 Td [(I dc 3 + I ua + I ` a 2 .9 I circ;b and I circ;c canalsobedenedasinthefollowing. 16

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I circ;b = )]TJ/F18 11.9552 Tf 10.494 8.087 Td [(I dc 3 + I ub + I ` b 2 .10 I circ;c = )]TJ/F18 11.9552 Tf 10.494 8.088 Td [(I dc 3 + I uc + I ` c 2 .11 Bysummingallthreecirculatingcurrentsitisobtainedthat I circ;a + I circ;b + I circ;c = )]TJ/F18 11.9552 Tf 13.15 8.088 Td [(I dc 3 + I ua + I ` a 2 )]TJ/F18 11.9552 Tf 13.15 8.088 Td [(I dc 3 + I ub + I ` b 2 )]TJ/F18 11.9552 Tf 13.15 8.087 Td [(I dc 3 + I uc + I ` c 2 I circ;a + I circ;b + I circ;c = )]TJ/F18 11.9552 Tf 9.299 0 Td [(I dc + I ua + I ub + I uc + I ` a + I ` b + I ` c 2 = )]TJ/F18 11.9552 Tf 9.299 0 Td [(I dc + I dc + I dc 2 =0 .12 Simultaneously,correlationbetweenacsideanddcsidevoltagesoftheMMCisextractedthroughKircho'sVoltageandCurrentLawsKVL-KCL. V dc 2 = V uj + L arm dI uj dt + R arm I uj + V j = V ` j + L arm dI ` j dt + R arm I ` j )]TJ/F18 11.9552 Tf 11.955 0 Td [(V j V dc = V uj + V ` j + L arm dI uj dt + dI ` j dt + R arm I uj + I ` j V j = 1 2 V ` j )]TJ/F18 11.9552 Tf 11.955 0 Td [(V uj )]TJ/F18 11.9552 Tf 11.955 0 Td [(L arm dI j dt )]TJ/F18 11.9552 Tf 11.955 0 Td [(R arm I j V di j = L dI di j dt + R arm I di j = 1 2 V dc )]TJ/F18 11.9552 Tf 11.955 0 Td [(V uj )]TJ/F18 11.9552 Tf 11.955 0 Td [(V ` j .13 where V di j representsinnervoltagedierencebetweenphaseunitsinMMCand R arm istheequivalentresistanceoftheSMsinanarm.ItisrelatedtonumberoftheSMs inanarmviatheresistanceofoneofSM'sIGBTswitch, R sm 17

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R arm = nR sm : .14 Equivalentconverterarmcapacitance C arm whennmodulesareinsertedinthe relatedconverterarmequalstothetotalcapacitanceofthenseriesconnectedsubmodulecapacitorsasitisshowninequation2.15. C arm = C sm =n .15 18

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3.MMCControl 3.1ModulationMethods IftwolevelVSCwhichisintheformofhalfbridgecircuitasitisshowninFigure 1.1isconsidered,conventionalpulsewidthmodulationwhichisusingonemodulating signalandonecarrierwaveformstogenerategatesignalsforcomplimentaryIGBT switchesinthesamephase[4].Figure3.1picturesanexampleforsinusoidalpulse widthmodulationandtheresult.AsitisseenfromtheFigure3.1modulatingsignal iscomparedwithtriangularcarrierwavesignal.Asaresultofit,incasemodulating signalishigherthancarrier,thismeansupperIGBTinVSCison,otherwiseifitis lowerthancarrier,loweroneison.ThisPWMmethodisrepeatedwithproperphase shiftsintermsofotherphaseswhen3phasetwolevelVSCisused. Formodularmultilevelconverters,thereareseveralofthesehalf-bridgecircuits SMsthatallofthemhastobeindividuallycontrolled.Thesolutionforthisisto usemulti-carrierPWMmethodswhichmeansthatonecarrierwaveformforeachSM inMMC. Figure3.1: SinusoidalPWMandOutputWaveformsFor2LevelVSC In[10]and[27]detailsaboutmultilevelconverterPWMmethodsaregiven.There aretwospeciedmethodsintermsofMMCmulti{carriermodulationtechniques. Thesearephase-shiftedandphasedispositionPWMmethods.Forbothmethods 19

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thereisonecarrierwaveformforeachSMintheupper n lowerarmoftheMMC phaseleg.Inbothmethods,multiplecarrierwaveformsfornumberofSMsinthe relatedarmarecomparedwithsinglearmvoltagereferencesignalmodulatingand thiscomparisondictateshowmanysubmodulesneedtobeswitchedonorbypassed. Apartfromthesemethodsthereareothermultilevelmodulationtechniquessuchas NearestLevelModulationNLMandSpaceVectorModulationSVM.However, thesemethodshavesomedrawbacks[28].Forinstance,NLMtechniqueissuitable withtheconverterswhichhavelargenumberofSMsduetosmallvoltagesteps.This meansifitisusedwithsmallscaleMMCwhichmeanslownumberofswitchings thismaycauselargervoltageuctuationinthecapacitorvoltagesandSVMbrings implementationcomplexity. 3.1.1PhaseShiftedPWMPS-PWM Phase-shiftedPWMformodularmultilevelconvertersuseonecarrierforeach submoduleintheMMCandthesecarrierwaveformshavethesameamplitudeand frequencywhichareshiftedby whichdependsonnumberofSMsinthearm.This angle iscalculatedusingtheequation3.1. = 360 n .1 n"indicatesnumberofSMsinanarm.Twokeyparametersaretheamplitudeand frequencymodulationindexinthismethod[20].Theequationstocalculatethese parametersareshowninequations3.2and3.3.Thefrequencymodulationindex m f relatesthefrequencyofthecarrierwave f c tothefrequencyofthereference sinewave f r m f = f c f r .2 Theamplitudemodulationindexistheratiooftheamplitudeofthecarrierwaveform andreferencewaveform. 20

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m a = A r A c 2 .3 Figure3.2showsanexampleofPSC-PWMwith4carrierand1referencewaveformswhichdictateshowmanysubmodulesneedtobeinsertedinthearminorder toachievethedesiredvoltagelevelasitisreectedinFigure3.3.Alsothereis2 = 4 phaseshiftbetweeneachcarrierwaveformwhichsatisesequation3.1. Figure3.2: PS-PWMReferencevsCarriers Figure3.3: ActivatedNumberofSMs 21

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3.1.2PhaseDispositionPWMPD-PWM PhaseDisposedPWMissimilartothepreviouslydescribedmethodsinthatagain thenumberofcarrierwaveformsisequaltothenumberofsubmodulesineacharm. Alsothesameamplitude.Thedierencesarethatthereisnophaseshiftbetween thecarriersandtheyaredisplacedwithrespecttozeroaxis.Alsoamplitudeofthem A c dependsontheequationshowninequation3.4 A c = 1 n .4 In[29]itisstatedthattherearevarioustypesofphasedisposedPWMtechniques whichdependonwhetherornotthecarrierwaveformsare0degreesoutofphaseor 180degreesoutofphase.Therstisphase-dispositionPWM.Figure3.4showsan exampleofphase-dispositionPWMbyshowing4carrierwaveformssuperimposed withasinglesinusoidalreferencewaveform.Figure3.5showsthereferencesignal usingPD-PWM. Here,eachcarrierwaveformhasthesamefrequencyandphasebutamplitudeof carriersis0.25whichiscalculatedbyusingtheequation3.4. Figure3.4: PD-PWMReferencevsCarriers 22

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Figure3.5: ReferenceforNumberofONStateSMs Thenextlevel-shiftedtechniquediscussedisphaseoppositedispositionPWM whichisidenticaltophase-dispositionPWMexceptthatthelowerhalfcarrierwaveformsare180degreesoutofphase.Figure3.6showsthecarrierwaveformsforphase oppositedispositionPWMandwecanseethatthebottomhalfcarrierwaveformsare 180degreesoutofphase.Figure3.7thenshowstheresultantwaveform. Figure3.6: POD-PWMReferencevsCarriers 23

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Figure3.7: ReferenceforNumberofONStateSMs Thenallevel-shiftedtechniquetobeinvestigatedisalternatingphaseopposite dispositionPWMinwhicheveryothercarrierwaveformisphaseshifted180degrees outofphase.Figure3.8showsthecarrierwaveformsforAPOD-PWMandFigure 3.9showstheresultantwaveform. Figure3.8: APOD-PWMReferencevsCarriers Inthisthesis,PS-PWMmethodischosenbasedontheassumptionsgiveninthe [30]whichsaysconciselyPS-PWMcanautomaticallysuppressloworderharmonics 24

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Figure3.9: ReferenceforNumberofONStateSMs forMMCs.Alsowhenthesimulationwhichisusedinthetheisstudyisrunwith PS-PWMandPD{PWMseperately,Figures3.10and3.11showthatphaseCarm currents,innerdierencecurrentwhichisincludingcirculatingcurrentasexplainedin chapter2havelessoscillationincomparisonwiththeFigures3.12and3.13obtained byuseofPD{PWMmethod.Alsomodulatingsignals M uj ref = V uj ref ;M `j ref = V `j ref whichmeansvoltagereferencesfortheupperandlowerarmsasinputforPWM blockinanyphaseofMMCiscalculatedinthefollowingway[31]; V uj ref = V dc 2 )]TJ/F18 11.9552 Tf 11.955 0 Td [(V diff;j ref )]TJ/F18 11.9552 Tf 11.955 0 Td [(V j ref .5 V `j ref = V dc 2 )]TJ/F18 11.9552 Tf 11.955 0 Td [(V diff;j ref + V j ref .6 V j ref representsthedesiredoutputphasevoltageofMMC[32]andcanbeexpressed as V a ref = V dc 2 mcos !t + .7 V b ref = V dc 2 mcos !t + )]TJ/F15 11.9552 Tf 13.151 8.087 Td [(2 3 .8 25

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V c ref = V dc 2 mcos !t + + 2 3 .9 m"demonstratesamplitudeofmodulationindexwhichvariesbetween0and1. and arephasefrequencyandinitialphaseanglerespectively.Also V diff;j ref isthe referenceinnerunbalancevoltageasexplainedinchapter2anditisobtainedfrom CCSCblockasitisshowninFigure3.17. Figure3.10: PhaseCArmandInnerDierenceCurrentsforPS{PWM Figure3.11: 3PhaseCirculatingCurrentsforPS{PWM 26

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Figure3.12: PhaseCArmandInnerDierenceCurrentsforPD{PWM Figure3.13: 3PhaseCirculatingCurrentsforPD{PWM 3.2VoltageBalancingAlgorithm AnotherimportantconcepttobeunderstoodforMMCisthebalancingofthe capacitorvoltages.ImportanceofthevoltagebalancinginMMCisaboutpreventing 27

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SMcapacitorvoltagevariationandasaresultofitphaseunitshavethesamevoltages. Otherwise,itcausescirculatingcurrents I circ;j thatowthroughthesixarmsand distortthesinusoidalarmcurrentwaveforms.Also,becauseofitthermsvalueof thearmcurrentsandtheconverterlossesincrease[25].InMMC,capacitorvoltage ofeachSMshouldbemonitoredandkeptequalforstableoperation.Toachieveit, propervoltagebalancingalgorithmneedstobeused.Inthisstudy,thealgorithm basedonthealgorithmstatedin[2]whichisarmspecicisused.InFigure3.14 owchartofthevoltagebalancingalgorithmisshown. Figure3.14: ReducedSwitchingFrequencyVoltageBalancingAlgorithm Accordingtothisapproach,numberofSMsinthesamearmthatneedstobe switchedonorosignalwhichisdictatedbyPWMblock,SMcapacitorvoltage measurements V c ; ijk andarmcurrent I ij directionsareusedasinputs.If I ij is positiveandextraswitches N> 0needstobeON",thereisnoswitching appliedtoSMswhicharecurrentlyinserted.Thisalgorithmsorts V c ; ijk andchooses SMswiththelowestvoltagesamongtheostateones.If N< 0whichmeanssome 28

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oftheSMswhicharealreadyinonstateneedtobebypassed,SMswiththehighest voltagesamongtheonstateonesarechosenandswitchedo.Incaseofnegativearm currentthisalgorithmworksinthereversewayintermsofchoosingSMsbasedon theirvoltagemeasurement.Additionally,bythetime N =0,sothismeansrecent statusfortheSMsiskept.Oneofthebiggestadvantageousofthisapproachisthatit reducestheaveragedeviceswitchingfrequencyandthetotalMMCswitchinglosses incomparisonwithconventionalmethod.Soitiscalledreducedswitchingfrequency RSFvoltagebalancingalgorithm. 3.3CirculatingCurrentSuppressionControllerCCSC In[33]itisstatedthatcirculatingcurrents I circ;j whichiscausedbyvoltageunbalancesbetweenthephaseunitsofMMCandcontainssecondharmoniccomponent distortsnotonlyarmcurrents,butalsoincreasetherippleonSMcapacitorvoltages. Itcanbeeliminatedbyaddingparallelcapacitorwhichisresonantlterbetweenthe midpointsoftheuppperandlowerarminductances[34]oneachphaseorusingan activecontroloverACvoltagereference[35].InthisstudyCCSCisbasedonthe approachgivenin[2,33]. Innerdierencecurrent I diff j equationwhichhastwopartsasmentionedinchapter 2isdenedas I diff j = I dc 3 + I circ ; j .10 andaccordingto[36] I circ;j arecomposedofnegativesequencecomponentwithtwice thefundamentalfrequency.So3phase I diff j canberewrittenas I diff a = I dc 3 + I circ ; a cos !t + I diff b = I dc 3 + I circ ; b cos !t + + 2 3 I diff c = I dc 3 + I circ ; c cos !t + )]TJ/F15 11.9552 Tf 13.15 8.088 Td [(2 3 .11 29

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! isthefundamentalfrequencyand istheinitialphaseangle.Innerunbalance V diff j voltagewhichisvoltageacrossthearminductanceandarmresistorisshown inthefollowing V di j = L dI di j dt + R arm I di j .12 andifParktransformationwhichisgivenintheappendixisapplied, dq components ofthreephase V diff j areobtainedasfollows V di d = L arm dI circ d dt + R arm I circ d )]TJ/F15 11.9552 Tf 11.956 0 Td [(2 !L arm I circ q V di q = L arm dI circ q dt + R arm I circ q +2 !L arm I circ d .13 Transferfunctionsofthe I circ;dq isshowninFigure3.15.Alsotodesigncontrol loop,twonewcontrolinputs u d ;u q canbeintroducedtoobtaintwodecoupledrst orderdierentialequationasitissuggestedin[4]. Figure3.15: TransferFunctionoftheCirculatingCurrentsindqReferenceFrame u d = V di d +2 !L arm I circ q = L arm dI circ d dt + R arm I circ d .14 30

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u q = V di q )]TJ/F15 11.9552 Tf 11.955 0 Td [(2 !L arm I circ d = L arm dI circ q dt + R arm I circ q .15 Finally,toeliminate I circ;dq twoidenticalPIcontrollerswithzeroreferencevaluesfor dq componentsseparatelyareappliedasitisshowninFigure3.16.Transferfunction ofthePIcontrolis PI circ;dq s = Kp circ;dq + Ki circ;dq s .16 V diff dq;ref equationsbecome V di d ; ref = )]TJ/F18 11.9552 Tf 11.955 0 Td [(I circ;d Kp + Ki s )]TJ/F15 11.9552 Tf 11.955 0 Td [(2 !L arm I circ q V di q ; ref = )]TJ/F18 11.9552 Tf 11.955 0 Td [(I circ;q Kp + Ki s +2 !L arm I circ d .17 Figure3.16: ClosedLoopd-qAxisCirculatingCurrentControllers Afterobtainingreferencevaluesforinnerunbalancevoltageindqreferenceframe, inverseParktransformationwhichisgiveninappendixisappliedtohaveitinthree phase.Eventually,Thesevaluesareusedtoattainreferencearmvoltagesasitis 31

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showninequations3.5and3.6.Overallcontrolsystemtoobtain V diff;j ref isshown inFigure3.17. Figure3.17: OverallCirculatingCurrentSuppressionController 32

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4.FaultDetectionandLocalization TherearevarioustypesoffaultsinMMCasitisgivenintable1.1.Because ofMMCstructuretherearemanypotentialfailurepointsbasedonsemiconductor devicessuchasIGBTanddiodesinSMsasitshowninFigure2.2anditissovital todetectandlocatethefaultaftertheoccurrencewithinashorttimeinthewayof systemreliability[14].Inthisstudy,onlyIGBTbasedopencircuitfaultisconsidered amongthem. 4.1FaultTypesandCharacteristics InSM,IGBTscanhavethreetypesoffault,whicharecalledType1,2and 3[15].Type1and2faultsarewhen S 1 and S 2 actasopencircuit,respectively. BothswitchesareopencircuitsimultaneouslyinType3fault.Type1faulthappens onlywhenconcernedarmcurrentisnegative I ij < 0andgatesignalof S 1 S ijk is1.Duetothefactthatupperswitchisopencircuit,currentisforcedtocirculate throughcomplementaryswitchdiode D 2 .Thus,SMisbypassedand V sm becomes 0insteadof V c .Type2occurswhenarmcurrentispositive I ij > 0andgatesignal for S 2 S ijk is1.Inthiscasearmcurrentowsthrough D 1 andcharges C sm .Unlike theexpected V sm is0, V sm equalsto V c .OthersituationsSMrunsnormally.What aboutType3isitshowsbothcharacteristicsoftype1and2faults.Faultscenarios aredepictedinFigure4.1respectively.Inthispaper,toillustratethefaultdetection andlocalizationmethodonlysingleType1faultisconsidered. Figure4.1: FaultTypes 33

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Table4.1:FailureCharacteristicsofType1 HealthyOperationType1Fault I arm Gatesignalfor S 1 Directionof I arm V sm Directionof I arm V sm Positive 1 D 1 and C sm V C D 1 and C sm V C 0 S 2 0 S 2 0 Negative 1 C sm and S 1 V C D 2 0 0 D 2 0 D 2 0 Table4.2:FailureCharacteristicsofType2 HealthyOperationType2Fault I arm Gatesignalfor S 1 Directionof I arm V sm Directionof I arm V sm Positive 1 D 1 and C sm V C D 1 and C sm V C 0 S 2 0 D 1 and C sm V C Negative 1 C sm and S 1 V C C sm and S 1 V C 0 D 2 0 D 2 0 Table4.3:FailureCharacteristicsofType3 HealthyOperationType3Fault I arm Gatesignalfor S 1 Directionof I arm V sm Directionof I arm V sm Positive 1 D 1 and C sm V C D 1 and C sm V C 0 S 2 0 D 1 and C sm V C Negative 1 C sm and S 1 V C D 2 0 0 D 2 0 D 2 0 Fromthetables4.1,4.2and4.3thatshowcharacteristicsofSMsinMMCsystem itcanbededucedthatunderalltypesofopencircuitfaultcircumstancesfaultySM capacitorvoltages V sm becomehigherthanthehealthyones. 34

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4.2ProposedFaultDetectionMethod AssoonasType1faulthappensinoneoftheSMsinanyarmoftheMMC, V diff;j betweenthehealthyphaseunitsandfaultyonegetslarger.WhenPWMblock dictatesallSMsinthethesamearmtobeswitchedonafterthefaultoccurrence healthycapacitorvoltagesincreasetorecoverfaultymodule.Inthisperiod,arm currentnegativepolarityissuppressedbecauseofcirculatingcurrentboostedbyfault freephaseunits. Innormaloperationeachcapacitorvoltageis V c = V dc n .1 whichisalreadyshowninequation2.1.Hereby,incaseoffaulthealthySMcapacitor voltagesareexpectedtoincreasetoreachthevoltagewhichcanbeshownasfollows V c threshold = V dc n )]TJ/F18 11.9552 Tf 11.955 0 Td [(n faulty .2 TodetectthefaultinanyphaseunitoftheMMCsystemthisvoltagecanbeused asthreshold V threshold .IfhealthySM V C reachorexceedthis V threshold foracertain periodoftime t min ,sothatarmcanbelabeledasfaultyanditcanbeproceededto locatethefaultymoduleinthearm.Simultaneously,itcanbeextractedfromhere thatifreallifeapplicationsinwhichhundredsofSMsareuseddependsonthevolume oftheapplicationareconsidered,bybenettingequation4.2thresholdvoltagefor faultdetectionbecomesless.Thismightaectthefaultdetectionperiodfavourably. FlowchartofthefaultdetectionprocessisshowninFigure4.2. 4.3ProposedFaultLocalizationMethod Tolocatethefaultymodule,stateobservertoestimatecapacitorvoltagescanbe usedintermsofcomparisonbetweenthedirectmeasurementofitandobservation. SMcapacitorvoltageequationisdenedas 35

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Figure4.2: FaultDetectionFlowchart dV c ; ijk dt = 1 C S ijk I ij .3 Asitcanbeseenfromtheequation4.3itisrstorderdierentialequationandcan beconsideredasstateequationforthecase. V c ; ijk isconsideredasstateand I ij is input.FlowchartofthefaultlocalizationisdemonstratedinFigure4.3. 4.3.1DesignofStateObserver TheStateobservershasbeencommonlyusedinindustriesasaneectivemethod toprovideestimationofarealsystem[37{39].Tobuilduptheobservertherstand mostessentialruleischeckingtheobservabilityofsystem[40].Butinourcasethis isnotnecessarybecauseofhavingtherstordersystem.Ifweconsidertheplant denedby x = Ax + Bu y = Cx .4 observerstateandoutputequationwillbeasfollows; 36

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Figure4.3: FaultLocalizationFlowchart ^ x = A ^ x + Bu + K e y )]TJ/F15 11.9552 Tf 12.747 0 Td [(^ y ^ y = C ^ x .5 K e isobservergainwhichiscorrectiontermbetweensystemoutputandestimated outputasitisshowninequation4.5.Itshouldbechosenproperlyintermsof systemperformancetomakeestimatedstate^ x convergetosystemstatevariablex regardlessofit'sinitialvalue^ x .In[40]itisstatedthatdynamicbehaviourofthe errorvectorwhichisobtainedbysubtractingsystemandestimatedstateequations fromeachotherdeterminedbytheeigenvaluesofmatrice A )]TJ/F18 11.9552 Tf 11.925 0 Td [(K e C asitisshownin equation. e = A )]TJ/F18 11.9552 Tf 11.955 0 Td [(K e C e .6 Ifitisstablematriceerrorvectorwillconvergetozeroforanyinitialerrorvalue e .Ifthesystemisloworderwhichmeanssystemordercanbethirdorderat most,directsubstitutionmethodcanbeappliedtondobservergain.Todothat, 37

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thedesiredcharacteristicpolynomialwhichisextractedfromequation4.5isusedand shownbelow. j sI )]TJ/F18 11.9552 Tf 11.955 0 Td [(A + K e C j = s )]TJ/F18 11.9552 Tf 11.955 0 Td [( 1 .7 1 isthedesiredobserverpolelocationwhichiswithinthelefthalfof j! axisins domain.IfSMcapacitorvoltageequationequation4.3whichisstateequationin hereisconsidered,itisseenthatAwhichisstatematriceis0andCwhichisoutput matriceis1.Asaresultofitfromtheequation4.7itisdeducedthat K e > 0isthe conditionforthestabilityasitisshownbelowinequation4.8.Whatmakesdierence inhereisdierentgainvalueseectingfaultymodulelocalizationtimewhenopen circuitfaultisgenerated. j s + K e j = s )]TJ/F18 11.9552 Tf 11.955 0 Td [( 1 .8 38

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5.DesignGuidelineandSimulation 5.1CircuitParameters TorunMMCinverterwithRLloadinopenloopcondition,circuitparameters aretakenfromthe[15].Theyareshownintable5.1. Table5.1:SimulationParameters V dc n sm C sm L arm R load L load f carrier f load modulationindex V mF mH ohm mH Hz Hz V j ref 3600 4 3.5 3 10 10 1650 50 0.7 5.2CirculatingCurrentPIControllerGainSelection InbothcirculatingcurrentcontrolloopsshowninFigure3.16,KpandKiare derivedasfollows[4]: Kp = L arm = i Ki = R arm = i .1 where i isthetimeconstantofthecirculatingcurrentcontrolloop. i isadesign choice,anditisgenerallyselectedintherangeof0.5-5ms[4].Inourstudyitis chosen0.2mstohavefasterresponse.SoKpwhichisusedhereequals15andKi becomes20. 5.3SimulationResults Mainparametertoimplementfaultlocalizationalgorithmisobservergain K e as mentionedinthepreviouschapter.Toshowhowitaectsthedurationtolocatefaulty moduletwodierentgainsareusedhere.Necessityforobserverstabilityisshownin equation4.8.If K e ischosenhighenough,itisexpectedtoseethatestimationfollows measurementaftergeneratingthefaultandwhencapacitorvoltagesinthesamearm 39

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reach V threshold itstartstodivergeslightly.So,ittakesmuchtimetoexceedV between V c;ijk and V c;ijk est tolocatefaultySM.Tosamplethisscenarioopencircuit faultin S 1 ofrstSMintheupperarmofphaseCisgeneratedat0.8sec.Also, CCSCisactivatedat0.3sectoshowhowtominimizeit. 5.3.1 K e =50 InFigure5.1itisseenthatuntilthefaulthappensbothupper{lowerarmcapacitorvoltagesareslightlyvaryingaround900Vwhichis V dc = 4anditprovesthat balancingalgorithmisabletoequalizetheSMcapacitorvoltages. Figure5.1: PhaseCUpper{LowerArmCapacitorVoltages Figure5.2showsthecirculatingcurrentsin3phaseofMMCsystem.Itisobserved fromthegurethatcontrollersuppressesthecirculatingcurrentswhenitisactivated at0.3sec.Capacitorvoltagevariationbecomessmallerbymeansofit.Assoonas faulthappensbecauseof V diffj itgetshigher. Figures5.3,5.4,5.5and5.6depictthecomparisonbetweentheestimationand measurementofphaseCupperarmcapacitorvoltagesrespectively.Fromthegures itisdeducedthatobservedstatesreachmeasurementfromitsinitialvaluewhichis500 Vinhereandincaseoffaultfaultymodulecapacitorvoltageestimationdivergesfrom 40

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Figure5.2: 3PhaseCirculatingCurrents measurementbecauseoftheerrorafterreaching V threshold asshowninequation4.2. InFigure5.3,rstSMintheupperarmofphaseCiscomparedwithitsestimation. Figure5.3: PhaseC V uc 1 and V uc 1 est Unliketheothersthisisslightlydivergingfrommeasurementanditshowsus thisisfaultyone,butforlocalizationdierencevoltagewhichisspeciedas100V 41

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isn'tenough.Soweunderstandthatbecauseofhighobservationgainitisrecovering theerrorwhichiscausedbyopencircuitfaultinthemodule.Restofthegures estimationfollowsthemeasurementforhealthyonesperfectly. Figure5.4: PhaseC V uc 2 and V uc 2 est Figure5.5: PhaseC V uc 3 and V uc 3 est ItisunderstoodfromtheFigure5.7thatevenallSMcapacitorvoltagesexceed V threshold forfaultdetectionbecauseofhighgainselectionobservedstatedoesn'tshow 42

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Figure5.6: PhaseC V uc 4 and V uc 4 est Figure5.7: FaultStatusofSMs divergentbehaviourtolocatethefaultwithinreasonabletime.Thusfaultstatusof allSMsstays0. 5.3.2 K e =0.1 Ifobservergainischosensmallenoughwhichstillneedstobegreaterthanzero, itisseenthatthedivergencebetweenmeasurementandestimationofstatebecomes 43

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moreclearandithelpsustodetectandaddressthefaultfaster.Relatedgures whichare5.8and5.9areshownbelow. Figure5.8: PhaseC V uc 1 and V uc 1 est for K e =0.1 Figure5.9: FaultStatusofSMsfor K e =0.1 44

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5.4Discussion IftheFigures5.3and5.8areconsidered,itisdetectedthatobservergainselection playsanimportantroletolocatethefaultymodulewithinareasonabletime.For smallobservergainerrorbetweenthemeasurementandestimationforeacherrorstep increments.Alsoitisselectivedesigncriteriathatobserverresponseforsmallergain issluggish. AsitisseenfromtheFigure5.9faultislocatedwithinapproximately0.4sec whichcanbeconsideredhighforrealsystemapplications,butasitismentionedin chapter4faultdetectionpart,fortherealMMCsystemswhichcontainhundreds ofMMCsthisfaultdetectionlevel V threshold canbekeptwithinthesmallrange. Forinstance,inthisstudyif10SMsperarmwereusedinstead4SMsatthesame switchingfrequency,faultdetectionvoltagelevelwhichisextractedfromtheequation 4.2andgivenbelowwouldbe400VforeachSMinsteadof1200V.Thus,thatmeans ittakessmallertimetodetectandlocateit. V c threshold = V dc n )]TJ/F18 11.9552 Tf 11.955 0 Td [(n faulty = 3600 10 )]TJ/F15 11.9552 Tf 11.955 0 Td [(1 =400 V 45

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6.Conclusion Inthisthesis,"levelthreephaseMMCinverterwithRLloadisdesignedto proposethefaultdetectionandlocalizationalgorithmsbasedonSMcapacitorvoltage measurementandestimation.Thevariouscomponentsinvolvedintherealizationof powercircuitaredescribedandthecontrolapproachisexplainedinparts.Inaddition, thedesignguidelineofthesystemparametersandtuningmethodsforPIcontrollers usedincirculatingcurrentsuppressioncontrollerareexpressed.Theproposedsystem isimplementedviadetailedMatlab/Simulinkcomputersimulations. ItisshownintheMMCcontrolpartthatemployedcapacitorvoltagebalancing algorithmwhichissimilartoreducedswitchingfrequencyapproachgiveninreferencepapersoperatesasdesiredbyequalizingthearmcapacitorvoltages.PS{PWM modulationwhichispreferredmulti{carrierPWMtechniqueinthisstudyprovides lessoscillatorycurrentwaveformsthanPD{PWMmethodincomparison.Additionally,implementedcirculatingcurrentcontrollerminimizescirculatingcurrentsin threephasebynarrowingvoltagevariationofcapacitorvoltagesandprovidesinner unbalancevoltagereferencetobeusedinarmmodulatingsignalreferencecalculation. Todetectthefaultandlocatethefaultymodulestateobserverapproachbased oncomparisonbetweenSMcapacitorvoltagemeasurementandestimationisused. Designofobserverandhowobservergain K e selectioneectslocalizationperiodas acriticalpointisexplained.Moreover,bycomparingthesimulationresultsfortwo dierentgainvaluesitisveried. Ascontributionapartfromtheothermethodswhichisalreadyproposedinthe papers,dierentapproachissuggestedforopencircuitfaultdetectionandlocalization inMMCsystem. 46

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7.FutureWork Thepossiblefutureworkscanbelistedasfollows: Studyontheobservergain K e selectionwhichmattersforfaultdetectionand localizationperiodincaseofhealthyandfaultyconditions. Theobserverapproachforfaultdetectionandlocalizationcanbeappliedfor theothertypesoffaultsinSMorconverterlevel. 47

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[12]GumTaeSon,Hee-JinLee,TaeSikNam,Yong-HoChung,Uk-HwaLee,SeungTaekBaek,KyeonHur,andJung-WookPark.Designandcontrolofamodular multilevelhvdcconverterwithredundantpowermodulesfornoninterruptible energytransfer. PowerDelivery,IEEETransactionson ,27:1611{1619,July 2012. [13]HuiLiu,PohChiangLoh,andF.Blaabjerg.Reviewoffaultdiagnosisand fault-tolerantcontrolformodularmultilevelconverterofhvdc.In Industrial ElectronicsSociety,IECON2013-39thAnnualConferenceoftheIEEE ,pages 1242{1247,Nov2013. [14]M.Shahbazi,P.Poure,S.Saadate,andM.R.Zolghadri.Fpga-basedfastdetectionwithreducedsensorcountforafault-tolerantthree-phaseconverter. IndustrialInformatics,IEEETransactionson ,9:1343{1350,Aug2013. [15]FujinDeng,ZheChen,M.R.Khan,andRongwuZhu.Faultdetectionand localizationmethodformodularmultilevelconverters. PowerElectronics,IEEE Transactionson ,30:2721{2732,May2015. [16]S.Shao,P.W.Wheeler,J.C.Clare,andA.J.Watson.Open-circuitfaultdetection andisolationformodularmultilevelconverterbasedonslidingmodeobserver. In PowerElectronicsandApplicationsEPE,201315thEuropeanConference on ,pages1{9,Sept2013. [17]H.Salimian,H.Iman-Eini,andS.Farhangi.Open-circuitfaultdetectionandlocalizationinmodularmultilevelconverter.In PowerElectronics,DrivesSystems TechnologiesConferencePEDSTC,20156th ,pages383{388,Feb2015. [18]V.Najmi,H.Nademi,andR.Burgos.Anadaptivebacksteppingobserverfor modularmultilevelconverter.In EnergyConversionCongressandExposition ECCE,2014IEEE ,pages2115{2120,Sept2014. [19]HuiLiu,KeMa,PohChiangLoh,andF.Blaabjerg.Designofstateobserverfor modularmultilevelconverter.In PowerElectronicsforDistributedGeneration SystemsPEDG,2015IEEE6thInternationalSymposiumon ,pages1{6,June 2015. [20]M.RajanandR.Seyezhai.ComparativeStudyofMulticarrierPWMTechniques foraModularMultilevelInverter. InternationalJournalofEngineeringand Technology ,2013. [21]B.Gemmell,J.Dorn,D.Retzmann,andD.Soerangr.Prospectsofmultilevel vsctechnologiesforpowertransmission.In TransmissionandDistributionConferenceandExposition ,pages1{16,April2008. [22]M.Davies,M.Dommaschk,J.Dorn,J.Lang,D.Retzmann,andD.Soerangr. HVDCPlus{BasicsandPrincipleofOperation. SiemensEnergySector ,3,2008. 49

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AppendixA.ParkTransformation Parktransformationtheoryisusedtotransformthree-phaseabcreferenceframe quantitiestothedqreferenceframequantities.Inthistransformtheory,itisassumed thatthedqreferenceframeisrotatingatsynchronousspeedwithrespecttotheabc referenceframewithaphaseangle .ThereferenceframesareshowninFigure A.1.Also,Parktransformationcanbereversed,whichmeansdqquantitiescanbe transformbacktoabcquantities. FigureA.1: Thestationaryabcreferenceframeandtherotatingdqreferenceframe Thedqquantitiesrelatetotheabccounterpartsaccordingto X dq = T dq abc X abc ; X abc = T abc dq X dq ; where T dq abc representstheParktransformationmatrix, T dq abc = 2 3 2 6 4 cos cos )]TJ/F15 11.9552 Tf 13.151 8.088 Td [(2 3 cos + 2 3 )]TJ/F15 11.9552 Tf 11.291 0 Td [(sin )]TJ/F15 11.9552 Tf 11.291 0 Td [(sin )]TJ/F15 11.9552 Tf 13.151 8.088 Td [(2 3 )]TJ/F15 11.9552 Tf 11.291 0 Td [(sin + 2 3 3 7 5 52

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and T abc dq standsfortheinverseParktransformationmatrix T abc dq = 2 6 6 6 6 4 cos )]TJ/F15 11.9552 Tf 11.291 0 Td [(sin cos )]TJ/F15 11.9552 Tf 13.151 8.088 Td [(2 3 )]TJ/F15 11.9552 Tf 11.291 0 Td [(sin )]TJ/F15 11.9552 Tf 13.151 8.088 Td [(2 3 cos )]TJ/F15 11.9552 Tf 13.151 8.088 Td [(4 3 )]TJ/F15 11.9552 Tf 11.291 0 Td [(sin )]TJ/F15 11.9552 Tf 13.151 8.088 Td [(4 3 3 7 7 7 7 5 : 53