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Parallel processing digital correlator

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Title:
Parallel processing digital correlator
Creator:
Rahbar, Kianoush
Publication Date:
Language:
English
Physical Description:
vii, 76 leaves : illustrations (including 4 folded) ; 29 cm

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Subjects / Keywords:
Correlators ( lcsh )
Correlators ( fast )
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bibliography ( marcgt )
theses ( marcgt )
non-fiction ( marcgt )

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Bibliography:
Includes bibliographical references (leaf 31).
General Note:
Submitted in partial fulfillment of the requirements for the degree, Master of Science, Department of Electrical Engineering ; Department of Computer Science.
Statement of Responsibility:
by Kianoush Rahbar.

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Source Institution:
University of Colorado Denver
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Auraria Library
Rights Management:
All applicable rights reserved by the source institution and holding location.
Resource Identifier:
21104500 ( OCLC )
ocm21104500
Classification:
LD1190.E54 1989m .R33 ( lcc )

Full Text
PARALLEL PROCESSING DIGITAL CORRELATOR
by
Kianoush Rahbar
B.S., University of Colorado at Denver, 1984
A thesis submitted to the
Faculty of the Graduate School of the
University of Colorado in partial fulfillment
of the requirements for the degree of
Master of Science
Department of Electrical Engineering and Computer Science
1989


This thesis for the Master of Science degree by
Kianoush Rahbar
has been approved for the
Department of
Electrical Engineering and Computer Science
by
Joe Thomas

Date
)) g?


Ill
Rahbar, Kianoush (M.S., Electrical Engineering)
Parallel Processing Digital Correlator
Thesis directed by Professor Douglas A. Ross
In this report the Time Average Estimate of a Correlator
is discussed. Design techniques to build a digital
correlator using multiplier/accumulators are presented
and theory of operation is described. The construnction
methods utilized to build a prototype unit are
explained. Hardware and software tests used to test and
debug the correlator are described. Problems encountered
and solutions provided to resolve such problems are
discussed. A list of all the equipments used to perform
these tests is given. Finally to verify the operation,
results collected from the digital correlator are
compared to the desired values based on the the
mathematical model.
The form and content of this abstract are approved. I
recommend it's publication.
Signed
Douglas A. Ross


IV
CONTENTS
CHAPTER
I. Parallel Processing Digital Correlator.... 1
Time Average Estimate................... 1
An Overview............................. 1
II. DESIGN AND IMPLEMENTATION................. 4
Overview................................ 4
Computer.............................. 8
MAC Board............................. 9
Address Decoder........................ 12
Timing Logic........................... 15
Software............................... 18
III. CONSTRUCTION AND TESTING................... 19
Construction............................. 19
Testing.................................. 20
Timing Logic.......................... 2 0
Address Decoder........................ 21
MAC Board.............................. 22
System Test............................ 24
Software............................... 24
Verification of Operation................ 24
IV. DISCUSSION AND CONCLUSION.................. 27
REFERENCES
31


V
APPENDIX
A. Schematic Diagrams and Program Listing.. 32
B. Specification Sheets and Manuals......... 37
C. Test Results............................. 76


VI
TABLES
Table
1. Parts List................................... 7
2. User RAM Memory Space Used to Memory Map the
Hardware..................................... 13
3. Address Lines Decoded for
Specific Purposes
18


VII
FIGURES
Figure
1. Functional Block Diagram of the Parallel
Processing Digital Correlator................ 6
2. Voltage Reference Supply Circuit Diagram..... 10
3. Status Register Bit Map...................... 12
4. Typical Timing Diagram for Timing Logic Based
on Diagram No. 3............................. 16
5. Block Diagram of the Test Set Up to Debug the
Hardware..................................... 23
6. Block Diagram of the Test Set Up to Verify
Operation ................................... 2 6


CHAPTER I
PARALLEL PROCESSING DIGITAL CORRELATOR
Time Average Estimate
The Parallel Process Digital Correlator
estimates the auto or cross correlation of one or two
analog input signals by a sum of products illustrated in
equation (1).
1 M-l
C (n) = ---x(m)y(m-n) (1)
M m=0
The input signals are quantized and N correla-
tion coefficients are calculated using multiplier/
accumulators (MACs). After the calculation is completed
the data is transferred and saved into a computer to be
displayed later.
An Overview
The Parallel Process Digital Correlator hardware
consists of four major functions. These four functions
include:


2
o Computer
o Analog to Digital conversion and
coefficient calculation
o Computer Interface
o Timing Logic Circuitry
As mentioned before the computer is responsible
for MAC'S reset and collection of the results.
One single board designated as the MAC Board
holds the analog to digital conversion circuitry plus 32
MACs to calculate 32 coefficients and the registers
which act as the delay units.
The Address Decoder Board is the interfacing
media between the computer and the outside devices.
The Timing Logic Circuitry provides the control
signals that are needed in order to calculate the
coefficients.
The software part of the design is mainly
responsible for issuing the control signals to reset the
MACs and to collect the data after the coefficients are
calculated.
The operator starts the process by executing the
software. All the MACs get reset then the Timing Logic
takes over and starts the calculation and signals the
computer of completion. The computer collects the data
from MACs, one at a time, saves them and prints and/or
displays them.


It should be noted that the quantization
sampling rate is fixed and therefore the incoming analog
signals must be band limited to prevent aliasing.
Design details and characteristics of hardware
and software are discussed in chapter two.
Chapter three discusses the construction methods
and the testing involved to debug the software and
hardware.
Next phase of this project along with some
recommendations to improve the existing design and
discussion of sample results are all presented as
chapter four of this report.


CHAPTER II
DESIGN AND IMPLEMENTATION
Overview
The Parallel Processing Digital Correlator has
two analog inputs. It performs quantization with 8 bit
resolution, calculates the coefficients using
multiplier/accumulators and transfers the results to a
computer. A functional block diagram of the Parallel
Processing Digital Correlator is shown in figure 1. All
the devices connected to the computer are memory mapped
in the user's RAM area not used by the computer.The
computer resets all the MACs through the Address Decoder
and signals the Timing Logic to start the correlation
process. The process of calculation is set to be 2 xTq
sec (Tq is the time of one master clock period) using
counters on the Timing Logic board. Afterwards the
Timing Logic activates the count over line (CNT OVER) to
inform the computer of completion and then the computer
takes over and reads in all the coefficients.
The correlation process can be divided into
three general cycles:


1. Reset Cycle
2. Calculation Cycle (parallel process)
3. Data Collection Cycle (serial process)
During the reset cycle computer resets all the
accumulator by writing zeroes to all the registers
inside the MACs. The calculation cycle is when the
computer is isolated from the MAC board and the Timing
Logic is generating all the control signals for the MACs
to do the required calculations, and finally the data
collection cycle is when the computer takes over the MAC
board and collects the coefficients. Figure 1
illustrates the overall block diagram of the system.
Table 1 lists all the parts needed for this project.
The technical characteristics and function of
each hardware block and the software are discussed
separately in details in the following paragraphs.


6
Figure 1-Functional Block Diagram of the Parallel Processing Digital Correlator


Part No. Technology Description Quantity
MAC 45CM16 CMOS Single Bus MAC 32
Board 74374 TTL 8 bit Shift Register 66
10319 ECL High Speed 8 bit A/D Conv 2
7404 TTL Hex Inverter 1
Address 7486 TTL Quadruple 2-input XOR Gate 4
Decoder 7432 TTL Quadruple 2-input OR Gate 8
7408 TTL Quadruple 2-input AND Gate 2
7404 TTL Hex Inverter 1
74154 TTL 4-line to 16-line Decoder 2
74244 TTL Octal Buffers and line Drivers 7
with 3-state outputs
74245 TTL Octal Bus Transceivers with 2
3-state outputs
74138 TTL 3-line to 8-line Decoder 1
74374 TTL 8 bit Shift Register 1
Timing 74161 TTL Asynchronous 4-bit counter 4
Logic 7474 TTL Dual D-type Flip Flop 1
7411 TTL Triple 3-input Pos. AND Gate 1
7408 TTL Quadruple 2-input AND Gate 2
7404 TTL Hex Inverter 2
7400 TTL Quadruple 2-input Pos. NAND Gate 1
7432 TTL Quadruple 2-input OR Gate 2
74244 TTL Octal Buffers and Line drivers 5
with 3-state outputs
Table-1 Parts List


8
1. Computer
The computer used to run the necessary software
in order to reset the MACs and to collect, save and
display the results is an IBM PC/AT.
The IBM PC/AT is an 80286 processor based
computer with 16 bit data bus (DO to D15) and 20 bit
address bus (AO to A19).
The software generates one address at a time on
the address bus which is decoded by the address decoder
to one predesignated select line (i.e. Chip Select) that
controls a MAC or the status register and based on the
cycle of the process either writes or reads data. Also
the tri-state buffer that carries the calculation cycle
completion flag (CNT OVER) from the Timing Logic is
controlled by the Address Decoder. IBM uses AO to
generate other signals beside SAO (the first address
line). To isolate any kind of intermittent problem only
even addresses are used so that AO can be eliminated and
in result the decoder decodes address lines A1 to A19.
The control lines used are MEMR and MEMW to
control the direction of data and BALE and AEN to check
the validity of the address on the bus. The description
and purpose of each control signal is copied from the
IBM technical manual and are included in appendix B.


9
2. MAC Board
The MAC Board quantizes the input signals and
includes the MACs to do the required arithmetic to
calculate the coefficients. The major components on
this board are two analog to digital converters (A/D,
ECL technology), 32 multiplier/accumulators (CMOS
technology) in parallel and 66 eight bit registers
(TTL technology). The A/Ds are to quantize two analog
inputs with 8 bit resolution with a maximum sampling
rate of 2.27 Mhz. The MACs calculate 32 correlation
coefficients and the registers are used as one clock
cycle delay units on input (x). Also two registers are
used as buffers on input (y). The clock rate on all the
registers is the same as the A/D's sampling rate. The
A/Ds' reference voltages are set to:
Voltage Reference Top, VRT=+1 volt
Voltage Reference Bottom, VRB=-1 volt
Voltage Reference Middle, VRM=0 volt
Separate power supplies are used to provide
reference voltages and the outputs were regulated for
accuracy purposes. Figure 2 shows the schematic for the
reference voltage supply designs. Also diagram No. 1 in
appendix A shows the schematic drawing for the MAC
Board.


10 uF
Figure 2-Voltage Reference Supply Circuit Diagram


11
The7th bit of the 8 bit output of the A/Ds is used as
sign extension to create compatibility with MAC'S 2's
complement arithmetic. It should be noted here that at
this point only stage one of the 32 MACs is complete and
working. The A/D's and MAC'S spec sheets are included in
appendix B.


3. Address Decoder
Since every device that interfaces with the
computer is memory mapped the Address Decoder is needed
to convert 19 address lines (As explained before only
even addresses are used, therefore only A1 to A19 are
decoded) along with some control lines (MEMR, MEMW, BALE
and AEN) to a single select line in order to control the
MAC Board, the Timing Logic and/or the status register.
Also included in the Address Decoder board are the
bidirectional data buffers to transfer data back and
forth and the status register to issue control signals.
The status register provides signals such as WE (Write
Enable) to control the direction of data to the MACs,
CLR (Clear) to reset the counters on the Timing Logic
board and Auto/Cross. The Auto/Cross which determines
whether the correlation is auto correlation (the input
signal correlates with itself) or cross correlation.
Figure 3 illustrates the bit map for the status
register.
Bit No. 7 6 5 4 3 2 1 0
CLR Auto/ ENP WE X X X X
Cross
o CLR = Counter Clear/Active Low
o Auto/Cross = Hi/Low
o ENP = Counter Enable/Active High
o WE = Active Low
o X = Don't Care
Figure 3 Status Register Bit Map


Table 2 provides all the control signals on the
MAC Board and their corresponding addresses.
Address fHex)____________Reserved For
SEG = 9000
to
03FF CSO TO CS31 (MACO TO MAC31)
_________________________Status Register Clocks
0400 Status Register/CLR
0400 Status Register/WE
0400 Status Register/Auto/Cross
0406 CNT OVER Tri State Control
Line
Table 2 User RAM Memory Space used to Memory Map the
Hardware
Address lines A4 to A19 are decoded to provide
the Active Low Select which controls one of the select
lines of the 4 by 16 multiplexers (154s) or to provide
Active High Select which controls one of the select
lines of the 3 by 8 multiplexer (138). The other select
lines of the 138 are controlled by the MEMW and MEMR of
the computer. The 154 multiplexers provide the CS
signals for the MACs during the reset and data
collection cycles and the 138 provides the status
register's clock. The Active Low Select also controls
the output of the bidirectionl data buffers (245s) and
their directions are determined by the MEMW and MEMR.
The addresses are first decoded to select the 138 in
order to issue a WE=0 so that the MACs can be written
to. Next the decoder activates the Active Low Select
which in turn activates the CS signals to enable one MAC
at a time to reset the accumulator and to write zero to


14
all the registers within each MAC. Since each MAC has
four address lines 16 memory spaces are dedicated to
each MAC and, therefore, each CS stays active for
sixteen consecutive even addresses. Once all the MACs
are reset the decoder turns the control of the MAC Board
to the Timing Logic by deactivating the Active Low
Select and issuing clear (CLR) and enable (ENP) to the
counters through the status register. After the
calculation cycle is over the computer issues a WE=1
through the status register so that it can read the
results from the MACs. Diagrams No. 2 in appendix A show
the schematic for the Address Decoder.


4. Timing Logic
The Timing Logic provides the MAC Board with all
the control signals during the calculation cycle. These
signals include the MAC'S addresses AO to A4, the chip
select (CS) the A/D clock (A/D) which is the same as
the register's clock, and the registers output controls
(0C1 & 0C2).
A typical timing diagram of the calculation
cycle is shown in figure 4. Assuming a minimum write
time of 220 nsec a total of 440 nsec is required to
multiply x input by y input and add it to the previous
sum of products which results to a maximum real time
rate of 2.27 Mhz which means that according to the
nyquest theory the frequency of the input signals can
not exceed 1.135 Mhz or half of the sampling rate.
Diagram No. 3 in appendix A shows the schematic for the
Timing Logic.
All the control signals on this board are
derivatives of a master clock (MC) which has a maximum
rate of 8 Mhz. The three counters are to control the
length of the calculation cycle to a maximum time of
212xTq sec (Tq is the time of one Master Clock period)
in order to prevent the MACs from overflow since there
are no overflow provisions built into them.
Once the computer is done resetting all the MACs
in the reset cycle it deactivates the Active Low Select
by changing the address to select the multiplexer (138)


1
VO
MC
TO
AO-A3
1001
NEW DATA TO Y
0110
NEW DATA TO X
\
A/D
CS
Latch Addr
Latch Data
Figure 4-Typical Timing Diagram For Timing Logic Based on Diagram No. 3


which controls the status register's clock. First a CLR
signal is issued to reset the three counters. This
causes the CNT OVER to go low and therefor the Timing
Logic takes control of the MAC Board and at the same
time the count starts. During the count the computer
monitors the data line DO by decoding one address (refer
to Table 2) that controls the tri-state buffer control
line. The DO line carries the CNT OVER signal from the
Timing Logic. A high on this line means that the
calculation is done and the computer can take over the
MAC Board to collect the coefficients.


5. Software
The software is designed to control the sequence
of the three cycles (Reset, Calculation and Collection).
Also the correct addresses to the MACs during the reset
and collection cycles is provided by the software which
is coded in basic. The predesignated addresses are
generated on the address bus which are decoded in the
format shown in table 3.
Process Cycle Address Lines
Reset A1 to A4
A5 to A8
A9 to A19
Calculation A1 to A3
Purpose
To provide the MACs
addresses (AO to A4)
Select Lines A to
D of the 74154 MUXs
To activate the -
Active Low Select
and enable one MUX
(154s) at a time
Select Lines A to
C of the 74138 MUXs
Collection
A4 to A19 To activate the
Active High Select
of the 138s to clock
the Status Register
or to provide the
CNT OVER flag
Same as Reset Same as Reset
Table 3-Address Lines Decoded for Specific Purposes


CHAPTER III
CONSTRUCTION AND TESTING
The construction methods utilized to build the
hardware and the testing schemes are discussed in this
chapter.
Construction
As indicated in chapter one the digital
correlator is divided into 4 major boards, the Computer,
the Address Decoder, the Timing Logic and the MAC Board.
Wire wrap techniques were used to construct all the
boards except the computer. All the IC pins were
numbered by wire wrap IDs to reduce the possibility of
wire connection errors. Strip headers were used to
connect the boards with ribbon cables. An IBM plug-in
expansion board was used to connect the Address decoder
to the computer via ribbon cable. The boards used for
the Timing Logic and the Address Decoder are regular
epoxy wire wrap boards. The MAC Board, however, has an
isolated ground layer to reduce excessive noise caused
by the large number of ICs and high frequency signals.
The MAC Board was provided with +/-5 VDC power supply


and the Address Decoder and the Timing Logic were
provided with a separate +5 VDC supply. By-pass
capacitors were installed on most ICs on every board.
20
Testing
Each board except the computer was tested
separately before it was integrated into the correlator.
The details of each test and the problems encountered
are discussed in details in the following paragraphs.
The equipments used to do these tests are listed below:
Function Generator HP 8111A
DC Power Supply HP 6236B
Logic Analyzer Nicolet NPC-764
Oscilloscope Tecktronix 2465
Timing Logic
The Timing Logic is provided with a +5 volt peak
to peak 8 Mhz square wave as the master clock.
The Timing Logic was tested for glitches caused by
propagation delays and overlapping of two or more
signals at the falling or rising edge. The minimum
address valid time was measured at 8 Mhz master clock
speed. Also the timing relation of the control signals
generated by this board was checked against the design
spec defined by the timing diagram shown in figure 4.
The only problem encountered with the Timing
Logic was the timing relation between the A/D and the CS


signal. The MAC latches the data at the rising edge of
the CS and the data is provided when the A/D goes from
logic 0 to logic 1. Originally the A/D and CS rose at
the same time and, therefore, the MAC did not have
enough time to latch the data. Inverting the A/D signal
resolved this problem. All the other outputs of the
Timing Logic were accurate and no glitches were
observed.
The block diagram in figure 5 illustrates the
test set up.
Address Decoder
The Address Decoder is connected to the computer
via the expansion board. A simple software routine was
written to generate one single address with a constant
frequency. Data was transferred back and forth to and
from the designated memory location. When the computer
was running the test program, the CS signal that the
address was mapped to plus the Active Low Select, the
Active High Select, the data lines the status register
outputs and the data buffers direction lines were
monitored for proper timing and operation.
The problem observed when performing this test
was the interface between the computer and the decoder.
Every time the decoder was plugged into the computer it
interrupted the operating system and caused the computer
to halt. After long hours of test and examination
several causes were discovered which among them all the


excessive noise caused by the XOR gates found to be the
major contributor. Bi pass capacitors were installed on
every XOR gate to reduce the noise. Eventhough the bi
pass caps helped to eliminate some of the noise it did
not solve the problem completely. Finally it was decided
to remove all the XORs from the design which meant
giving up the starting address flexibility but resolved
the problem.
The rest of the problems at this time were
mostly software related which will be discussed in the
software section. Refer to figure 5 for test set up.
Note: The XOR ICs are not physically removed from the
board but are disconnected and are not shown in the
schematic drawing.
MAC Board
The analog to digital converter section was
tested for accuracy. To test the accuracy, the input to
the A/D converter was set to +0.99 volt DC and then it
was decreased by increments of about 0.25 volt to -0.99
volt DC (i.e. 0.99, 0.75, 0.5, etc.) and the 8 bits
output was recorded for each input. All the recorded
data was compared to the theoretical values tabulated in
the A/D's spec sheets which is included in appendix B.
Beside a few adjustments in the reference voltage supply
to the A/D (VRT & VRB) to acquire maximum accuracy, the
results were acceptable for the purposes of this
project. As mentioned before only one stage of the 32


HP G236D
Figure 5-Block Diagram of The Test Set up to Debug the Hardware


24
stage MACs was wired and, therefor, due to simplicity
there was no need to test the rest of the MAC Board.
Figure 5 illustrates the test set up.
System Test
Several glitches were found on the CS when all
the address lines were set to zero a state which resets
the accumulator. A pull up resistor on the CS line
assured that this line would stay high all the time
unless a low state was desired and the problem was
resolved.
A second problem was found to be the tri-stated
control lines shared by the Timing Logic and the Address
Decoder. In order to make sure that Timing Logic was off
the line when the Address Decoder was supposed to have
control, a simple routine was added in the software
before the reset cycle to start a count that would set
the CNT OVER line to high and therefor isolate the
Timing Logic.
Software
Due to simplicity of the software at this phase
of the project (only one MAC) the problems were minor
and not due to the design.
Verification of Operation
To test the calculation accuracy of the first
stage and to verify the proper operation of the system


the correlator was provided with three defined signals
one at a time. The signals were autocorrelated and the
results were displayed as binary numbers. Figure 6
demonstrates the set up that was used to operate the
Parallel Process Digital Correlator. Also the results as
they were printed after collection are included in
appendix C.


FUNCTION GENERATOR NO. 1 SETTING
TO PROVIDE THE MASTER CLOCK (MC)
SIGNAL TYPE: SQAURE WAVE
AMPLITUDE: 2 4 Vp-p
FREQUENCY: l MHZ
FUNCTION GENERATOR NO. 2 SETTING
SIGNAL TYPE: SQUARE WAVE/SINE WAVE
AMPLITUDE: 0.98 Vp
FREQUENCY: 7.8 KHZ
DC SUPPLY SETTING TO PROVIDE
TEST SIGNAL
DC VOLTAGE: 0 87 VDC
HP 6236D
HP 8111A
Figure 6-Block Diagram of Ihe Test set up to Verify Operaion


CHAPTER IV
DISCUSSION AND CONCLUSION
The results of phase I of the Parallel
Processing Digital Correlator are collected and
evaluated for three different inputs. All inputs were
autocorrelated and results were printed in binary
format, 16 bits at a time.
The results of autocorrelations were collected
and compared to the theoretical values calculated using
equations (1) and (2).
c(t) = < x(t)x(0) >
where x(t) = A sin(2PIf0t + 0Q) A = Vpeak
hence c(t) = A2/2 cos(2PIfQt) (2)
and c(0) = Az/2
Also for x(t) = Constant (DC value), C(0) = A2
The theoretical calculations for the three cases
tested (DC voltage, square wave and sine wave) were
compared to the results of the Digital Correlator. The
correlator was set to operate as an autocorrelator all
the time and c(0) was calculated five different times
for each case. The worse cases and best cases are
presented in the followings.


28
Vpeak was set to 0.87 volts for DC input and
0.98 volts for square wave and sine wave inputs. The
theoretical value of Vpeak in binary is calculated as
follows: Vpeak = 0.87/0.0039 = 223 and Vpeak =
0.98/0.0039 = 251 where 0.0039 is the A/D's resolution
per one volt DC. (Vpeak)2 = 49763 for Vin = +0.87 VDC
and (Vpeak) 2/2 = 63142/2 for Vin = square wave or sine
wave.
Worst case result for +.87 VDC input after
converting to decimal is: 33686540. Normalizing this to
212 which is the number of samples, the result is
33686540/212 = 8224 and calculating the percentage of
error: (49763-8224)/49763 = 83%. The best case after all
conversions is: (49763-32902)/49763 x 100% = 33.8%.
Worst case result for AC inputs after normalizing is
3714. Error percentage for this particular result is
(31571-3714)/31571 x 100% = 88%. Best case for AC inputs
is 32370 after normalizing. Error rate for this case is
2.5%. Average error rate is calculated by adding all the
error rates and dividing by the number of results. The
average error rate for DC input is about 50% and about
48% for AC inputs.
Major areas that can be greatly improved in
phase II and will directly impact the performance of the
correlator are A/D's reference voltages, Address Decoder


and MAC Board. Since the binary outputs of A/Ds are
critically related to the voltage source that they
compare the incoming signal to, the reference voltage
should be as stable as possible. The design of the Vref
presented in this project is not efficient and perhaps
the inaccuracy of some of the results could be partialy
blamed on Vref drift and noise. This design should be
replaced with one involving a reference switch which has
much higher accuracy and stability. Also to improve the
accuracy the number of samples could be increased. This
can be done by having more counters on the Timing Logic
or to use eight bit counters.
Second improvement would be to replace most of
the logic circuitry in the Address Decoder with PALs.
This will reduce the size and should improve noise
immunity. The MAC Board's wire wrap board should be
replaced with a Printed Wiring Board (PWB) in order to
isolate excessive noise as much as possible. At last if
PALs are used to build the Timing Logic circuit, it is
possible to use one IBM/AT compatible PWB to place all
the hardware and plug it directly in the motherboard.
Although in some cases the coefficients
calculated by the Digital Correlator are not within
acceptable range of what they should be. Nevertheless,


the results prove that with proper design implementa-
tion, and proper equipment, NCR 45CM16 multiplier/
accumulator IC can be used to build an economical real
time Digital Correlator with reasonable accuracy.


31
REFERENCES
[1] Alan V. Oppenheim/Ronald W. Schafer, Digital
Signal Processing. (Prentice-Hall, NJ, 1975).
[2] Murray Sargent III and Richard L. Shoemaker, The
IBM PC from the Inside Out. (The University of
Arizona, 1986).
[3] International Business Machines, IBM PC/AT
Technical Reference. (IBM, 1984).
[4] Texas Instrument Inc., The TTL Data Book. (TI,
1985).


32
APPENDIX A
Schematic Diagrams and Program Listing
Schematic Diagrams for the three boards designed and
constructed for this project are presented here. Every
IC on these schematics is designated with an specific
U"nit number. Also included is a copy of the basic
program written to test the hardware and collect
results.


00010 DEF SEG*S 00020 A=S 00025 N=S 00027 D= 00030 POKE WORD A,0000
00031 POKE WORD A, S.H0500
00032 FOR X=0 TO ifi00
00035 NEXT X
00040 POKE WORD *440002,00000
00070 POKE WORD A,* H0000
00080 POKE WORD A, *'00500
00070 FOR X=0 TO 1000
00074 NEXT
00100 Y=FEEK WORD O5.H0406)
00110 Z = D AMD Y:W=Z AMD D:IF W=0 GOTO 100
00120 POKE WORD A, '.H0D00
00140 R1=PEEK WORD(M):LPRINT
00145 R2PEEK WORD (&H0002 > : LPR I NT
00150 R3=PEEK WORD (? 00160 LPRIMT
00170 LPRINT
00180 LPRINT
00170 LPRI NT






R e. f f erence ~Des i0nator Pins Conoea.te.ct to G round Pina Connected to -VSVoW
u4, U5,U6,m,u8,uq,Ufo, UH, U(2, U13 7 14
Ul4, UI5,U6 ,Ul6, UR, U20, U2l,U22 ,U23,U24,U25,U26 to 20
UI7 8 16
Diagram No* 2.
Address Decoder Schematic
of 2
Note.0; ' 1
(T) "To Simplify these. parts of the schematic not ah
Connections orvd puv numbers are abioyon, msttad
the CollouJinn Chart in etudes oAV the -m\aSir\a *h^o_
trnemon.
RtCCfcvtrvrp* T5^^iar\rilor Pm numbers
jnpvjL-t Ou.Vpu.^.
: jjn8,.u\i i.: 1 j i -. 'i f i ,2,3,4,5 ,6, 7,8,3,l0,n, 13,14,15,16, 17
U20,u2i ; : : ; I" v: : i.;\ 2,3,-f,5,6,1, 8,3,10 18,11,(6.15, K,13,12,U
U22,U23,U24, UZ5 .1 : 4. t : ; t } i. y : i '* 2,4,6,8,11 > 13,15 a 8,16,14,12, ^,1,3,3

i I
i .


91 ,9l'>lrzryL,S*£


APPENDIX B
Specification Sheets and Manuals
A copy of the A/D and multiplier/accumulator' s spec
sheets along with any application notes that were used
are included in this appendix. Also presented here are
schematics and charts of IBM control signals and addres
lines copied directly from IBM hardware manual.


I/O Pm Sipnal Name I/O
C 1 SBHE I/O
C 2 LA23 I/O
C 3 LA22 I/O
C 4 LA21 I/O
C 5 LA20 I/O
C 6 LA19 I/O
C 7 LA16 I/O
c e LA17 I/O
C 9 -MEMR I/O
C 10 -MEMW I/O
c n SDOE I/O
C 12 SD09 I/O
C 13 SD10 I/O
C 14 sdii I/O
C 15 SD12 I/O
C 16 SD13 I/O
C 17 SD14 I/O
C 16 SD1F I/O
I/O Channel (C : ;de JIDthrough J14 and J16)
I/O Pin Sianal Name I/O
D 1 -MEM CS16 1
D 2 -I/O CS16 1
D 3 IRQ10 1
D4 IRQ11 1
D 5 IRQ12 1
D 6 IRQ15 1
D 7 IRQ14 1
D E -DACK0 0
D 9 DRQO 1
D 10 -DACK5 0
D 11 DRQ5 1
D 12 -DACK6 0
D 13 DRQ6 1
D 14 -DACK7 0
D 15 DRQ7 1
D 16 *5 Voc Power
D 17 -MASTER 1
D 16 GND Ground
I/O Channel (D-Side, J1 0 through J14 and J1 6)
I
I
I
System Board 1-21


I/O Channel Signal Description
The following is a description of the system boards I/O channel
signals. All signal lines are TTL-compatible. I/O adapters should
be designed with a maximum of two low-power Shottky (LS)
loads per line.
SAO through SA19 (I/O)
Address bits 0 through 19 are used to address memory and I/O
devices within the system. These 20 address lines, in addition to
LA 17 through LA23, allow access of up to 16Mb of memory.
SAO through SA19 are gated on the system bus when 'BALE' is
high and are latched on the falling edge of 'BALE.' These
signals are generated by the microprocessor or DMA Controller.
They also may be driven by other microprocessors or DMA
controllers that reside on the I/O channel.
LAI 7 through LA23 (I/O)
These signals (unlatched) are used to address memory and I/O
devices within the system. They give the system up to 16Mb of
addressability. These signals are valid when BALE' is high.
LAI 7 through LA23 are not latched during microprocessor cycles
and therefore do not stay valid for the whole cycle. Their purpose
is to generate memory decodes for 1 wait-state memory cycles.
These decodes should be latched by I/O adapters on the falling
edge of 'BALE.' These signals also may be driven by other
microprocessors or DMA controllers that reside on the I/O
channel.
CLK (0)

This is the 6-MHz system clock. It is a synchronous
microprocessor cycle clock with a cycle time of 167 nanoseconds.
The clock has a 50% duty cycle. This signal should only be used
for synchronization. It is not intended for uses requiring a fixed
frequency.
1 -22 Svstem Board


RESET DRV (0)
'Reset drive' is used to reset or initialize system logic at
power-up time or during a low line-voltage outage. This signal is
active high.
SDO through SD15 (I/O)
These signals provide bus bits 0 through 15 for the
microprocessor, memory, and I/O devices. DO is the
least-significant bit and D15 is the most-significant bit. All 8-bit
devices on the I/O channel should use DO through D7 for
communications to the microprocessor. The 16-bit devices will
use DO through D15. To support 8-bit devices, the data on D8
through D15 will be gated to DO through D7 during 8-bit
transfers to these devices; 16-bit microprocessor transfers to 8-bit
devices will be converted to two 8-bit transfers.
BALE (0) (buffered)
'Address latch enable' is provided by the 82288 Bus Controller
and is used on the system board to latch valid addresses and
memory decodes from the microprocessor. It is available to the
I/O channel as an indicator of a valid microprocessor or DMA
address (when used with 'AEN'). Microprocessor addresses
SAO through SA19 are latched with the falling edge of 'BALE.'
'BALE' is forced high during DMA cycles.
-I/O CH CK (I)
' -I/O channel check' provides the system board with parity
(error) information about memory or devices on the I/O channel.
When this signal is active, it indicates an uncorrectabie system
error.
System Board 1-23


-SMEMR (O) -MEMR (I/O)
These signals instruct the memory devices to drive data onto the
data bus. '-SMEMR' is active only when the memory decode is
within the low 1Mb of memory space. '-MEMR is active on all
memory read cycles. '-MEMR may be driven by any
microprocessor or DMA controller in the system. '-SMEMR' is
derived from '-MEMR' and the decode of the low 1Mb of
memory. When a microprocessor on the I/O channel wishes to
drive '-MEMR', it must have the address lines valid on the bus
for one system clock period before driving '-MEMR' active.
Both signals are active LOW.
-SMEMW (O) -MEMW (I/O)
These signals instruct the memory' devices to store the data
present on the data bus. -SMEMW is active only when the
memory decode is within the low 1Mb of the memory space.
1 -MEMW is active on all memory read cycles. 1 -MEMW1 may
be driven by any microprocessor or DMA controller in the
system. '-SMEMW is derived from '-MEMW' and the decode
of the low 1Mb of memory. When a microprocessor on the I/O
channel wishes to drive -MEMW', it must have the address lines
valid on the bus for one system clock period before driving
'-MEMW active. Both signals are active low.
DRQ0-DRQ3 and DRQ5-DRQ7 (I)
DMA Requests 0 through 3 and 5 through 7 are asynchronous
channel requests used by peripheral devices and the I/O channel
microprocessors to gain DMA service (or control of the system).
They are prioritized, with 'DRQO' having the highest priority and
'DRQ7 having the lowest. A request is generated by bringing a
DRQ line to an active level. A DRQ line must be held high until
the corresponding 'DMA Request Acknowledge' (DACK) line
goes active. 'DRQO' through 'DRQ3 will perform 8-bit
DMA transfers; 'DRQ5' through 'DRQ7' will perform 16-bit
transfers. 'DRQ4 is used on the system board and is not
available on the I/O channel.
System Board 1 -25


-DACKO to -DACK3 and -DACK5 to -DACK7 (O)
-DMA Acknowledge 0 to 3 and 5 to 7 are used to acknowledge
DMA requests (DRQO through DRQ7). They are active low.
AEN(O)
'Address Enable' is used to degate the microprocessor and other
devices from the I/O channel to allow DMA transfers to take
place. When this line is active, the DMA controller has control of
the address bus. the data-bus Read command lines (memory and
I/O), and the Write command lines (memory and I/O).
-REFRESH (I/O)
This signal is used to indicate a refresh cycle and can be driven by
a microprocessor on the I/O channel.
T/C (O)
'Terminal Count' provides a pulse when the terminal count for
any DMA channel is reached.
SBHE (I/O)
'Bus High Enable' (system) indicates a transfer of data on the
upper byte of the data bus, SD8 through SD15. Sixteen-bit
devices use 'SBHE' to condition data bus buffers tied to SD8
through SD15.
-MASTER (I)
This signal is used with a DRQ line to gain control of the system.
A processor or DMA controller on the I/O channel may issue a
DRQ to a DMA channel in cascade mode and receive a
' -DACK '. Upon receiving the 1 -DACK ', an I/O
microprocessor may pull '-MASTER' low, which will allow it to
I -26 System Board


The following figure shows the layout of the system board
I
nfPANEL
CONNECT*
*rvor
CONNICIO*
rrpf O'
Difti'
w'tc*
1-60 Svstem Board


Svstem Board 1-61
am 7 1 <7 *9 71 >?
<*>' 3 *7 '
am I **
am r
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rtl 7 3
am 7t
am
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System Board (Sheet 1 of 22)
Logic Diagrams


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1-62 Svstem Board


System Board 1-63
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I Noiiaji


1 -64 System Board
System Board (Sheet 4 of 22)


Svstem Board 1-65
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IN0I13II


1-66 Svstem Board

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System Board 1-67
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----
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System Board (Sheet 7 of 27)
111011919 ,


-68 System Board
B"1 *01 ifw> ---------
|S ItH ini ----------------------
ISM? 0| **>(!----------------------
----------------------
Mft------------------------
Ht*------------------------
Hfr.
"fit
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tHt ft SV?
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5*1-------------
s n n.
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It*-------------
S*S------------
............


S*l
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I5'l | -MSI*--------------------
ISMI f| -ty*----------------------
IS"I M r*5cM-------------------
IV* 1 - ------------------
System Board (Sheet 8 of 22)


uo# mu aai* ri e* Mcivjis-U
MC10319
Specifications and Applications Information

HIGH SPEED 8-BIT ANALOG-TO-OiGITAL CONVERTER The MC10319 is an 8-bit high speed parallel flash A/D convener. The device employs an internal Grey code structure to eliminate large ouiout errors on last slewing inpul signals, h is fully TTL comoatioie. reouinng a *5.0 V suopiv ano a wide tolerance neg- ative supply of -3.0 to -6.0 V. Three-state TTL outputs allow Direct 0'ive of a Gate pus or common I/O memory. The MC10319 contains 256 parallel comparators across a pre- cision input reference network. The comparator outputs are ted to latches anc than to an encooer network, to proouce an 6-Dii oata Dyie plus an overrange Pit. The oata is latched ano convened to 5-state LS-TTL outputs. The ovenange Pit is always active to allow tor either sensing of the overrange condition or ease of interconnecting a pair of devices to proouee a 9-Pit A/D convener. Applications include Video Display and Radar processing, high speed instrumentation and TV Broeocast encoding. internal Grev Code for Speed and Accuracy, Binary Outputs 6-Bit fiesoiution/9-Bit Typical Accuracy Easiiv interconnected tor 9-Bit Conversion 3 State LS-TTL Cutouts with True and Complement Enable inputs 25 Mh; Sampling Rate Wipe input Range: 1.0-2.0 Vp.p Between -2.0 V Low input Capacitance: 50 pF Low Power Dissipation: 618 mW No Sampie/Hoid Reouired tor Vioeo Bandwidth Signals Smgie Cioc* Cycle Conversion

BLOCK DIAGRAM Awn *** gno ww. vCd*ie c v!t vCCrpi e t 0.11. w ns I i ns. nt m ; T h. i | 1 Wt ; MC1Q3IS 1 1*, j uwi < L u--..1 iiirs*T~i i ,'i i i i o- 1 1 fix**-" 1 1 I '<* D > i I ; 1 a o* rsi | 1 1 1 1 m 1 I t** >\ J PV***WN#I n 1 r*/ *"* r^/l 1 ICi-TTl r B3 m, .'ll i ill: rtei : 1 : in 1-r-- ? | 1 [_ J [_ 1 1 o oc Oil air I c MS; be 00 Cwc iiwe* Ivon MS!
HIGH SPEED
8-BIT ANALOG-TO-DIGITAL
FLASH CONVERTER
SILICON MONOLITHIC
INTEGRATED CIRCUIT
l SUFFIX
CERamiC PACKAGE
CASE 623-OE
ORDERING INFORMATION
Pvvoet | T*mp**tur* Ar>9 | Fcft*e j
MC1C319* I PieOCt Cr*mic |
CMOTOAOCA tMi
DS9680
fAepiacmg NPIfiO)


ABSOLUTE MAXIMUM RATINGS
j Parameter | Symbol Vaiua | Unn
Swopiy Vonagt vCCl*l.(D) VEE *7.0 I -7.0 1 Voc
Poan 1 Digue) input voltage (Pm* 10*20) VD! -OS 10 -7.0 I Voc
Analog Inoui Voltage (Ptni 1, 14, 23. 74) VilAl - 2.5 ic -2.5 | Voc
Reference Voltage Span (Pm ?4-Pin 23) - 2.3 1 Voc
Applied Output Voiiape (Pint a-1C. 21 m 3-Staic) - -0.3 10 7.0 | voc
junction Temperature -150 ' C i
Storage Temperature *10 -65 ic 150 ' *C |
Davicaa tnouK) not M oparatac at >m Tn '*fccommetoa6 Operating limn*' P'W'O* 9w actual o*xi optraiaon
RECOMMENDED OPERATING LIMITS
Peramete' Sempci ! M*n 1 rv Mai Unn
>e*er Supow wenppe 15) * COAf I -4.5 5X J *5.5 Vac
.. (P*m 11 271 - TCCIC'. 1 1
i VCC(0I VCr,Ai AV-c i -0.1 C 1 -0.1 Voc
-L-Ppwer Suocwv Vouage fPr. >3! - vEf 1 -6.C -5.0 i -3.C 1 vac
1 Digital inout Vortapet (Pins 15-20) VHDT i 0 - 1 *5.0 1 voc
__ j Aaiop input iPn U; ... *ti'' : -2.1 - I -2.V i Voc
Voltage 4>RT IP*o 24! VR-- j -1.0 - 1 *2.1 1 Voc |
* uonaoe tO'-Ape 23) VRf 1 -2.1 - 1 *ix i Vo: i
1 Vo- Vre 3Vs | -i.c ! - ! -2.1 1 Voc !
1 Vre VEc - ! U i - 1 - 1 voc i
1 Applied Output Voitaoe (Pmj 4-1C. ?1 in 3-State- Vc 1 c i - 1 S.i 1 voc |
I Doe* Purse Wioin Hipn ICKK j 5.0 | 20 | 1 n* i
1 Low icx: ! 15 1 20 ! ! j
^ Xjoc* Ptwevoneu i ''CLr 1 0 1 - 1 <. | MH: |
! Operating Ampien: Temperature | ! t 1 - I -70 1 -c i
ELECTRICAL CHARACTERISTICS Itr < 7* < 70*C. vcc 5.0 V. vEE . -L3V. VRT 1.0 V. Vgg -1.0 V. except
mere noted.)
j Parameter Svmpo j Mm | Tyt l Mai 1 Unn J
TRANSFER CHARACTERISTICS CKL B 25 MH2)
j Resolution ! * 1 - - e.c I Bits |
| Monotpmenv ! MOK I Guarantee? Bui |
j mteprai Nonuneaotv j INL 1 - - 1/4 = 1.0 LSE |
| Differential Nonimesrrtv ! DNl , - 1 - Six LSI j
. ] Differential Pnese (See Figure 16! I d* | IX 0t 1
| Differential Gain (See Figure 16) ! DC - 1 1.0 * !
i Power Swppiv Rereciion Rene PSRF | | LSB/v j
I (4.5 V < Vq- < 5.5 V. Vg£ -5.2 V) 0.1 j
| (-6.0 V < Vgr < -3.0 V. Vcc *5.0 V 1 - ' 0 - 1

MOTOROLA
Semiconductor Products Inc.
2


|Hf K
ELECTRICAL CHARACTERISTICS continue IP* < TA < 7CTC V^C 5.0 V. Vgp -5.2 V. VAg 1.0 V. ecceo* wr>ee noted.l VfIT - * 1.0 V.
| Perimeter I S*eaa | Mm | Tve Mea 1 Unit |
analog input (Pin ui
inoui Current tit V,r Vpg (See Figure 5) I *INL 1 -100 I 0 - 1 |
inoui Current m V, Vrt (See Figure 5) I INh ! 1 60 1 ISC 1 M* !
input Caoacitence (Vr? V*g 2.0 V. See Figure 4) i c, I ! 36 1 - 1 Df 1
input Capacitance (Vpr V*g 1.0 V. See Figure 4) I u ! i 55 1 - i of I
Bipolar OWiet Errp' I ''OS - I 0.1 t - i ise |
REFERENCE
Laooer Resistance (Vpr to Vug, T* ?5*C> i l 1CW 1 130 1S6 1 n
Temperature Coertc*ent I TC ! I -C.2S ! ! %-c
Laooer Capacitance (Pm 1 opem ! t,, i 25 1 - i p'
ENABLE INPUTS (VCC 5.5 VI (See Figure 6)
input Vottape Hipn fPms 15-201 ! Vine 2.0 ! - i - V
mpui Vonape Low (Pm* 15-201 i VILF - ! - 1 0.E V
Input Current fa 2.7 V I *IMf i i C 1 sc A
input Current tit 0 4 V (ft ?N (0 < EN < 5.0 V> I Hi' - 40C j -IOC I - tfA
input Current fa 04V(F EN (pN 0 VI I >il: i -400 | - 10C 1 _
input Current fa 0 4 V tit EN (£n 2.0 V) 1 il: ! 20 ! - 2.0 - **A
input Clamp vonape (ir -16 mA' ! v,Kt i -u ; - 1J t _ V
CLOCK INPUT ivc^ 5.5 V)
input Vonape Hipn i vimC l 2.0 ! - ! 1 Vflc
input Vonape low 1 VILC ! 1 - ! o.e voc
input Current fa 0.4 V (See Figure 7) *ILC I -40C ! -8C 1 i
input Current fa 2.7 V (See Figure 7| *IMC 1 -10C ! -2C i l *A
i input Clamp vonaoe (i^ -15 mA)____________________________i V|<; ~^-5 I * VQc j
DIGITAL OUTPUTS
| Hpn Output vonape Iiq* -40C *A V££ 4.5 V, See Fipure 8! I Vq* ! 2.4 i 3.C I ! V
| Low Output Vonape (iq^ 4.0 mA. See Fipgre 9) vOl j - 0.35 ; D.4 1 V
i Output Snon Crcun Curren** (V^£ 5.5 VI sr - 35 | mA
1 Output Leakage Current (0 4 < Vq < 2.4 V. See Fipure 2. 1 VC: £.5 V. 00-07 m 3-Siate Mooel LK -sc -sc ! M*
1 Output Capacitance (OC-D7 m 3-State Moot! Cpir - s.c - 1 Dr
*Onrv one output m to Ot anonee at t*m. not to eiceetf 1 cone.
ROWER SUPPLIES
i VCC(A, Current u.5 V < v^ia* < 5.5 VI (Outputs unioaoedl CCI*! It 17 25 mA 1
! VCC(D Current 14.5 V < V^cfC* < 5.5 V| (Outputs unioaoed) *CCfD sc 9C 132 mA J
1 Vge Current i-6.0 V < Vgr < -3.0 VI i EE -14 -1C -6.C mA |
I Power Dissipation (V*j* V^p 2.0 V) (Outputs unioaoed) j rc - Bit 995 mW |

MOTOROLA Semiconductor Products Inc.
3


TIMING CHARACTERISTICS (Ta 2S*C. VCC #6.0 V, Vg£ Stt Svttem Timmg Diagram.) -S.J V. VT - 1.0 V. V*g - 1.0 V.
J Parameter Svmooi ! Mm j Tw> 1 Max 1 Unn
INPUTS
[ Mm Clock Pula* tNipm High 1 1 Mtn Clock Put*# Hucm Low 1 >CKl I i 15 1 1
1 Max Clock Aiac. Pall Tim# I ip a i l IOC ! 1 ns
| Clock Preouencv 1 'ClK I T f 3C 1 25 i MHj
OUTPUTS
| New Data VaitC from Clock low 1 'C>CDV ! I 15 na
4k Aperture Daiav ! AD f I a.c ! M
| Hold Tim# i in 1 i 6.0 1 ni
1 Data High to 3-Siate trom fcnapi# Low* 1 | Data iow to 3*Siaie from Enaoie low'* 1 *EL2 i ie - na
Data High to 3-Siate trom £naoi# Htgr* 1 'In? - i 3* ! ni
' Data LOW to 3-State trom Enaoie ipn* j i ii i - na
Vaitd Data trom Enapi# High (Pin 20 0 V)* 1 *EDv i ! u i ns
VaC Data trom Enaoie Low (Pin 15 5.0 V* ! I£DI' - i 16 1 m
Output Transition Tim#* M0V90T*: ! tfr : 8.0 | - ni
ie# k*gur* 3 t output aaens.
MN DESCRIPTIONS
! Svmooi Pin f Description
j V*M i | The miepomt OJ the retarence resistor toooer Bypassing can oe 1 ooo# at this pomi to improve performance at high treouencres
I GNC 2.12 16.22 I Power tupDiv ano ngnai grounc The tou pms ahouie P# connected 1 oirectiv together, arid through a tow impeoance to the power supply
| Ovt. 3 | Gvtrrange ouioul moicatei it more ootmve than Wr#-1/5 l$E. This output ooet not nave 5*fiait capaomtv
j D?-D0 4-1C. 21 1 Dipnei Outoun. 07 (Pth 4) is me MSE. DO (Pm 211 is the lSE. LSTTk 1 compatible wrth 3-staie capapiiitv.
vCCI0 11,17 i Power suppiv tor th# oigita* lectior #5.0 V. s 10V reourac j
VEE 13 Negative Power suppiv. Nominally *5.2 V, it can range trom *3.0 to *6.0 V. ano mutt oe more negative than vpp pv > 1.3 V.
v 14 Signal vortag* mpui Tms voitape is compared to tn# teierence to generate a pigrtai eowivatant. Input impeoance ik nominally 16*33 kfl in parallel with 36 pf
VCCIA' is Power suppiv forth# analog lector *5.0 V 10% reouireC
1 a.1 11 Ckoec mouv TTl compatible i
1 EN 1 19 Ena Pi# input TTl compaupit. a Logic "1** land Pm 20 a Logic *TT) anap*es me oata outputs. A Logic **C" puts m output! m a 3-state moot
En 20 Enaoie input. TTl compatible. a Logic *T land Pm 15 a Logic "i") enapies the oata outputs. A Logic V puts ih# outputs m a 3-ftate moot
*re Tht oonom (meat negative point) ot me internal roierence resistor tapper
Vrt | 24 The top imoii poamve pomt) pf the miemai reference roaistor iappei
MOTOROLA Semiconductor Products Inc.




vw ouirtii vrxfAn ivwisi u xrui oitwiHl
figure 4 iMnrr capac/tance ^ ipin ui
FIGURE S INPUT CURRENT £ IPIN 14)
FIGURE INPUT CURRENT £ ENABlX. ENARLfc
FIGURE ? CLOCK INPUT CURRENT
v*. wnn voltage noltsi
21 It 4.C
V*, INPUT VOLTAGE NOlTSl


cwwuni.hns
AGuRE 10 SUPPLY CURRENT V>rwi TEMPERATURE FK5URC 11 SUPPLY CURRENT v*r%a TEMPERATURE
r Jr r irTr
*M|K/TTlM*IUTuRt ro
FIGURE 12 DEFERENTIAL LINEARITY ERROR
AMMWTTlMFflUTuRf ro
FIGURE 13 INTEGRAL LINEARITY ERROR
FIGURE 1* DIFFERENTIAL LINEARITY ERROR FIGURE IS INTEGRAL LINEARITY ERROR
MOTOROLA Semiconductor Products Inc.
7


DESIGN GUIDELINES
INTRODUCTION
REFERENCE
The MC1D31S ii a high-speed. 8-bit. parallel ("Flash)
type ansiog-to-digitat convener containing 256 com-
parators at me front nc. See Figure 17 tor a block Dia-
gram. The comparatori are arrangao tuch that one in-
put 0* aach is relerenced to evenly tpacao voltages,
oenved from the ratarance resistor ladoer. The othar
input of the comparators is connactao to the input signal
(VtflJ. Some of the comparator s Oittarantial outputs will
be "true/* while other comparators will have "not true"
outputs, oepenoing on mair relative position. Their out-
puts are than tatcnaO. ano convened to an 8-bit Gray
COOa by the Differential Latch Array. The Gray cooe en-
sures any input errors Oue to cross talk, -lead-thru, Or
timing disparauec. result in glitches at the output of only
a few LSBs. ramer than me more traditional 1/2 scale
ano If* scale gmches.
The Grtv cooe n than translated to an 8-Dit binary
code, ane me differential levels are translated to TTl
levels before being applied to the output latches. EN-
ABLE inputs at this fmai stage permit the TTL outputs
(except Overrange) to be put into a high impeoance
(3-state) conoition.
ANALOG SECTION
SIGNAL INPUT
The signal voltage to be digitized (V,n) is aooLed
simultaneously to one input of each of tne 256 com-
parators through Fm 14. The other inputs of the com-
parators are connected tc 256 evemy soaced voitaoes
oertved from the reterenec laooer. The output cooe oe-
penes on me relative position of the tnout signal and
tne reference voltages. The comparators have a
banowiom of >50 MHz. which is more than sufficient
for tne allowable (Nyouist theory) input freouenev of
12.5 MHz.
The current into Fin 14 varies iineany from 0 (when
vin VRB*10 ** Iwnen V*, Vrj). If V,n is taxen
below VRg or above Vr*. me input current will remain
at tne vaiue corresoonomg to VRg and Vrt respectively
(see Figure 5). however. V,n must be maintained wtmm
the absolute range of r2.5 volts (with respect tb
ground) otherwise excessive currents will result at
Fm 14. oue to internal eiamos.
The inout capacitance at Fin 14 is typically 36 pF if
IVrt VRg] is 2.0 volts, and increases to 55 pF if |Vr-
- Vpg) is reduced to 1.0 volt isee Figure 4]. The ca-
pacitance is constant as V,r vanes from Vrt oown to
0.1 volt aDove vpg. Taxing V|r to Vpg will snow an
increase in tne caoacitance of *50%. H V,n is taxen
above Vr* or beiow Vpg. me caoacitance will stay at
the values corresponding to Vrj and VRg. respectively.
The source impeoance of me signal voltage should
be maintained beiow 100 ft (at me treouencies of in-
terest) in order to avoid sampling errors.
The reference resistor (adder is composed of a string
of eouai vaiue resistors so as to provioe 256 eouaiiy
spaceo voltages for tne comparators (see Figure 17 tor
the actual configuration). The voltage difference be-
tween ao/ecem comparator! corresponos to 1 LS6 of
tne input range The first comparator (closest to Vpg)
it referenced 1/2 LS6 above VRg. ano tne 256th com-
parator (tor me overrangel is referenced 1/2 LSB beiow
Vrt. The total resistance of the laooer is nominally 130
ft. r 20V reouinng 15.4 mA 1.0 von There is a nominal warm-up change of 9.0%
in me iaooer resistance due to tne 0.29V*C temper-
alure coefficient.
The minimum recommended span |Vrj VRg} is
1.0 volt. A lower span will allow offsets and nonlinear-
ities to become significant. The maximum recom*
menoec span is 2.1 volts Oue tc power (imitations of
the resistor laOOei. The spar may Oe anvwnere within
me range Of -2.1 to *2-1 volts with respect to ground,
and VRg must oe at less: 1.3 volts more positive than
Vcg. The reterence vonagts must be stable and tree of
noise ano sotxes. since tne accuracy of a conversion is
directly related to tne oueiify of the reference.
in most applications, tne reference voltages will re-
main fixed, in applications involving a varying reference
for modulation or signal scrambling, tne modulating
signal may be applied to Vr-, or VRg, or Doth. The out-
put will vary mversiv with me reterence signal, intro-
ouemg s nonlinearity into tne transfer function. The so-
omon of tne moouiatmg signal sne tne dc level applied
to the reference must oe suen that the aosoiute voltage
at Vrt and VRg are maintained within the values listed
in me Recommenoed Operating Limns. The RMS value
of the span must be maintained <2.1 volts.
Vrn^ (Fm 1) is the mioooim of the resistor ieooer.
excluding me Overrangc comparator. The vonage a:
VpM is: .
Vp-
vre
2.0
- 1/2 ISE
in most aoplications. bypassing this pm to ground (0.1
mF) is sufficient to maintain accuracy, in applications
involving very high treouencies. ano wnere linearity is
critical, rt mav De necessary to tnm tne voltage at tne
miopomt. A means for accomplishing this is indicated
in Figure IE.
ROWER SUPPLIES
VCC(A) fFin T5) is the positive powe' supply for the
comparators, and Vq*(qj (Pins 11. 17) is the positive
power supply for the Oigitsi portion. Both are to be 5.0
volts, r 10%. and the two are to be within 100 millivolts
of each ether. There is moireci interna) coupling be-
Tween VccfDj and V^CfAF M ,n*v are powered seoa-
rataiy. ano one suooty tails, there will be current tiow
through the MC1031S to the faiiec supply.
MOTOROLA
Semiconductor Products Inc.
i


ICCIA1 nominally 1? mA. and ooes not vary with
Clock freouencv or with Vm. ft ooes very linearly with
VeciA)- *CC(0> ** nominally 90 mA. ano it moepenoent
of clock freouency. ft floes vary, riowt^r, bv 6-7 mA
at V,r is Changed. with the lowest currant occurmg
wnan Vtn Vrt. ft vanes imtariy with VQ£tO\-
Vgg it th# negative powar supply for the comparators,
ano is to be within the range *3.0 to *6.0 vofts. Ad-
ditionally. Vg£ mutt Pa at least IJ volts more negative
than Vfig. ££ it a nominal 10 mA, and it indepenoent
Of clock treouency. Vm> and Vg£.
for proper operation, the tuopliet mutt be bypassed
at the tC. A 10 tantalum, in parallel with a 0.1 **F
ceramic it recommended for each supply to ground.
DIGITAL SECTION
CLOCK
The Clock input fPin 16) is TTL compatible with a typ-
ical freouency range of 0 to 30 MHi. There is no duty
cvcie limitation, but the minimum low and high times
must be adhered to. See figure 7 tor the input current
reouiremems.
The conversion seouence is shown in Figure IS. and
is as follows:
e On the nsmg edge, the data output latches are latched
with old oats, ano the comparator output latenes are
released to follow the input signal |Vtn).
During the high time, the compereiors track the input
signal Tne data output iatenes retain the old oats.
On the taiimg edge, tne comparator outputs are
tateneo with the oata immediately prior to this eoge.
The conversion tc dgttai occurs within the oevice.
and the oata output latenes are released to indicate
the new oata within 20 ns.
During the clock low time, the eomoarator outputs
remain latcnec. ano the oata output latches remain
transparent.
A summary of the seouence is mat oata present at
Vin just prior to the Clock falling eoge is digimec and
available at tne data outputs immediately after that
same tailing eoge.
The comparator output latches provioe me circuit
with an effective sempie-ano-noio function, eliminating
the need tor an external sampie-ano-nold.
enable inputs
The two Enable inputs IPms IS. 20) are TTL compat-
ible. ano are used to cnange me data outputs (D7*D0)
from active to 3-siate. This capability allows cascading
two MCl031Ss into a 9-bit configuration, flip-fiooomg
two MC1031S* into a SO MHi configuration, connecting
me outputs directly lo a data bus. multiplexing multiple
conveners, etc. See the Applications information sec-
tion tor more Details, for the outputs to be active. Pm
IS must be a Logic M1.* and Pm 20 must be a Logic "C."
Changing either input will put the outputs into the high
impeoance moot The Enaoie inputs affect only me
state of me outputs tnev oo not inhibit a conversion.
The input current into Pms IS and 20 is shown m figure
6. and the input output timing is shown in figure 1
and 20. Leaving either pm open is eouivaient to a Logic
~V although gooo oesign practice delates that an m*
put ahoulc never be left ooen.
The Overrange output (Pm 3) is not affected Oy the
Enable inputs as tt ooes not have 3*state capability.
OUTPUTS
The oata ouiouts (Pms a-10. 2D are TTL level outputs
with high impeoance capability. Pm a is me MSB (D7),
and Pm 21 ts me LSB (DO). The eight outputs are active
as tong as tne Enable moms are true (Pm IS hign.
Pm 20 low). Tne timing of tne outputs relative to the
Ooc mom and The Ena&le inputs is snown in figures
1 and 20. figures E and S indicate tne output voltage
versus toao current, while figure 3 indicates the leakage
current when m me hign imoeoance moot.
The ouioui cooe is natural omary. oepmed in me tabte
beiow.
The Overrange output (Pin 3) goes high when the in*
pul. V,n. more positive mar. vp*; 1/2 LSE. This
output is aiwavs active n ooes not have high impeo-
ance capability. Besioes being used to moicate an input
overrange. it is additionally used for cascading two
MC10319* to form a S-Pil A/D convener tsee figure 27).
1 V*T- Vn( Lem Output
! Input 2.0*1 V. 0 V 1.0 V/-1.0 v 1.0 V, 0 V Cmi Overrtnpr
>V*T 1/2 LSE >2.0** V >0.9961 V >0.9960 V 1
V*y 1/J LSE 2.0*4 V 0.9961 V C.9980 V 0 1
VRT 1 LSE 2.0*0 V C.9S? V 0.5961 V 0
vrr 1*1/2 LSE 2.036 V 0.9W V 0.99*1 V 3 X 1 X 0
Miopomt 1.03* V 0.000 V 0.9000 v o* 0
VRe 1/; LSB 4.0 mV -0.SM1 V * 1.96 mV 00*- -01H -* 0
<''HE <0 v < 1.0 v <0 V 0G* 0

MOTOROLA Semiconductor Products inc.
9


APPLICATIONS INFORMATION
POWER SUPPLIES, GROUNDING
The PC board lavout. anc the oualitv of the power
tuppiies and the Qrouno system t the 1C ere very im-
portant in orotr to obtain proper operation Noise, from
any source, coming into the Oevice on Vqq, Vgg. or
prouno can cause an incorrect outout cooe due to in-
teraction with the analog ponton of the circuit. At the
same time, noise penereiec within the MC10319 can
cause incorrect operation if that noise does not have a
clear path to ac prouno.
Both the Vqc and Vgg power supplies must be
decoupled to prouno at the 1C (within V max) with a 10
#*F tantalum ano a 0.1 m? ceramic. Tantaium capacitors
are recommenoeo since eiecuoivuc caoacitors simpiv
have too much mouctance at the frtouencies of interest.
The oualitv of the V££ and Vg£ supplies should then
be checxeo at the 1C with a hipn treouencv scope. Noise
spikes iaiwevs present wnen pipitai circuits are present)
can easilv excaeo 400 mV peat, and if they pet into me
anaiop portion of the 1C. the operation can be disrupteC.
Noise can be reouceo bv inserting resistors and/or in-
ductors between the supplies ano the 1C.
If switching power supplies are usee, mere will usu-
ally Pe spikes of 0.6 votts or greater at treouencies of
60*200 kh2. These spites are generally more difficult to
reouce because of their greater energy content. In ex-
treme cases. 3-termmei regulators (MC78L06ACF.
MC7906.2CT), with appropriate high treouencv filtering,
should Pe usee ano oedicatec to me MC10319.
The nppie content of the suopues snouic not allow
their mapnituoe tc exceeC the values m the Reeom-
menoec Operating Limits.
The PC Dosrc tracks supplving and Vgc to the
MC10319 should preferably not be at me tail end of the
Dus distribution, after passing through a mare of oiguai
circuitry. The MC10319 should oe close to the power
supply, or the connector where me supply voltages en-
ter me boarc. if me Vgf and Vgc lines are suopivmg
considerable current to other parts of the pparos. men
h is preferable to have oedieated lines from the supply
or connector directly to the MC1C31S.
The tour ground pins 12.12.16.22) must Pe connected
directly together. Anv long path oeween them can cause
stability problems due to the mouctance (<£.25 MH2) of
the PC traeks. The ground return for the signal source
must be noise free.
REFERENCE VOLTAGE CIRCUITS
Since the aecuracy of me conversion is directly related
to me oualitv of the references, it rs imperative that ac-
curate anc staple voltages Oe provided to Vrj and Vpg.
tf the reference span is 2 volts, men 1/2 LS6 is only 3.9
millivolts, and h is oesireabie mat Vgy and Vpg be ac-
curate to within this amount, and furthermore, that they
do not orrh more than mis amount once set. Over the
temperature range of 0 to 70*C. a maximum tempera-
ture coefficient of 28 ppm/*C if reouired
The voftage supples used for oigitai circuits should
preferably not be used as a source lor generating Vrt
and Vftg, due to the noise spues (50*400 mV) present
on the supplies and on their ground lines. Generally
z 16 volts, or 12 volts, are available for analog circuits,
anc are usually clean compared tc supplies used lor
Oigitel circuits, although nppie may oe present in vary-
ing amounts. Ripoie is easier to finer out than spites,
however, and so these supplies ere preferred.
Figure 21 oepicts a circuit which can provioe an ex-
tremely steDie voltage to Vrt at the current reouired
(the maximum reference current is 19.2 mA <£ 2.0 volts).
The MC1400 and MC1403 senes of reference sources
have very low temperature coefficients, pood noise re-
jection. and a high inmai accuracy, allowing me circuit
to be built without an adiustmem pot if me voltage
is to remam iixed at one value. Using 0.1** wirewounc
resistors tor me divider provioes sufficient accuracy and
stability m many cases. Alternately, resistor networxs
provioe high ratio accuracies, and dose temperature
tracking. If me application reouires Vrt to be changed
periodically, the two resistors can be replaced with a 20
turn, eermei potentiometer. Wirewounc potentiometers
should not be used for this type of application since me
pot's slider jumps from wmomg to winding, and an ex-
act senmg can oe difficult to ODtam. Cermet pots allow
tor a smooth continuous adjustment.
In Figure 21, R1 reouees the power dissioation m the
transistor, and can pe carbon composition. The 0.1 u?
caDaotor in the feedback path provioes stapiiitv m tne
unity gam configuration. Recommenoec op amps are:
LM35E. MC34001 senes. LM306A. LM32<. anc LM11C.
Ofiaet drift is me key parameter to consioer in enoosmg
an op amp. ano tne LM30BA has the lowest orift of those
mentioned. Bypass capacitors are not shown m Figure
21. but should aiwevs be provtoec at the input to me
2.6 volt reference, ane at the power supply pins of the
op amp.
Figure 22 snows a simpler and more economical cir-
cuit. using me LM317L2 regulator, but with lower initial
accuracy ano temperature stability'. The op amp/current
booster is not neeoeo since the LM317L2 can supply the
current oireeiiy. In a well controlled environment, this
circuit will suffice for many applications. Because of the
lower initial accuracy, an adjustment pot is a necessity.
Figure 23 snows two circuits for providing the vonaoe
to Vre The circuits are simitar to those of Figures 21
anc 22. and have simitar accuracy and stability. Al-
though the MC1400G2 is mean: to provide a positive
voltage, it can pe configured to provioe a negative r#g-
uiated voltage by grounomg the input ano output, and
Oerivmg me reguiateo voltage at the ground pm (Pm 4).
The MC1403 senes of regulators cannot be used in this
menner. The outout transistor is a pNp in this case smee
tne circuit must sink the reference current.
MOTOROLA Semiconductor Products Inc.
10


Hk
VIDEO APPLICATIONS
Tne MC10319 is tunable lor digitizing vioeo signals
directly without signal conditioning, annowgn the stan-
dard 1 von p-p video signal can be amplified to a 2.0
volt p-p signet tor eligntiy better accuracy Figure 2*
snows the input (top trace) eno reconstructed output of
a standard NTSC test signal, sampled at 25 MSPS. con-
sisting of a sync pulse. 3.56 MHz color Durst, a 3.56 MHz
signal in a Sm*x envelope, a puise. a white level signal,
and a Disc* level signal. Figure 25 snows a Sin** puise
that has been digitized and reconstructed at 25 MSPS
The width of the pulse is *450 ns at the oase. Figure 26
shows an application circuit tor digitizing video.
9-BIT A/D CONVERTER
Figure 27 snows how two MCl0319s can be con-
nected to form a 9-bu converter. In this configuration,
the outputs (D7-D0) of the two 8-bit conveners are par-
alleled. The outputs of one device are active, while the
outouts of other are in the 3-state mode. The selection
is made by the OVERRANGE output of the lower
MC10319. which controls Enable inputs on the two oe-
vices Additionally, this output provides the 9th pit.
The reference ladders are connected th senes, pro-
viding the 512 steps reauired for 9 bits. The input volt-
age range is determined by Vr? of the upoer MC1C31S.
and VRg of me lower oevice. A minimum of 1.0 volt is
reouirec across each convener. The 500 fi pot (20 turn
cermet) allows for aoiustment of the midpoint since the
reference resistors oi the two MCl0319s mav not be
identical in value Without the aoiustment. a non-eouai
voltage divisioo would occur, resulting in a nonlinear
conversion. If tne reierencas are to be symmetrical
about ground le g., r 1.0 volt). tne aoiustment can be
eliminated, and tne midpoint connected to ground
The use of latches on the outputs is optional. De-
pending on the application.
50 MHz. S-BIT A/D CONVERTER
Figure 28 snows how two MCl0319s can be con-
nected togetner in a flip-flop arrangement in oroef to
have an effective conversion speed of 50 MHz. The
74F74 D-type flip-flop provides a 25 mhz clock to aach
convener, and at the same time, connois the ENABLES
so as to alternates enable ano Oisabie the outputs. The
Overranges oo not have 3*staie capability, ano so can-
not be paraiieiac. instead they are OR'C together. The
use of latches is optional, anc oeoenos on the appli-
cation. Data shouic be latcntd, or written to RAM (m
a DMA operation), on the high-to-iow transition of tne
50 MHz cioct.
NEGATIVE VOLTAGE REGULATOR
In me cases wnere a negative power supply is not
available ntitner the 3.0 to 6.0 volts, nor a higher
negative voltage from which tc oertve it the circuit
of Figure 29 can be used to generate >5.0 votts from
tne *5.0 votts suopiy. The PC ooarc space reouired is
small 1*2.0 tn*), anc it can be located physically ciose
to tne MC1Q31S. The MC34063 is a switching regulator,
and in Figure 25 is configured n an inverting mode of
operation. Tne rtguiator operating specifications are
given in tne Figure.
FIGURE U DIFFERENTIAL FHASE ANO CAIN TEST
Voec
Signal
(See Beiow)
MC10319 i
out r
8/
F374
Late*
MDS-125C
12 Br. D/A
Doc* -
IJ03
i DC
tc
Anaivier
0>nv**vwi e-a emout A tat imi cometw
m*t o tat
biififmvi pn*M A *en w**i ceme*r te tnai
* e tat.
MOTOROLA.
Semiconductor Products Inc.
n


ncunt n mcioiii
MOTOROLA Semiconductor Products Inc.
12


FIGURE 11 ADJUSTING VKM FOR IMPROVED LINEARITY
FIGURE 21 PRECISION VT VOLTAGE SOURCE
*5.0 v O
10 **F
R1 100 n io* *5.0 V
620 n tOf 15 V
VCC(A) VCC(D)
25 MH; .
ClOCt '
vrtW
soo n >
vhb >-
CLK
VRT
V*M
Jxfie
o >
07 i
I
OulDtf
Diu
input
Signal
VEE
-5.2 vch
FIGURE 19 CONVERSION SEQUENCE
Comparator Output! Latef*C
IVoIiO Oil* attar ICKOV)
* Ljtct*! Comparator Outouu.
Ot>ani Data Output Later*s
-Data Output! Latct*c. ftaitast!
Comparator Later*!
FIGURE 20 ENABLE TO OUTPUT CRITICAL TIMING
____/ o.s v
w-07
p 5 010 40 V
! 2.5 V fc*i****tci IMCUOOC2 MC140JU IMC74C3AU j
| Lm RQuiat*r. 1.0 mV 0.5 mV 1 0.5 mv |
! Tf tppm>"C} ma 25 40 I 15 |
tor 0-7CTC I a a mV 7.0 mV 4 4 mV |
Initial Accurao i r C.7** 1 r 1V. 1 =,s 1
5.0 to
A0 V *
FIGURE 22 VBT. VOLTAGE SOURCE
1.25 tc 2.00 V
-- LM317LZ pcT m ilaji il AO|.| 340: ssi.0
J 200 s1 ;

LM317L2
1 Una Rtpuianon | 1.0 mV
1 Tr loomPC) mn 6C
! iVoir lor 0-7Ct | 6.4 mV
1 mrtiai Accuracv 4V
* tc VRT
£N J10.9V BIV^
00-07-----^iViiiePiii^
Timing 4n DI-DC mmmmn tuni 10
moicaiac im* * MOTOROLA Semiconductor Products Inc.
13


FIGURE 23 Vfte VOLTAGE SOURCES
mci.ooc: IM337MT
Rl 100 n lor -5.0 V L'rx Rtpuittior I 1.0 mv 1.0 mV
620 n tor 15 V I Tf ipomfC) m I JE
R2 620 0 lor -5.0 V I AV0U, lor 0-7CTC 4 4 mV 6.3 mV
3.0 kn lor -15 v I inmi Aecur*cv z0.2% *
FIGURE 24 COMPOSITE VIDEO WAVEFORM
FIGURE 2S SIN2 X WAVEFORM
i)k


FIGURE 21 AFnjCATKM* CWClirr FOA OtGITBIWC VIOEO
MOTOROLA Semiconductor Products Inc.
is


*GimE 2? -ifT VO CONVERTER
MOTOROLA Semiconductor Products Inc.
16


AGUAE 21 SC MK] S-BH A/D CONVEATEA
<#///////?#}
{*4.5 id 5.5 V}
>
3.0 fcfl
NGUAE 21 -S O VOLT AEGUIATOA
100 SK
I
I I
6 7 * 1 l
MCU063 |
1470 pf 1NU19
-1*
1.0 kfl
WO mM
| Imt A*puli*on |4. V < V. < 5.5 V. 1 *ew 10 mA 0.16V
| iMd Aapuiaiion | Vir 5.0 V. 1.0 mi < 1 < 20 mi 0.4V
| Guiooi Kidd* ! v,. 5.0 V. ,eu. ?0 mi 5 "VD-B
1 Snon Circuit i0ui t V,,.. 5.0 V. A1 0.1 n 1 140 mi
| Ef!icr>cv I V,r 5.0 V. 50 mi 67V
470 '** SS
CKA
c-S.O V/20 mA
470 '
-
MOTOROLA Sem/conc/L/cfor Product Inc.
17


GLOSSARY
APERTURE DELAY The nme difference between the
tempting signal (typically a cioc* togel enc the actual
analog signal convened. The actus* signal convened
mev occur petore or after the tempting tignel. Depend-
ing on the internal configuration of the convener.
BIPOLAR INPUT A moot of operation whereby the
analog input tot an a-D), or output tof a 0*0. mdooes
both negative ana positive values. Examples are *1.0
to 1.0 V. 5.0 to i- 5.0 V. 2.0 to 8.0 V. ate.
DIPOLAR OFFSET ERROR The difference between the
actual and ioeai locations of the 06* to 01* transition,
wnere the ioeai location is 1/2 LSE above the most neg-
ative reference voltage.
DIPOLAR ZERO ERROR The error (usually expressed
in LSBsl of the input voltage location (of an A-D) of the
80h to 81* transition. The ioeai location is 1/2 LSB above
zero volts m the case of an A-D setup tor a symmetrical
bipolar input le.g., 1.0 to 1.0 V).
DIFFERENTIAL NONLINEARITY The maximum de-
viation in the actual step size lone transition level to
another) from the ioeai step sue The ioeai step sue is
defined es me Full Scaie Range divided by ?n in num-
ber of bits). This error must be within 11SB for proper
operation.
ECL Emitter coupled logic.
FULL SCALE RANGE (ACTUAL! The difference be-
tween the actual minimum and maximum enc points
Of the analog input (of an A-D).
FULL SCALE RANGE (IDEAL) The difierence between
the actual minimum ano maximum enc points of the
analog mout (of an A-D). plus one LSB.
GAIN ERROR Tne difference between me actual and
expected gam tend point to eno point). with respect to
me reference, of a oaia convener. The gam error is usu-
ally expressed m LSBs.
GREY CODE Also known as refiecitC binary code, it
is a digital code suen mat each cooe differs from aoia-
cent cooes by only one bit. Since more than one bit is
never enanged at each transition, race conomon errors
are eiimmatec.
INTEGRAL NONLINEARITY The maximum error of
an A-D. or DAC. transfer function from me ioeai straight
line connecting me analog eno pomu This parameter
is sensitive to ovnamics. anc test conditions must De
Specified in oroer to be meaningful. This parameter is
the best overall moicator of me Device's performance.
LSB Least Significant Bil h is the lowest oroer bit of
a binary cooe.
LINE REGULATION The ability of a voltage regulator
to maintain a certain output voltage as me input to the
regulator ts varied The error ts tvpicaiiv expressed as
a percent of me nominal output voltage.
LOAD REGULATION The ability of a voltage regulator
to maintain a certain output voltage as the load current
is varied. The error is typically expressed as a percent
of the nominal output voltage.
MONOTONICITY The chereeterisnc Of me transfer
function whereby increasing me mout cooe (of a DaC).
or me input signal (of an A-D). results m me output never
Decreasing.
MSB Most Significant Bit. ft is me highest oroer bn
Of a binary code.
NATURAL BINARY CODE A binary code defined by:
N A*?" .... A323 Aj?2 A,31 AojO
where each "A** coefficient has a vaiue of 1 or 0 Typ-
ically. all teroet correspond to a zero input voltage of
an A-D, ano all ones correspond to the most positive
input votieQe.
NYOUIST THEORY See Sampling Theorem.
OFfSET BINARY CODE Applicable only to biooiar in-
put for output) oata converters, u is me same as Natural
Binary, exceot mat all reroes correspond to tne most
negative input voltage (of an A-D). while all ones cor-
respond to the most positive input.
POWER SUPPLY SENSITIVITY The change in a oats
convener s penormance with changes in the powef
supply voitageisi. This parameter is usually expressed
in percent of full scale versus }V.
QUANTmZATlON ERROR Also xnown as animation
error or uncertainty. It is the inherent error involved m
aioimmg an analog signal oue to tne finite numoer of
steps at tne oigital output versus me mfmtte number of
values at me anaiog input. This error is a minimum of
r 1/2 LSB.
RESOLUTION The smallest ehange which can be dis-
cerned bv an A-D convener, or prooucee by a DAC. It
is usually expressed as me number of bits. n. wnere me
convener has 2r* possible states *
SAMPLING THEOREM Also known as tne Nvouist
Theorem, it states tnat me sampling treouency of an
A-D must be no less men 2x tne highest treouency (of
interest) of me analog signal to be digitized in oroer to
preserve the information of that anaiog signal.
UNIPOLAR INPUT A mode ol operation whereDv me
analog input range (of an A-D), or outout range iof a
DaC). includes values of a signal ooiarny. Examples are
0 to 2.0 V. 0 to 5.0 V, 2.0 tc 8.0 V. etc.
UNIPOLAR OFFSET ERROR The difference between
the actual and total locations of me 00* to 01* tran-
sition. wnere the ideal location is 1/2 IS6 above me
most negative input voltage.
MOTOROLA Semiconductor Products Inc.


OUTLINE DIMENSIONS
on*
i c*vioawTio'
U*X>S **"**&
0AAAU1.
1 UA0!>
m'UMO'TM
W*
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AfcMAAUU
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: r :x sor :r*
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>s* i: or.ir i
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t SUFFIX
CERAMIC package
CASE (23-DS
wo'orou mt njflt 10 "tnr c'v'>p*> ** >y***' **"C* to p*O0nCT to iwiNit iwacmoa eoMf* mote* on oet
*i OM powci o* c*rcw*' ovtcepo no**** eon ce*^* an Heonw wno> m
paiomi t^n m* ifmei m** **oo>om otp*o>c weoowim o motion me Mowe* me n ttwti ooPn^miy-
MOTORCIA Sem/concuefor Products Inc.
is



^C-io.c;-**-*vv.-r .r.'**
i '**. s-*~r^\. '-^T* ''. -v ...*,Jr _* : NCR45CM16
^k|p|^IS!3H&'CM0Sl6 X 16 BIT' ' -v-' .....-
^^S'lNGLE PORT MULTIPLIER/ACCUMULATOR '*-.
^general description.-- '- y.
.:" The NCR45CM16 a*3* pin CMOS multiplief/accumuieror tor un witn 16-bit rrucroorooruor systems. All input and outx>ut
Ocu are transferred Throu^ iingi# 16-bit bidirectional data Dui in ugned two'* complement forme;. Thu device it TTU
'VCMOS compatible and r*ouire* no ciocx due to its tool static (asynchronous) operation. The oevice mav b attached to the
system but in the um wey as a 16-6n wio* static RAM. A emgie 16 x 16 mufTJDly and reed 33-bn result reouiret 5 cvciet
' (wnxa X, writ* Y#-multiplyV7eed >idfvorder Twuit'V**^ low-order reauft). 'Pipelined multipiy/eccumulm operations require
only 3 cvqb ~VT TT'' " _* -T '-V ...J.l.. .... ..... ... ..
' FEATURES
--- - -i-.vc
3* Pin Pecxege
300 mil Ceramic "Skinny DIP"
- 600 mil Pianie DIP I
*0 bit Accumulator -~r.v-
Add Product to Accumulator ; V
. Suotract Prpouet from Accumulator .
Cycle Time 190 ru (typ) ,m -~r

:+ ' "Low Power CMOS
. lOO^V Sundbv (max)
v u*. T ** tJOmA Ooeratinc (max) *
Singie-B'Voit 10% Supoiy
- -L. Puliy Static Operation No Clock Reouireb
. . 3-natt Bui Compatible Gutters
P FUNCTIONAL BLOCK DIAGRAM
! AC A2 Aooren Inpup j
! DC-DU Dau inouo/OurpuU j
j w t J Cnic S'ec: |
i WE Write enable i
Q O > SV ICflk j
1 Sucoiv Voitaoe !
Soecificationi are subiect to
Change witnout notice.


iVJV:
CR45CM
£T.AB SPLUTEMAXIMUMtRAT1 n gs
~t-SuOCXv Voraq*. Voo--- ;;,. -.'TV ~j
** -j ~ r*1'. .... . . . -2,.-
,_^vort9* on Any pm rinc -1 -i. i Trl- T*.
'"to to v0c*civ **
Z^. . ..- -> >V -T^T*.^W s.u ?i-A.
: *^tor9 t*moru/ft.y.%7 . 55"C 15C"C '
'Scrmn oov% "apiotinj maximum rtunot** may rtnjrr
in OamaQc to tnt Oevic*. Functional opacaoon of Oivch
at tft* *'aD%Oii/te mAjtimum raunpi" or aDov# tt> raconv
manoed oo* ration condition* rtipulatad aitawnart in trm
oacificjtion it not imcNwti.. -........ t
ryp*cal limiu art 5.0V, 7A 2S*C; Typical parameter! are not guarantee
* CAPACITANCE ta irc.f-1 mh:
Svmoo* Prtmtr Conomon Mm. Tvo. Max. Unip
Cik Input caoacitanc* All ptm except D>n 5 j os
Input/OutDUt capacitance 00?' ten are tieC to a o
prpunc




.-------*-*. . *r~ ^.t V ^ V T- ->. - ^ \ V. -;-:> ~- > v ..., :- .?- -v
NCR45CM16
.vv'* Aj A; 1 A, *' '*?* OPERATION '* -
X 0 . 0 " o - .'"Raad bit* 0 TTirou^ 15 of majlT Trom accumulator .. .
*' V; X o D ' 1 ' ' "Raad bio 16 Trtroupr 31 Of muh from acnjmuiarror .
X 0 1 X ' R*aO bro 32 tnroutr A7 of mult* from accumulator
r ..? ;

* -L- '*
v :.y:* Wis--. v
*'* *< r.r
*


/ **: "if m / ;i£fiDIVIOE BY 2 AND READ (We 1) '.
Aj A; Ai AO ' -.:: :;r : u'-' operation
X | 1 0 0 fiaed bits 1 OTrouor, 16 of mult from accumulator
X | 1 0 4 Read bio 17 tnrou^. 32 of reuult trom accumulator
X | 1 , X Read biO 23 through A£ of result from accumulator*
X Don't cart zr'v/C-** *.Ti... -
*NOT£: Accumulator accumulate* to AO bin. Thu* bio 0 39 art valid, whiia bio AC AS are a ipn extennon of bit 39.
- -V w : -"* .. .: TT?-sw.V:.-A* xrrr *.r\v.*? -. ., *.c-.............................
r,'.' WRITE OPERATIONS fWI Ol .' '
a3 1 a3 ACCUMULATOR OPERATION A ! Ac MULTIPLIER OPERATION
I o i o Ciaar J .. - . 0 1 0 NO0 fi.ti.n X nC v
I o i i AOd X Y to A 0 ! 1 Writ* r**w OaU tc Y
I 1 1 0 NOp 1 i c Writ* new oau to X
1 I 1 Subtract X Y from A 1 I i Writ* n*w oati to doth X anc Y |
-fV . -

* ..* *
A - Accumulator r- -i: ^ . . ....
X - Data latsrtec into X- Y - DatxjrcaC into Y-ra^rtaf y.* .'.i
*
- .
.... . .

'





NCR45CM16 ____________
'EXAMPLE OPERATIONS /S', "

. .11.v-.-V
Oparvtron
' 1 Moltiwy two l$^*t r*xno*a, rw^ C26*t r^aott
r^V^jAVjT;
bC' L-oooi ZZ£7iZ5*Z£Jc:a '.^TS.?CJ.-~
...0100 , v'.i:\o ,; -
..il'T- oooo -\ ;.:Vi.;:;;.,
oooi-v:y^uVr::;v ''C-. ~ -i v ...^
2.*' Multiply two 1S-t>it numbvn and ccumulrta, rD*at frva times (fiat point digital filter), raad AO*bn rasult Y^
-;x2y: *_x3y: t.>UYf XflY,
. lr\*tn*ct>on \£[\ T."WE _v*'.
Ciaar A, Wno X
Z**f A. Writ* Y \
. Aad XYidA '
Raad low oroar result
Raad httfft roar result
Operrocm

Claar A. Writi X^
* Claaf A. Wrra Y1 *
A X, Y*. Writs X3
Writi Y3 *.'v
;A-X, -Y,
Writ* Yj
A X. Y,
Writ* Y<
A X, -Y,
' Writ. Ys
Xj Yj, Wriu Xj .
X- Y; Xj Yj. Writ. X.
* Xj Y: Xj Yj X* Y*. Wrat X6
'--A X, Y. + X; Y: X: Y3 X. Y< X6 Y6
"RexS mor. ii^nificjm bio (32-47) of mult
-Rxf bro 16-31 of murt 1 ""
RaxJ bn 0-15 of mult ... -
*' i *
'1-i' 2. Half of juiti of souar** % {B* B-2) -v. ^....
. v - inrcructjofi 2 ** *--.r *** Oparvoon
/. - 0011..'- _... o -- - Ciaar A. Writs to Ra^rnaa X ar>d Y
-* '** cm A B Writs 5j to fiaflinan X ar>d Y
* oi re v _~v_ o .. 'V '* a-b.:*5::
. .. -- Old ~ .. 1Til-. -. DiviOs A Dv 2 and raad mon tignlficADt
' 4. Seals sertei of nomewn &v conrunt ~ * ~A*' -
innructxxi *:.. we :' ; "V.* ,'T 'i.-. Opr*rioo

- 0001 ',- ^ v.-v;y o * Claa' A. Write Connan? to Y
1010 ' o 'i. NOP A, vsrm X,
0100 ,, .... : A X, Y
. 0001 .*" i Rsad oroar rvsjlt
0000 Raad K>w orotr rauit
0010 .0 Clear A. Writs Xj
r V-' 0100 ' 0 A X; Y -
'It.-.:-'- 0001 - Read hiph orOer result
!* ' 0000 ........ y Read lew OfOer rmajn
0010 . : : ; o .:. Clear A. writs X3
0100 ' : 0 A X3 Y
.:Z.'T'* 0001 . : 1 ~ Read hipri oroer rtJft
oooo a Read tow orOar r*ult
Y -- K -jur'yy.'- - T. ~
. ... . ... . p......... .... ... ....... -
. ^ / . '.t . *
... ...
r



NCR45CM16 /:*-
T.'"-~: AC CHARACTERISTICS rvoc'-^i re E-5v,ta ore 7trc. v^-o^, v, 3.ov ''
V^READcrcLE'?;-r=-r?^S£?i^^^^^^-- ---'- ~ *--~-"'"" '
. rf -iC -
NCR *50*16

n;_Cya. tt* .. ::w.r.~r-.^zrrTyr-'''- j->-220 >'T' . ns
_ Kaartn too Tm : 120 - ns
rChip Select Output 0O Valid T*Y;T?* V'T** T/w*'--.IT - 70 ni
Wrrta Enable Set Uo Baton Saiact -..-c .... >*.r C=-'.--=-. ns
Read Recovery Time ^ ~ ns
Omo Deselect to Oonx/t HipvZ 50 m
"Data Hold from Read Time 0 ns
.^READ CYCLE TIMING WAVEFORMS ':t.\.::T. -t^ f;;v :y; -.. -:
read operation h pertormed with Wc high. Tha falling eoge of latcnex The addrro and initiates the raaC pi
ADDRESS

ft. #/
ADDRESS VAXIO
^ZXZI
1*C-
Jpgg& ^&V///////A. : -ims
|
' J I
* I *
____I-------
:>l ***'

T
-kWW
icxr1

Si;,::..<2^
rf?r
l!? WRITE CYCLE
"To*l
'\ data valjot
HU?
JT** ,wy 5:--jVT'v T *<: i T. T'*T"Tt ' 1 NCR AS CM 16
LT.l ' SYMBOL ': parameter Min. Mia. Umo
T~~ HVC - Wrrta Cvcl* Tm '. ........uL-.L.*.. .... :2o
- USA. art * "AdOreu Valid to End of Writ* **'*.r\ 170
**" ......
.*.'1' Twts _ Wrrra Enapie Sat Up Baton S'ct V.'. - o-. . .. ns
WR - Writa Recovery Tut*.. - 15 '. ns
... we* 1 Writ* Ruise Width * ' 120 m
ow r: Data Set Up Writ! Time ."V^V ; *' v:" 70 ns
*-v k)H "Data Hold From Writ# Time \ w.*.*v r.... . T'" 30 ns
*Wr Writ* Enaoie to OutpoT Ki*Z * C 5C ns
WRITE CYCLE TIMING WAVEFORMS
The writ* operation is performed with low. The tilling eoge of £2T latches the aoflren anc the rising eoce of latches
ciu m.
Data UNDrc,H£D

CATAolIT


;v --v


\'C3 CcrDorauon
Microcectroriics fon Coinns
2001 Oant.eic Coun
ron Coinns. Coioraoo 8CS25 2998
ERRATA
NCR4 5CX16 SINGLE PORT MULTIPLIER DATA SHEET
The V?.ITE OPERATIONS" cable on page 3 of the data sheec iaplles
cnac data can be written to the Y register wnile siaulcaneously
adding or subtracting the previous XV procuct into the accuaula-
tor. This CANNOT be done Ir. all cases. The following table
replaces the WRITE OPERATIONS table at the boctoe of page 3. Note
that op-codes 0101 and 1101 are invalid-
WRITE OPERATIONS (WE-0)
I ^ * a: Al AO Operation ! a;. A? A1 AO Operation
p' 0 0 0 Clear Aceuaulacor Retain X and V 1 0 0 0 Retain Aceuaulacor Retain X and Y (NOP)
0 0 0 X Clear Accucuiacor 1 0 0 1 Retain Accuaulator'
Write new cata to Y Write new data .cc Y
0 0 i 0 Clear Aceuaulacor 1 0 1 0 Retain Accuaui'accr j
Write new data to X Write new data to .X
1 0 0 l Clear Aceuaulacor '1 0 1 A Retain Accuaulator
1 write nev cats cc X and Y Write new data to X anc Y
1 0 l 0 0 Add X V to Aceuaulacor 1 1 0 0 Subtract X Y froa Accua.
Retain X and Y Retain X and Y
0 1 c 1 Invalid Operation 1 0 Invalid Operation
0 1 > 0 Add X Y to Aceuaulacor 1 l 0 1 Subtract X Y froc Accua. j
Write nev data :c X j Write new data to X j
0 1 1 A Add X V :c Aceuaulacor l 1 Subtract X Y froc Accua.
Write new data to X and Y -rite nev data to X anc Y


76
APPENDIX C
Test Results
A copy of the test results collected from three
different test signals, sine wave, square wave and +0.87
VDC is presented here. These results are shown in binary
format, 16 bit at a time.


FIVE r!FrZ
bite 0 to
bits It to
bits or to
UTS 0 TO
BITS 16 TO
BITS TO TO
BITS 0 TO :
BITE l TO
BITS TO TO
BITS 1? TO :
BITS 16 TO
BITE rr TO
BITS 0 TO 1
BITS i TO
BITS TO TO
r.ZNT CALCULATIONS Z~ C<01 FOR *i vOL*1, DC AUTO COP.RE
2 0 Dr THE RESULT
Zi OF THE RESULT
A7 OF THE RESULT
.5 OF THE RESULT
T: of the result
AZ OF THE RESULT
S OF THE RESULT
El OF THE RESULT
AZ OF THE RESULT
Z OF the result
Z: Or THE RESULT
-5? OF THE RESULT
Z OF THE RESULT
M Or THE RESULT
; OF THE result
0 2 00 1 000!? 101 1010
000001 000000!? 101
0000000000000000
0010110100101101
0000100000001000
0000000000000000
0000100001011100
0000011000000111
0000000000000000
0110100001101100
0000100000001000
0000000000000000
0000010000001100
0000001000000010
0000000000000000


r:vc 2irrzr-&>f c.^llulr. Dr c(o> pop s;ns llve *.ro ootrelation
PITS & TO :E OP the result S'lrz is to :.: op the result PITS 70 TO S? OP the result J l ] Ml ] 00^00 j i j i j <;; £>#
SITE 0 TO 15 OR THE RESULT SITE 16 TO 01 OR THE RESULT BITE 00 TO *7 OF THE RESULT 01 J00001 PI 1PPPP 2 MHMWfi'Pl 2 2 1 IftW 0000000000000000
SITE 0 TO 15 OR THE RESULT BITS lfc TO 01 DR THE RESULT BITE 00 TO *7 OR THE RESULT 00 2 PPPPP 1 P11 0001 000001 i: u iPPi u pppi^ppppppppppi^p
BITS 0 TO 15 OR THE RESULT BITS 16 TO 01 OR THE RESULT BITS 00 TO ? OR THE RESULT 01100000 11101 00 1 0000000011110000 0000000000000000
BITE 0 TO 15 Or THE RESULT BITE 16 TO 01 OR THE RESULT BITS 00 TO *7 OR THE RESULT ppipipppipinipp 0000000012101000 0000000000000000


n* r*
r:v£ ?!'i~?Zr.z. .7
rTTi TO IZ CP *THt RESULT
riTS : TC 7 2 C,c THE RESULT
sits rr TC- 4? OP THE RESULT
sits 0 to :r or the result
ElTE lc TO *2 OP THE RESULT
lITS rr TO 47 OPTHE RESULT
SITE 0 TO IS OP THE RESULT
SITS i TO Cl CP the result
sits :: TO 4? OP the result
SITS 0 TO IS OP THE result
SITS 16 TO Cl OP the RESULT
sits rr to 4? op the result
ITS e TO 15 OP the RESULT
ITS 16 to Cl OP the result
its rr to 4? op the result
op city pc= square alr
12£; 2 i fi*
2: i: l ii£t);:::: 11
02 000000011002 00
0000100100002 001
0000000000000000
100000001 2 001
00001000:11:1111
0000000000000000
00000100000Z:2 00
00001000 2 112 101*1?
0000000000000000
10001010110Z1110
00000001000 2 0001
0000000000000000