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- Permanent Link:
- http://digital.auraria.edu/AA00002033/00001
## Material Information- Title:
- Non-linear phase locked loop design and verification
- Creator:
- Spurr, Robert Nelson
- Publication Date:
- 1995
- Language:
- English
- Physical Description:
- vi, 76 leaves : illustrations ; 29 cm
## Subjects- Subjects / Keywords:
- Phase-locked loops ( lcsh )
Nonlinear control theory ( lcsh ) Nonlinear control theory ( fast ) Phase-locked loops ( fast ) - Genre:
- bibliography ( marcgt )
theses ( marcgt ) non-fiction ( marcgt )
## Notes- Bibliography:
- Includes bibliographical references (leaf 76).
- General Note:
- Submitted in partial fulfillment of the requirements for the degree, Master of Science, Electrical Engineering.
- General Note:
- Department of Electrical Engineering
- Statement of Responsibility:
- by Robert Nelson Spurr.
## Record Information- Source Institution:
- University of Colorado Denver
- Holding Location:
- Auraria Library
- Rights Management:
- All applicable rights reserved by the source institution and holding location.
- Resource Identifier:
- 34034606 ( OCLC )
ocm34034606 - Classification:
- LD1190.E54 1995m .S68 ( lcc )
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NON-LINEAR PHASE LOCKED LOOP DESIGN AND VERIFICATION by Robert Nelson Spurr B.S., University of Colorado, 1977 M.S., University of Colorado at Denver, 1995 A thesis submitted to the Faculty of the Graduate School of the University of Colorado at Denver in partial fulfillment of the requirements for the degree of Master of Science Electrical Engineering 1995 This thesis for Master of Science degree by Robert Nelson Spurr has been approved Hamid Fardi Spurr, Robert Nelson (M.S. Electrical Engineering) Non-Linear Phase Locked Loop Design and Verification Thesis directed by Professor Miloje Radenkovic ABSTRACT A simple Phase Locked Loop (PLL) example was used to develop a model which can be simulated with non-linear components, in particular, a non-linear phase detector with linear control loop and Voltage Controlled Oscillator (VCO). Variable loop bandwidth which was dependent on input signal amplitude was demonstrated. An attempt was made to estimate internal control loop parameters using a recursive least squares estimation algorithm. The method described is applicable to other types of control systems containing non-linear elements. An actual example based on a helical data recorder is included to show the types of input signals which were present in the analog to digital conversion of the data detection process. A clock signal was extracted from these signals using a non-linear PLL. This abstract accurately represents the content of the candidates thesis. I recommend its publication. Signed Miloje Radenkovic CONTENTS Chapter 1. Analyzing specialized control systeme with non-linear components.................1 1.1 Introduction....................................................................1 1.1.1 Thesis objectives..............................................................2 1.2 Classical PLL design............................................................2 1.2.1 Types of PLLs.................................................................3 1.2.2 Translation between frequency and phase.......................................4 1.2.3 Analysis of a type-2 PLL with an integrator...................................4 1.2.4 Third order PLL with an integrator............................................6 1.2.5 Conclusion.....................................................................8 1.3 Continuous and sampled time third order PLLs....................................9 1.3.1 Whole system model............................................................10 1.3.2 Simulation in parts model.....................................................12 1.3.3 System equivalence............................................................14 1.3.4 Conclusion....................................................................18 1.4 Adding non-inear elements.....................................................19 1.4.1 Step response.................................................................23 1.4.2 Noise response................................................................24 IV 1.4.3 Pulse response..............................................................27 1.4.4 Bandwidth approximation method..............................................28 1.4.5 Conclusion..................................................................29 1.5 Parameter estimation of systems with non-linear components.................30 1.5.1 Noise cancellation review...................................................30 1.5.2 Estimating parameters in non-linear control systems.........................33 1.5.3 Application to the non-linear PLL example...................................34 1.5.4 Input stimulus..............................................................37 1.5.5 Simulation results..........................................................37 1.5.6 Possible reasons for non-convergence of parameters..........................41 1.5.7 Conclusion..................................................................42 2. Application to a high density helical digital tape recorder...................43 2.1 Helical recording............................................................43 2.2 Description of helical recording.............................................44 2.2.1 Machine basics..............................................................44 2.2.2 Recording format.......................................................... 45 2.2.3 Electro-mechanical system model.............................................48 2.2.4 Data synchronizer...........................................................49 2.3 Identification of the synchronization process...............................51 2.3.1 Time base error (TBE) and jitter...........................................53 v 2.3.2 Frequency domain analysis..................................................53 2.3.3 Time domain analysis.......................................................55 2.3.4 Tracking errors............................................................57 2.3.5 Rotary transformer frequency response......................................58 2.3.6 Equalization magnitude and phase response..................................60 2.4 Conclusion....................................................................62 3. Future dirrection..............................................................63 4. Simulation listings...........................................................64 Glossary..........................................................................75 Bibliography......................................................................76 vi 1. Analyzing specialized control systeme with non-linear components 1.1 Introduction Previous engineering problems associated with the detection of analog data recorded on helical tape recorders have promoted an interest in designing better data recovery circuitry. An important part of the data recovery circuitry and part of the detection problem was the Phase Locked Loop (PLL) which regenerates the clock of Non Return to Zero (NRZ) recorded data. Basic PLL technology has been in existence for many years, and is still widely used in many modem analog and digital applications. Since the theory of the analog PLL is well developed in literature, only a brief description of the basic concept was presented. This thesis will add to the basic PLL technology by adding a nonlinear phase detector to the basic PLL structure, and analyze the effect of this change. Least squares parameter estimation methodology was applied to the nonlinear PLL example to automatically determine control parameters for a specific class of input signals. Inserting non-linear components to an otherwise linear control system adds an interesting twist to the usual analysis methods. Since superposition as defined in linear control systems no longer applies to a non-linear system when signals of large dynamic range were applied, an alternative simulation method was proposed to determine desirable control parameters. Basic theory and results derived from linear and non-linear PLL examples were provided. Part 2 provides an example of how non-linear methods of PLL control have application to the field of high density helical tape recorders. l 1.1.1 Thesis objectives - To briefly review existing PLL technology. - Starting with a continuous time PLL control system, develop the sampled time equivalent system. - Verify the equivalent sampled time PLL model. - Propose a method for simulating control systems with non-linear components. - Separate the linear sampled time equivalent control system into parts, and compare simulation results to previous simulations. - Add a non-linear phase detector to the system simulated in parts and re-simulate. - Show advantages and disadvantages of PLLs with non-linear phase detectors. - Discuss classical methods of determining performance of PLLs with non-linear phase detectors. - Propose the use of parameter estimation as a tool for determining control system parameters for non-linear control systems. - Apply this method to a simple PLL example. - Provide a practical example of the use of non-linear control methods for a data separator in a high density helical tape recorder. 1.2 Classical PLL design The basic PLL, shown in Figure 1.1, contains a phase detector, a loop filter, a Voltage Controlled Oscillator (VCO), and a feed back divider. The input was a frequency source which was applied to the phase detector. The output was a VCO which was controlled by the loop filter. The phase of the VCO output was compared to the phase of the reference signal in the phase detector, and the error signal was applied to the loop filter. The loop filter controlled the performance characteristics of the PLL. 2 Reference Input Figure 1.1 Basic PLL block diagram Historically, PLLs have been designed from classical second order control system models. The characterization of these models have been improved by using third order models to compensate for one additional pole in the VCO circuitry. Further model improvements have been made for digital PLL by adding a sample and hold to more accurately model the effect of a sampling phase detector. 1.2.1 Types of PLLs PLLs can be classified by their ability to track step, ramp, and parabolic input signals. The following three classifications were commonly used: Type-0: Follows a step frequency input with constant frequency error. Will not follow a ramp or parabolic frequency inputs. This type was really frequency locked loop. Type-1: Follows a step frequency input with zero error, follows a ramp frequency input with constant error. Will not follow a parabolic frequency input. Type-2: Follows both a step and ramp frequency input with zero error, and follows a parabolic frequency input with constant error. In the remainder of this thesis the type-2 PLL was considered because of its ability to track a step phase change with diminishing phase error. This feature was ideal for data recovery in a digital tape recorder. 1.2.2 Translation between frequency and phase PLLs were very similar to other control systems with the exception of the generation of the loop error signal. PLLs perform an analog subtraction of the phase of the input frequency from the phase of the output frequency. Since frequency is the derivative of phase, calculations at the phase detector must use the integral of the frequency. This was why the VCO was modeled as an integrated gain function, and the PLL input was defined in terms of phase. Using this frequency to phase translation, a type-2 PLL will follow a step phase input with zero error, a ramp phase input with constant error, and will not track a parabolic phase input change. 1.2.3 Analysis of a type-2 PLL with an integrator Figure 1.2 shows the control system diagram for a second order PLL with a perfect integrator. The reference signal input (jV was defined in terms of phase, the phase detector subtracts the reference phase from the VCO phase (j)f' to produce the loop error 'Â£'. The loop filter contains an integrator with a single zero at frequency 'a' radians per second. The Voltage Controlled Oscillator (VCO) input was defined in terms of frequency and the output signal'(])/ was defined in terms of phase. To make the modeling translation of frequency to phase, an integrator' 1/s' was used in the VCO block. The loop gain constant was combined in the VCO block by 'k,,,' and 'kvco'- Actually \ was the phase detector gain, and usually the loop filter has an attenuation factor which can be adjusted to compensate for the fixed gains of the phase detector and the VCO. a Phase Detector Loop Filter Voltage Controlled Oscillator Reference Input Figure 1.2 Basic Second order PLL with integrator The transfer function of this loop can be calculated as follows: Equation 1 T(s) = G(s) 1 + G(s) N kit, (s+a) kvco 1 s s 1 + JlL (s+a) N s kyco s T(s) = k 2 kvco k^kycO_^ N N Similar to all second order systems, the response was governed by the natural frequency CO and the damping factor 8. Equation 2 q) /k^kyco a n N P 6 CD k,|,kvco 8 _L / k n N 2 N N a 5 By rearranging the loop components, a transfer function at the phase detector output can be obtained. Using the final value theorem with a step phase input (a ramp frequency function) the steady state error can be found. Equation 3 lim s r s2 i 1 sN S-0 _2 kct>kVCO kdikVCO a L N N J s2 k(|>kVCO a This means that theoretically a second order PLL with an integrator will track a step phase input change with no output error. In practical PLLs, perfect integrators can not be achieved because amplifiers with infinite gain were not realizable. The phase error due to this practical consideration is usually far to small to be seen, and phase errors were usually dominated by time delays in the circuit components. 1.2.4 Third order PLL with an integrator The type-2 PLL described above was modified to include the effects of a third pole in the VCO which was usually placed just above the desired control system bandwidth. Some YCO have a limit on the rate of frequency change due to their design. Often the VCO performance was intentionally reduced by adding a rate of frequency change limit because it has the effect of filtering out spurious noise signals which were outside the PLL control loop bandwidth. This feature was added to Figure 1.3 with the (s+b) term in the VCO block. Phase Detector Loop Filter Voltage Controlled Oscillator Reference Input Figure 1.3 Third order PLL 6 Transfer function of the third order PLL: Equation 4 T(s) = G(s) 1 + G(s) N k||) s+a kvco 1 s s (s+b) . k|> s+a kyco N s s (s+b) T(S) = k(|> kyco (s+a) s3+bs2+ k^kvcs +k^--v-c-- N N Frequency response: Equation 5 T(s) = kif kyco (s+a) 33+bs2+MMs + Wol N N S = JC0 T(jco) = k(j> kyco (a+jco) - ini3 h2 +j kvco + kf kvco a N N Using the following performance parameters, Equation 6 Given: a = 0.1 *6.28 b = 100 *6.28 k = k N = 1 the following simulation diagram can be obtained. 7 Figure 1.4 Continuous time implementation of the third order PLL 1.2.5 Conclusion The above third order continuous time PLL model serves as a starting point for the design of the PLL with a non linear phase detector. Thorough characterization of this system will set a performance reference to which changes in the system can be compared. Following analysis and simulations replace the linear phase detector with a nonlinear phase detector. Before these changes could be made, however, the following issues were first addressed: 1) Practical control parameter values were need to allow for frequency response and transient response simulations. A loop bandwidth of 10 Hz was chosen for convenience. Actually, data recovery systems use much wider band width. The results presented were independent of the actual bandwidth because the design can be scaled to any frequency. 2) A sampling phase detector was added because our application uses a phase detector which was built out of digital components and because discrete time simulations require a sampled data input. Analog phase detectors were some- times used in this application, but they have the disadvantage of lower noise immunity. The frequency response of the continuous time and sampled time systems were compared to insure that the sampled time system was nearly equivalent to the continuous time systems. 3 3) Adding a nonlinear phase detector requires a different modeling approach. In general, linear system properties such as superposition no longer apply to non- linear systems. Because of this difficulty, the third order PLL with a sampling phase detector was simulated in parts. The performance of the system simulated 8 in parts needs to be verified against the original system to insure equivalence. To do this, the system with the linear sampled phase detector was separated into parts and simulated. The results were compared to the nearly equivalent system which was simulated as a whole. Once equivalence was obtained, the linear phase detector was replaced with the nonlinear phase detector and the system were simulated again. 4) Parameter estimation was tried to automatically determine controller parameters. Nonlinear components provide different characteristics at different signal amplitudes. Stimulating the system with a "typically good" input signal levels provides one set of results. Stimulating the system with a "typically bad" input signal level provides another set of results which may not be related in magnitude to the "typically good" input signal levels. To determine optimum system parameters, a "typically good" input signal was applied to the system and control parameters were automatically generated which minimize the least squared error as compared to the desired system result. "Typically bad" input signal levels were then applied to verify the effect of the non linear element. 1.3 Continuous and sampled time third order PLLs The intent was to use a pure sampled data system for PLL simulation because parts of a digital PLL were implemented using discrete time components and simulations were in general faster and easier in the discrete time domain. The design requirement, however, was based on an analog requirements which was recovering the clock of digital data recorded and reproduced with a mechanical interface. Frequency response analysis was intended to show that the continuous time (analog) and sampled time implementations have approximately the same amplitude performance. The second complexity was separating both the analog and sampled time systems into parts to be simulated with separate lines of code which were subsequently combined to form the completed control system. Justification was necessary to prove that after the system was separated into parts, it was roughly equivalent to the original system. The designations "Whole System" and "Simulated in Parts" were used to distinguish between the different methods which ultimately achieve the same result. o 1.3.1 Whole system model The "Whole System" designation refers to the system which was simulated as a single mathematical equation as shown in Figure 1.5. This was a common simulation method for linear systems because for linear systems the effects of individual system components can be combined into a single easy to solve equation. Systems with non- linear components can not be reduced in this way. Phase Detector Sample/Hold Loop Filter Voltage Controlled Oscillator Reference Input Figure 1.5 Sampled time block diagram of third order PLL The transfer function of Figure 1.5 was derived by taking the ^ transform of the forward path, and using the feed back control equation, Equation 7, to close the loop. Equation 7 G(s) = - T(z) = -sT e s+a k,j, kVco s s s (s+b) z) . Q T (s+a) k0 kVC0 L s3 (s+b) G(z) 1 + G(z) N The frequency response for this model can be derived as follows: 10 Equation 8 T(s) = G(s) 1 + G(s) N T(s) = kfr 1-6 s+a kyQQ 1 T s s s (s+b) 1 + k 1 ~ e'sT s+a kvc0 NTs s s (s+b) T(s) = [(1 esT)s + (1 esT)a] k<|> kvco ls4+ Tbs3 +hhÂ£ (1 e'sT)S + k^kvco (1. esT)a N N s = jco TGco) = jtok [l cos(Tco) + j sin(T Equation 9 Given: a = 0.1 *6.28 b = 100 *6.28 k = k^ k^QQ = 36000 T = 0.001 N = 1 , t 0.0997q'1 0.1728q2 + 0.0731 q'3 T(cl)= ------------;---------:---------r- 1 2.433 q'1 + 1.894 q'2 -0.460 q3 The simulation diagram was shown in terms of the delay operator 'q'1' which was the unit time delay T. 11 Figure 1.6 Discrete time implementation of third order PLL 1.3.2 Simulation in parts model The "Simulated in Parts" designation was used to show results of an equivalent system in which the individual system components were simulated separately, and the simulation results were combined to form an equivalent control system. This ap- proach is necessary when some of the system components were non linear. Figure 1.5 was used again as the system diagram, but the ^ transforms of the loop filter and VCO were computed separately. Later this will allow the insertion of a nonlinear phase detector, and the computation of only the loop filter parameters without changing the constant VCO parameters. The loop filter can be described as: Equation 10 . -sT Gi(s)=-^- G1(z) = 1'z'1^ s+a s s+a G,(q) k+ k(aT-1)q1 1 -q'1 \r The voltage controlled oscillator can be described as: Equation 11 G2(s) = k s (s+b) k<|> kyco s (s+b) . G2(q) = 1 e -bT . .. -bT. -1 -bT -2 1 (1 e )q + e q System model: Phase Detector Loop Filter Voltage Controlled Oscillator Reference Input Figure 1.7 Third order PLL simulated in parts Given values: Equation 12 Adding values to the to the design variables. Given: a = 0.1 *6.28 T,(q) = 36000-35773 q b = 100 *6.28 1 -q1 k = ki|) kvCO = 36000 T = 0.001 T2(q) = 7.43e-4 q'1 N = 1 1 1.53q1 +0.53q'2 Simulation Diagram: 13 The simulation diagram shown in Figure 1.6 was used as the linear "Reference" system to be compared to the results obtained by simulating the system shown in Figure 1.8. The system shown in Figure 1.8 was first simulated with a linear phase detector to prove equivalence to the system shown in Figure 1.6. The next step was to simulate Figure 1.8 with a nonlinear phase detector and show its performance with various classes of input signals. Finally, the system model shown in Figure 1.8 was simulated in conjunction with least squares parameter estimation to estimate good control parameters for a given class of input signals. 1.3.3 System equivalence Since the system simulated as a "whole system" (Figure 1.6) and the system simulated in parts (Figure 1.8) were based on the continuous time model shown in Figure 1.9, they should have similar characteristics. System similarity was done in the following two steps: Continuous time Vs sampled time models First, the frequency response of the linear continuous time system shown in Figure 1.3 was compared to the linear sampled time version of the same PLL shown in Figure 1.5. Figure 1.9 shows that the two systems were nearly equivalent at frequencies below 100 Hz. Since the -3dB bandwidth was set to 10 Hz, this plot shows very good similarity. There were some differences between the two systems at frequencies above 100 Hz. These differences were due to the sampled phase detector used in the system described in Figure 1.5. As one would expect, there was a response null for the sampled time system at 1000 Hz because the sample time 'T' was 0.001 second. 14 Figure 1.9 Frequency response comparison between continuous time and sampled time PLLs Figure 1.10 shows the step response of linear continuous time system shown in Figure 1.3 as compared to the step response of the sampled time PLL shown in Figure 1.5. Again the linear continuous time system and the linear sampled time system looked nearly identical. Continuous Time PLL Step Response Time (Seconds) Continuous Time Sampled Time Figure 1.10 Step response comparison between continuous time and discrete time PLLs "Whole system" VS system "simulated in parts" models The second test for similarity compared the step response of sampled time system shown in Figure 1.6 which was the "whole system" simulation to the same system shown in Figure 1.8 which was "simulated in parts". Figure 1.11 shows the simulation results were similar, but not identical. Modeling errors associated with breaking the system apart caused the transient response to take slightly different trajectories. Also the steady state response was slightly different. The system "simulated in parts" had unity feedback which was absolutely set by the feed back path to the phase detector as shown in Figure 1.8. This forces the DC gain to be exactly 1.0. The system simulated as a "whole system" also has a gain of 1.0, but the gain was numerically set by the accuracy of the system zeros. Model round off errors and small simulation numerical errors will cause a small gain difference. This fact was important later. 16 Sampled Time PLL Step Response 0 0.02 0.04 0.06 0.08 0.1 Time (Seconds) Whole System - Simulated In Parts Figure 1.11 Differences in step response between sampled time PLL simulated as a whole system and simulated in parts Noise response Figure 1.12 shows the Gaussian noise response of the system simulated as a "whole system" and the system simulated in parts. The trend was similar, but the system "simulated in parts" did not respond to the noise as much as the system simulated as a "whole system". Later, we will see that this effect will cause difficulty in estimating equivalent parameters for the controller. 17 Sampled Time PLL Noise Response Time (Seconds) Whole System Simulated in parts Figure 1.12 Differences in noise response between a sampled time PLL simulated as a whole system and simulated in parts 1.3.4 Conclusion The system simulated as a "Whole System" and the nearly equivalent system simulated as a "Simulated in Parts" system had some notable differences. The high frequency response of the sampled data system did not have a high degree of correlation between the two systems. For a real system which was built with specialized components connected together to form the "Simulated in Parts" system, an equivalent "whole system" model may become very complex or not possible. In many cases, complicating the "whole system" to represent the "simulated in parts system adds complexity to the design process without significant benefit. In general, a design specification should be as simple as possible. IK Examples of small differences between different system topologies were fractional time delays, numerical limitations, amplifier offsets, band width limitations, and noise. For the purpose of this thesis it was better that the system simulated as a "whole system" and the system "simulated in parts" have the same trend, but have small differences in transient and noise response because a physical implementation of a system usually will not totally agree with the model. 1.4 Adding non-inear elements The linear phase detector can be converted mathematically to a nonlinear phase detector by making the phase detector output a special function of the input phase difference. The simplest method was to use the mathematical SIGN function which converts a number greater than or equal to 0 to a +1 in value, and numbers less than 0 were converted to a -1. A zero output for a zero input was not allowed in this conversion. The actual gain of the phase detector was modified by multiplying the +1 and -1 numerical SIGN output by k which established the phase detectors gain. The SIGN method has the characteristic of making the phase detector output a constant positive or negative value for any input difference. This means that its effective gain was variable. It was dependent on the input phase error, and in a control system, the loop gain will also be variable. Variable loop gain will cause change in system bandwidth. Hence a SIGN type phase detector will produce a PLL which will respond quickly to small input phase errors due to its high gain for small phase error inputs, and will tend to reject large phase error inputs. This system, however, has the tendency to drift or "hunt" when the input phase detection rate approaches the control system bandwidth. We will call this system a non-linear type-1 phase detector. A type-0 phase detector was defined as the common linear phase detector as described in previous sections. Figure 1.13 shows a practical implementation of a non-linear type-1 phase detector. IQ 180 degree Type-1 Loop Filter Voltage Signal Non-linear Pole @ co=0 Controlled Splitter Phase Detector Zero @ co=a Oscillator Other nonlinear phase detectors can also be devised. For example, instead of a constant positive or negative level output level for any phase error, one could devise a system which provides a SIGN magnitude output pulse for every transition. The phase detector output error would then return to zero in a specified time after every phase detection. Similar to the previous SIGN system, this system has variable gain dependent on input phase error, but would not "hunt" as much when the input phase detection rate approaches the control system bandwidth.. This system also has variable gain dependent on the frequency and the magnitude of the input phase error. This system is defined as a non-linear type-2 phase detector. Figure 1.14 shows a practical implementation of a non-linear type-2 phase detector. Type 2 Non-linear Phase Detector Input Data Set D Q One >CK Q 3 Shot Rst pu A. Set D Q >CK Qb T pu vw 3VW One Shot vw-1 3VW From VCO =j= To Loop Filter Figure 1.14 Improved non linear phase detector for missing pulse applications Figure 1.15 shows a graphical output of various phase detectors stimulated with an early and late data transition. The linear phase detector integrates the phase error causing a proportional control error for all input errors. The type-1 phase detector provides a constant large phase correction for all levels of input phase errors. The type-2 phase detector provided variable duty cycle correction depending on the input data transition rate. Higher order phase detectors (Type-3, etc.) could also implemented by creating an exponential phase detector output pulse for every phase detection. Although a circuit diagram was not shown for this type of detector, it could look similar to the phase detector shown in Figure 1.14 with the one shot replaced with exponential decaying circuit. The performance of this phase detector could be better than Type-1, 2 phase detectors for missing pulse phase detection applications because it has a diminishing effect on following phase samples. During data periods having maximum transitions, the type-3 phase detector would provide maximum correction, but during infrequent data phase detections, that is during the period before the next data transition, this detector would provide diminishing phase correction. ^1 Input Data Transitions Early Data Transition Late Data Transition The type-2 phase detector is probably the best compromise between ease of implementation and performance. The introduction of nonlinear components into a control system causes simulation difficulties because the control system can not be reduced into a simple formula. Instead, the loop components must be simulated separately. This was why a great degree of effort was devoted in the previous section to show similarity between a "whole system" and the system "simulated in parts". The benefit of nonlinear phase detector was primarily to filter unwanted PLL input signals. Other benefits such as an all digital design, and more predictable phase error and slew characteristics were also provided. The disadvantage was increased phase detector noise at low input levels. These features were illustrated in the following sections. 1.4.1 Step response Figure 1.16 shows a simulation of the step response obtained with a nonlinear phase detector. All other parameters were identical to the previous examples which used a linear phase detector. The nonlinear phase detector caused the system to approach its final value in a predictable linear trajectory. This could be an important advantage for control systems which rely on predictable settling times. An example of such a system would be a disk drive head seek problem where the track to track servo would apply a calculated amount of control to achieve the desired control response. To obtain this response, the phase detector gain must be set appropriately. One could use the step response to calibrate the gain, but in this example, the noise response (to be described next) was used. Step Response Input = 1 unit Step Linear Non-Linear Figure 1.16 Comparison between the step response of linear and non-linear PLL 1.4.2 Noise response Figure 1.17 shows the system response when noise with unity variance was applied. The linear system replicates the noise within its bandwidth, but the nonlinear system actually attenuates the noise extremes. This feature was useful in the PLL problem because noise transients can cause a significant output phase error. The operation of the PLL with the non-linear phase detector was dependent on the combination of the loop gain and the expected input phase variation. Noise Response Input =1.0* Gaussian Noise Linear Non-Linear Figure 1.17 Comparison between the noise response of linear and non-linear PLL The phase detector gain in this example was adjusted such that the linear and nonlinear example would produce approximately the same noise tracking with unity variance Gaussian noise applied. If the expected normal input variance was smaller then the phase detector gain should be larger to compensate. Similarly, if the input variance was larger the phase detector gain should be less. Actually, this gain need not appear in the phase detector, it can be inserted anywhere in the forward control path. Figure 1.18 easily shows the greater noise rejection of the PLL with a non linear phase detector when a Gaussian noise source with a variance of 4 was applied to the 14 input. The reason for the rejection was because the magnitude of the limited phase detector error output was the same as the unity variance case. Noise Response Input = 4 Gaussian Noise Q. 4' o E 0 CO CO Time (Seconds) Linear Non-Linear Figure 1.18 Comparison of output noise dependence on input signal amplitude of linear and non-linear PLL. The non-linear PLL reduces noise under large input noise signal conditions The price to be paid for noise rejection was shown in Figure 1.19. For very low input noise levels, the control system actually amplifies the output phase noise because the phase detector can only output a -i-k or -k error signal. In data detection systems, a noise threshold is usually defined which provides a level of diminishing returns on system performance. In other words, if the PLL provides a constant low level of output noise below a predetermined threshold, it will not significantly affect the data recovery performance because there were other error sources which dominate the system performance. 25 Noise Response Input = 0.5 Gaussian Noise Time (Seconds) Linear Non-Linear Figure 1.19 Comparison of output noise dependence on input signal amplitude of linear and non linear PLL. The non-linear PLL increases output phase noise under low input noise input signal conditions Although this example loop has been optimized for a unity variance Gaussian noise performance, other criteria such as colored noise or transient response could be used. When matching lower frequency content input signals is desirable, adding more noise signal power in the lower frequency area will intensify the response in this frequency band. The fixed phase detector gain k can be re-adjusted for the best tracking. 26 1.4.3 Pulse response Figure 1.20 shows the pulse response for the linear and nonlinear PLL. Since the nonlinear phase detector causes constant error correction rate independent of input magnitude, it does not follow the' transient as quickly as the linear PLL. The step response for the expected input magnitude was nearly equivalent to Figure 1.11 for both PLLs, but the pulse response for larger than expected inputs has been attenuated in the nonlinear case. This result was expected because of the constant rate of phase change characteristic on the control system with the nonlinear phase detector. Pulse Response Input = 5 Unit Pulse Linear Non-Linear Figure 1.20 Comparison between the pulse response of the linear and non-linear PLL For magnetic tape data detection systems, a run up sequence of transitions without user data can be used to lock the PLL at the beginning of the data stream. Lengthening 27 this lock up region can give the non-linear PLL adequate time to lock before data is present. Although mechanics variances causing changes in head to tape speed can be obvious sources of transition timing variance, other significant sources such as code sensitivity, media problems and tracking can also exist. The output phase of the nonlinear PLL will not deviate as much as the linear PLL under these conditions, and therefore will more accurately track the data to be recovered. 1.4.4 Bandwidth approximation method Classical control methods can be applied to the PLL with the nonlinear phase detector by considering effect of phase detectors dependence on the magnitude of the input phase error. The result was a family of frequency response curves shown in Figure 1.21. Notice that large input signal were over damped by the PLL non-linear control system, while very small input signals can cause peaked response or have a tendency of instability. The over damping was caused by the constant magnitude output of the phase detector which in the large signal case was smaller in magnitude than in the linear phase detector case. Similarly, the under damped response was caused by an excess phase detector output. This instability was sometimes observed as a hunting of the output phase. 7ft Non-Linear PLL Frequency Response Dependence on Input Magnitude Frequency (Hz) Input = 0.01 Input = 0.1 Input = 1 s Input =10 * Input = 100 Figure 1.21 Effect of input signal amplitude on the frequency response of a non- linear PLL 1.4.5 Conclusion Substituting a non-linear phase detector for the linear phase detector found in many PLL has the advantage of filtering "out of bounds" input signals. These erroneous signals can be caused from excessive channel noise bursts or when the reproduce head goes off track and intercepts signals from an adjacent track. Sources of such problems were from media damage, mechanical vibration of the drive, splice points of the recorded data, or simply normal tracking variances. A data synchronizer was a good application of this technology because detection Signal to Noise Ratio (SNR) was limited by the head to media interface, and the low level of additional phase noise created as a by product of the nonlinear phase detector was not significant to the data recovery operation as a whole. 7.Q A low phase noise frequency synthesizer, however, would not be an application of this technology because of the residual low level phase noise produced by the non- linear phase detector. The remaining question was how to develop a good control system to be used with the non-linear phase detector operating with various input signals. Linear methods which rely on frequency-phase design methods were no longer applicable when the non- linear phase detector was operated over a large range of input phase errors. Transient response methods can be used, but have the disadvantage of using a very restricted class if input signals and therefore may not yield a worst case design. The next section will propose a method which will automatically determine the appropriate control system for a given input signal. 1.5 Parameter estimation of systems with non-linear components The previous section has shown the operation of a PLL after the linear phase detector was replaced with a non-linear phase detector. The loop filter and the VCO models used in the non-linear phase detector case were identical to the models used in the all linear PLL example. The phase detector gain was adjusted to match the expected input phase deviations. The operation of a system with one or more non-linear component can be highly dependent on the input signal characteristics as well as the internal control system characteristics. Experimental methods can be used to "tweak in" the optimal performance with a given signal, but changing component values and re-running simulations, or bench testing with actual components is time consuming, and in general does not produce a worst case design. 1.5.1 Noise cancellation review The adaptive noise cancellation circuit was a starting point for a system which can automatically calculate the control parameters in a non-linear control system. Since the non-linear control system behaves differently with different input signal levels, the adaptive nature of the noise canceling circuit can be used determine control system parameters which mimic the desired linear control system performance under specified normal signal constraints. The parameters of the non-linear control system were then fixed, and the noise reduction and step response characteristics were tested with significant input deviations. Figure 1.22 shows the noise cancellation circuit. Noise Source Input x(n) Signal S(n) Figure 1.22 Adaptive noise cancellation block diagram The noise canceling circuit applies the noise source to the fixed noise path characteristic model, and at the same time applies the same noise to an adaptive noise path estimator. In practice, the noise path was some physical realizable transfer function which conducts noise into the desired signal. The adaptive noise path estimator attempts to adjust its filter coefficients to electronically match the physical noise path characteristic. Once matched, y(n) is equivalent to interference signal vo(n), and the noise can be subtracted out in the last summer. Initially, the noise path estimator was not calibrated to the actual parameters of the physical noise path. The parameter estimator accomplishes this by measuring the resulting error and adjusting the noise path estimator parameters to minimize this error. Since the noise applied to both the noise path characteristic block and the noise path estimator was the same signal, it was correlated. The parameter estimator 31 actually minimizes this correlated noise leaving the signal which was not correlated with the noise. Equation 13 describes the output of the noise path characteristic when the noise signal, x(n) was applied. Equation 13 vn(n): B(z ) A(z1) x(n) B(z ) = b0+ b,z'1 + +bmz'r A(z1) = 1 +a1z1+ +a, z'n Equation 14 describes the output of the noise path estimator when the noise signal, x(n) was applied. Equation 14 -1 B(z ) y(n) = -7t x(n) = The output of the adaptive filter A(z ) B(z1) = b0(n-1)+ 6,(n-1)z'1f + 6n(n-1)z" A(z1) = 1 +a1(n-1)z'1+ +an(n-1)z'n The transfer function shown in Equation 15 represents the noise path transfer function which in this case was estimated using Recursive Least Squares (RLS) parameter estimation (RLS). Equation 15 B(z1) -xri = The transfer function to be estimated A(z ) The actual mechanics of parameter estimation process can be shown in Equation 16 and Equation 17. These equations were calculated recursively, and will usually converge to reduce the level of the noise. n Equation 16 T eo=[b0 b," -bm a, a,] e(n-1) [60(n-1) B^n-1) 6(n-m) a,(n-1) an(n-l) ] y(n) = 0(n-1) Equation 17 6(n) = 0(n-1) + p(n) |(n) [ d(n) 0(n-1)T^(n)] P(n) = p(n-1) - p(n-1) 1.5.2 Estimating parameters in non-linear control systems The noise canceling circuit diagram, shown in Figure 1.22, was modified in Figure 1.23 to perform automatic parameter estimation of a subsystem within another control system. The problem was simplified by removing the signal source in the noise canceling circuit, but complicated by solving for only the controller part of the transfer function. Linear System Model Figure 1.23 Noise cancellation circuit modified for automatic parameter estimation of a control system with non linear elements Under certain conditions the gain of the estimated path must be variable and was controlled by the Co. In the PLL example discussed next, the gain of the model was close, but not exactly equal to the gain of the control system to be adapted. This small gain difference can cause a residual output error which makes parameter estimation difficult. 1.5.3 Application to the non-linear PLL example An automated method of determining control system parameters for the non-linear PLL example illustrated should be possible using the noise cancellation process described in the previous section. This method is not limited to the simple lag-lead compensater used previously, but instead considers a general class of loop filters containing multiple poles and zeros. Figure 1.24 shows the general architecture of a system which compared the outputs of a linear and non-linear PLL connected to the same signal source. Using a noise source representing the expected input and least ^4 squares parameter estimation, the parameters of only the loop filter in the non-linear PLL were automatically adjusted by the algorithm to produce an output which was similar, in the lease squared sense, to the linear system model. The linear system model was not part of the final design, but serves as performance standard to which system with the non-linear phase detector was to be adjusted. Linear System Model Figure 1.24 Parameter estimator for the non-linear PLL example Notice that the feed back path was set to simply a gain of 1. This was a practical requirement in the PLL example because physical implementation of this path was digital clock signal. Some sort of digital phase compensater could be implemented in this path, but this would unnecessarily complicate the PLL example, and would not be a practical solution. A gain block was added for numerical reasons. The gain of the linear system model was set by the zeros in that model. The gain of the PLL was set by the unity feed back path. Since the system model was calculated with fixed precision, the gain of the two paths will never be exactly equal. This causes a consistent offset error, and the loop parameter estimator falsely tried to adjust other parameters to reduce this error. The variable loop filter can be simplified by adding a fixed integrator. This helps prevent possible convergence instability since the integrator pole was calculated near the instability zone. If poles close to the instability zone must be estimated, care must be taken so that these potentially unstable poles do not cause instability in the convergence of the parameters. During every iteration of convergence, one could calculate the stability of the poles, and provide hard limits to prevent oscillations. In the discrete time domain, one could multiply all the poles by a constant less than one to bring the locus of poles back within the unit circle. After parameter convergence, the loop parameters in the non-linear PLL were fixed, the linear model and the loop filter parameter estimator and were removed, and basic PLL was tested with input signals having a large dynamic range. The block diagram shown in Figure 1.24 was further reduced in Figure 1.25. The variable poles of the controller (1+aoq"1 + ajq'2) were replaced by a single fixed pole at z = 1. This serves as a loop integrator to maintain zero phase error under step input phase conditions. The zeros of the controller (bo + biq'1) were left adjustable by the least squares parameter estimator. The non-linear PLL path gain was adjustable by Co to provide the small gain adjustment needed to match the gain of the zeros in the linear system model. Linear System Model Figure 1.25 Actual PLL estimator block diagram 36 A small modification to the parameter estimation algorithm shown in Equation 18 and Equation 19 below was necessary. Equation 18 T 60 = [c0cr -ck b0 b, bm ] 0(n-1) = [c0(n-1) c,(n-1) -cn(n-k) b0(n-1) b,(n-1) -bn(n-m)] y(n) = 0(n-1)T<()(n) Equation 19 0(n) = Â§(n-1) + p(n) <|>(n) [ d(n) 0(n-1)^>(n)] p(n) = p(n-1) - p(n-1)(|)(n) t|>(n)T p(n-1) 1 1.5.4 Input stimulus Up to this point we have considered only Gaussian or colored random noise sources. This was a good choice if the system to be optimized has an input which has an even distribution of signals which can be represented by a noise source. Other input signal choices representing the actual applied input could produce a more optimized control parameters. One must be careful about choosing narrow band signals as input stimulus because the parameters may not converge properly if only a restricted number of modes were excited. The best solution was to add some noise with the specialized input signal to insure good parameter convergence. Part 2 of this thesis begins to describe the actual input signals to be applied to the example PLL. 1.5.5 Simulation results T7 Figure 1.26 shows an unsuccessful attempt of parameter conversion with the linear phase detector used in the previous PLL example. The linear phase detector was used first to prove the method before the trials with the non linear phase detector. The desired result should have been convergence to the original loop parameters of bo = 36000 and bi = 35773. The Co parameter should have remained close to the value of 1 because the unity gain of the linear system model. Obviously the parameters did not converge. The input noise level was changed as well as the initial least squares convergence gain, but the results of wandering parameters were consistent with all combinations of gain. Initializing the parameters to their expected final value did not help. The parameters still did not converge. PLL Parameter Estimation Parameters cO, bO, b1 Estimated cO bo b1 Figure 1.26 Convergence of example PLL parameters Falling back to a previous class example, three zeros and a single real pole of the example PLL closed loop response were successfully estimated using the identical algorithm which previously proved unsatisfactory. The two poles which were left out were a complex pair which were located close to the unit circle. The results of this parameter estimation were shown in Figure 1.27. 38 Previous Class Problem 3 PLL Zeros and 1 Pole Estimated bO b1 b2 a1 Figure 1.27 Convergence of previous class example using partial example PLL parameters Estimating all of the zeros and poles (3 poles and 3 zeros) for the example PLL closed loop response also proved fatal to the parameter estimation algorithm. The sampling period was reduced by a factor of 10 (from T = 0.001 to T = 0.01) and parameter estimation was repeated. This time it converged easily because the complex poles were moved further in from the unity circle. This longer sampling period, however, was not a solution because it caused a larger discrepancy between the continuous time and sampled time transient responses. A simplification of the problem was attempted by fixing Co = 1. The remaining two parameters (bo and bi) were estimated with zero initial conditions. The results shown in Figure 1.28 show an oscillation in parameter value which was very far from the expected value (bo =36000 and bi = 35773). PLL Parameter Estimation Initial Values Set to Zero bO b1 Figure 1.28 Unsuccessful estimation of two parameters Figure 1.29 repeated the parameter estimation with initial conditions equal to the expected values. Again convergence did not occur. PLL Parameter Prediction Initial Values Set to Correct Values bO b1 Figure 1.29 Unsuccessful two parameter estimation with initial conditions 1.5.6 Possible reasons for non-convergence of parameters 1) The Co term was several orders of magnitude smaller than the bo and bi terms. During least squares parameter estimation, the magnitude of all terms was considered when computing the next value of these terms. When one term is much smaller than another, small changes in the larger term can cause significant changes in the smaller term. In the PLL example, the internal computational magnitudes were adjusted so that the resulting parameters were of similar magnitudes. This was accomplished by multiplying the large coefficients by le+4 to reduce the subsequent parameter magnitude from 36000 to approximately 3.6. Again, this did not help convergence. 2) The feed forward path of the PLL model required the subtraction of two large numbers (bo = 36000 and bi = 35773) The variance of the least squares parameter 41 estimator may not be able to discern the precise magnitudes of these two large numbers. 3) Estimating open loop parameters in a closed loop system was difficult because there was usually at least one pole position close to the unit circle. In the PLL example there was one pole at z = 1 for steady state error performance. Closed loop parameter tests showed difficulty when estimating poles which could be unstable. This problem was solved by not estimating this pole, but in the general case it would be desirable to do so. 4) Differences between the response of the reference model and the adaptive model could require more terms or adjustable parameters in the feed back loop for parameter convergence. In the simple PLL example, the feedback path was set to the fixed value of 1. This was a practical consideration since this path was actually a digital clock signal. Since it was the phase of this signal which was adjustable, it would be difficult to implement a compensater in the feedback path. In general, the PLL example should be a simple device. Designs using the classical method of analysis have worked well and required only minimal components. Unnecessarily adding the complexity of extra unneeded poles or zeros for parameter estimation convergence was not a practical solution for such a simple problem. 1.5.7 Conclusion Estimation of parameters in non-linear control systems could provide a good way to optimize a system under specified input signal conditions. Actually, a great deal of effort was expended to obtain only minimal results. Difficulties included unstable poles in the control system, simulation of the system in parts, and having an adaptive model which was not identical to the reference model. In general parameters tended to drift, and confidence in the resulting control system was low. In many simulations the parameters did converge on something. This was encouraging because it was the opinion of this author that once better methods are devised to handle non-linear control systems, they will be used more often in industry. 42 2. Application to a high density helical digital tape recorder 2.1 Helical recording Helical recording has been used for video tape recorders since the 1950's because of its high signal bandwidth and storage capacity. These older systems generally used frequency modulation (FM) recording methods to record wide bandwidth analog information. Within the last 10 years, digital recording systems have been used to record both video signals and digital information. Some examples of tape systems which use helical technology for digital data recording were the VHS (Metrum), and the 8mm (Exo-Byte) machines. These early systems were originally designed for analog video recording, and were later converted for digital use. As the digital technology matured, video systems were redesigned to convert analog camera signals into digital form to be directly recorded on digital helical recorders. Examples of these systems were D-l (Sony), D-2 (Ampex), D-3 (Panasonic). 4 mm digital audio recorders (Sony) also use helical technology. Each year the demand for greater information storage densities encourages the development of better, and usually smaller equipment. As linear recording densities increase to over 100 Kilo bits per inch (Kbpi), and track densities exceed 1200 tracks per inch, better methods were needed to recover the stored information. This section will discuss the process of digital data recovery in a helical recording system, and methods used to improve the quality of the recorded data. A basic understanding of helical recording technology is necessary before the details of designing a PLL data recovery system can be discussed. As with all control applications, a thorough understanding of the plant was a requirement. This section was written for readers with little background in digital helical data recording. 43 2.2 Description of helical recording 2.2.1 Machine basics Figure 2.1 shows the basic layout of a helical transport. Large stationary recording heads, found in longitudinal recording systems, were replaced with very small heads mounted on a rotating drum or disk. These heads rapidly scan the tape diagonally as it was slowly advanced longitudinally across the scanner. One track was quickly laid down after another at an angle corresponding to the scanner helix angle. In these systems, the data signal was not continuous, but was recorded and reproduced at the rate of 50 to 150 Radio Frequency (RF) envelope bursts per second. This method allows the recording of high signal bandwidths due to the high head to tape speed while conserving linear tape length by using very narrow tracks and advancing tape at a much lower longitudinal speed. The intermittent contact of the scanning heads with the tape was not a problem for video because the horizontal retrace signal was inserted into the video signal when the reproduce head was off the tape. Digital data storage systems use solid state memories to even out the data bursts. High aerial densities were easily achieved using helical technology because of the narrow track widths employed in these systems. New helical systems can achieve over 1200 tracks per inch as compared to production longitudinal systems having less than 200 tracks per inch. This increase in track density in helical systems was primarily due to the precise control of the head to tape interface. The magnetic tape was firmly wrapped around the scanner drum and was positioned by a long lower guide, and was precisely scanned with magnetic recording heads rotating inside the drum. AA Rotation Figure 2.1 Helical machine mechanical schematic diagram Tape path description: Unrecorded tape was stored on the supply reel (a), was guided by rollers and posts (b), was wrapped around a scanner assembly (c), was guided by rollers and posts (d), passes by the control track head (e), was moved by a capstan and pinch roller (f), and was returned to the tape up reel (g). The scanner assembly contains a rotating magnetic recording and play back head assembly, and has a lower guide to precisely position the magnetic recording tape. The result was a recording process which produces tracks which were aligned diagonally across the tape path. 2.2.2 Recording format Figure 2.2 shows a helical recorded tape segment. The recorded tape tracks were recorded sequentially along the tape at an angle of approximately 5 degrees. Information was recorded and reproduced in "bursts" because the head was in contact with the tape for only part of the total head wheel rotational degrees. The system shown uses a 170 degree electrical wrap angle. This means that each of the helical heads in this system was electrically active for only a portion of a scanner revolution. Because of the helical recorder's mechanical dynamics, head to tape velocities can change as the head enters a new track, passes through, and finally leaves the track. 45 A control track was recorded on the lower tape edge. During record mode, a stationary longitudinal head records pulses which were synchronized to the scanner rotation angle. In play back mode, a control system longitudinally positions the tape such that the helical heads scan the previously recorded tracks. Some newer systems can provide tracking without a control track. Helical Tracks Tape motion Figure 2.2 Data tracks recorded on tape Digital data was recorded on the tape as a string of magnetic l's and 0's. Figure 2.3A shows the digital data to be recorded on tape and its clock. Figure 2.3B shows a typical bit-stream reproduced from tape. Notice that the data clock was not recorded. This effectively doubles the system storage capacity since the clock has a minimum of 2 transitions for every data transition and therefore would require more channel bandwidth. During playback, the unrecorded clock must be re-created from the data transitions using a Phase Locked Loop (PLL). In other words, a non-self-clocking modulation code was used during the recording process. Figure 2.3C shows a clock which was regenerated from the data transitions with a small timing error. Figure 2.3D shows the re-clocked digital data. 46 Clock W innnniumnruinrituinnnnjuui A A: Data recorded with clock. B: Reproduced analog data. C: Regenerated clock with small timing errors. D: Re-clocked digital data. Figure 2.3 Recording and reproducing of digital data The data synchronizer, the subject of this section, contains a PLL which must regenerate the original recording clock, and convert the analog data pattern back to digital form. Mechanical transport variations can cause variations in the reproduced data. The data synchronizer must track the reproduced data with nearly zero phase error in the presence of time base error (jitter). Other electronic variations can also cause data detection problems. Figure 2.4 shows the helical track format. User Data bites, shown above in Figure 2.3, were mapped into code-words and recorded serially in blocks on each track. Sync words provide logical starting points for the individual data blocks. A run-up sequence was provided at each block beginning to re-synchronize the PLL clock at the beginning of each track. Although the track segment shown in Figure 2.4 was oriented horizontally, this track was actually recorded at a 5 to 6 degree angle on tape. All preceding and following tracks were recorded in a similar manner. 47 Run up Sync Code Data Sync Code Data Sync Code Data Sync Code Data Sync Code Sync Code Figure 2.4 Helical track format 2.2.3 Electro-mechanical system model Figure 2.5 shows a schematic of a complete helical recording system. In order to design the control characteristics of the PLL control loop in the data synchronizer, we must "identify" the characteristics of the system to which it was connected. Data Clock Tape path signal distortions Electronic signal distortions f) S / 1 $ la- >1- Equalizer 1- Record Reproduce Heads Rotary Transformers Figure 2.5 Electro-Mechanical model of a helical record and reproduce system Electro-mechanical description: The record amplifier (a) converts the digital data into a record current which was applied to the record head. The record head (b) creates a magnetic flux which magnetizes the tape with magnetic poles corresponding to the 48 V digital data. The tape path mechanics (c) add unwanted timing variations in the data which was later reproduced by the play back head (d). The rotary transformer (e) magnetically couples the stationary record and reproduce electronics to spinning record and reproduce heads. A preamplifier and equalizer (f) amplifies and conditions the recorded signal. The data synchronizer regenerates the data clock and converts the data back to digital form. Although for schematic reasons the record, reproduce heads, and rotary transformers were shown outside of the scanner, they were actually inside. 2.2.4 Data synchronizer The data synchronizer converts the incoming analog data back into digital form and provide a digital clock signal which was in phase with the data transitions. Previous designs: The clock frequency was exactly two times the frequency of maximum data transition rate. A nonlinear circuit was used to generate even harmonics of the incoming data transitions and provides a strong frequency component at the data clock frequency. A PLL was used as a narrow bandwidth filter to extract, amplify, and limit the clock frequency. Since the phase detector provides an output which was usually linear with phase shift, classical control methods can be used to characterize its performance. Figure 2.6 shows this design. 49 Analog to Digital Phase Detector Analog Data Figure 2.6 Classical data synchronizer design Although these designs have been successful in reliably recovering the clock from the data transitions, difficulties in designing the frequency doubler circuit have limited their usefulness to single speed operation and to relatively short code patterns. Improved design: Using a digital approach to the phase detector, one can avoid the use (and the phase error problems) of the separate nonlinear device to multiply the frequency content of the input data stream. This was particularly attractive for multiple speed systems which must continuously operate without readjustment. In addition, this approach has an additional interesting feature: Loop correction will not be proportional to input error, but was constant for all magnitudes of input error. This means that the PLL loop bandwidth will change depending on the input phase error. This design however has one difficult problem, the DC phase error gain was infinite. Figure 2.7 shows this design. 50 Analog to Digital Phase Detector After the system identification process in the next section, the above design was discussed in detail. 2.3 Identification of the synchronization process The previous section described the basic function of a helical scan tape recorder, and discussed some of the mechanical and electrical characteristics resulting from helical head to tape interface. This section will use actual data taken from a helical machine to obtain an accurate model of the record and reproduce dynamics. This model was called the "channel model". Once the channel model was obtained, the data synchronizer control system can be designed, simulated, and tested. In general, the designer should consider the following two basic factors during the data synchronizer design process: 1) Time base error, jitter, and offset factors affecting the phase locked loop: This aspect of the design was in the control system domain. Measurement and 51 modeling of these parameters was described in great detail in literature and was relatively straightforward. Since the control system bandwidth was usually under 30 KHz, the parameters used in the design synthesis should agree with the actual system performance 2) Channel frequency response factors affecting data detection: Typically, the analog electronics in the helical channel operate in the 20 MHz to over 100 MHz frequency range. The design of these components can cause channel amplitude and group delay effects which were dependent on the exact sequence of the recorded data bits in the coded data signal. Group delay errors, better known as code sensitivity, was modeled in the control system as a noise input signal. The digital data quality after detection depends on optimizing all aspects of the analog data channel. In some cases, distortions in components preceding the data synchronizer can limit the performance of the data synchronizer. Although some of the data presented in this thesis may not represent an optimum data channel, we will assume that it can be used for the data synchronizer design. The judgment criteria for a digital channel were usually the bit or code word error rate and the burst error rate. In general, the error rates were calculated as the number of successfully detected bits or code words divided by the total number of bits or code words passed by the channel. A typical error rate of a good helical channel was an average of one error for every 10A6 data bits passed. This performance was often described as "BER = IE-6". Burst error rate was usually defined as the probability that a fixed length of repetitive data errors will occur. Situations can happen when the data synchronizer must "re- lock" to the incoming data phase. During phase acquisition, the detection system can incorrectly sample the analog data and cause a string of errors. Burst error length was often more important than the "average" error rate because later in the digital portion of the channel error correction codes have a limited burst error correction capability. A detailed development of the operational characteristics in the data path of a helical tape recorder will now be discussed. 52 2.3.1 Time base error (TBE) and jitter Timing error occurs during recording and reproducing when the head to tape speed was not constant. If velocity error and acceleration were considered at the head to tape interface, the reproduced signal will contain combinations of these mechanical errors. Conceivably, a recorded signal could be distorted by a velocity or acceleration at the record head to tape interface, and be further distorted by a similar velocity or acceleration error at the reproduce head to tape interface. Since TBE errors were mechanical servo errors, their frequency content was usually low and they can be tracked by the PLL. These errors were called "Time Base Errors (TBE). The sudden impact of a helical head into the tape can cause the transmission of a mechanical shock wave down the track length. These waves can displace the proper mechanical tape position under the record head, and/or displace expected bit pattern location under the reproduce head. Rubbing noise, generated from the heads against the tape, can cause high frequency vibrations which can also affect the mechanical position of the data bits. These errors were not insignificant when one considers that the actual magnetic bit length can be less than 0.5 micro meters. These timing errors were called "jitter". Note: Rubbing noise was more commonly used to describe a particular channel noise. The head to tape rubbing action causes vibrations in the ferrite of the reproduce head causing an increase in the noise floor in the lower third if the channel spectrum. For control system modeling purposes, this noise was lumped into a single random noise quantity in the channel. Two very good instruments for the evaluation of time base error and jitter were the spectrum analyzer for frequency domain measurements, and the time interval analyzer for time domain measurements. 2.3.2 Frequency domain analysis The spectrum analyzer was a frequency domain tool which can be used to experimentally determine the variations in the head to tape speed caused by transport mechanics. A frequency, pure from side bands, within the channel bandwidth was first recorded on tape. The tape was re-wound and reproduced. Time variations caused by mechanical transport variations will phase modulate the reproduced signal. A spectrum analyzer connected to the preamplifier or equalizer output centered at the 53 recorded frequency will measure the power content of the reproduced signal as a function of frequency. The resulting spectrum, containing frequencies generated from mechanical phase modulation of the recorded data, was usually within 30 KHz of the data synchronizer's control system. Figure 2.8 shows the frequency spectrum caused by transport head to tape speed variations for a helical transport. This curve appears to be Gaussian in shape because the scanner control system was designed to maintain constant head to tape speed. Mechanical variations caused head to tape speed deviations which can not be corrected by the scanner control loop. Electronic noise, to a much lesser degree, can also account for head to tape speed variations. MKR 7.92600 MHz REF 0 dBm ATTEN 10 dB -38.4 dBm CENTER 7.92600 MHz SPAN 40.00 KHz RES BW 100 Hz VBW 100 Hz SWP10 SEC Figure 2.8 Frequency spectrum of the reproduced signal 54 The test frequency of approximately 8 MHz was used. The actual channel bandwidth for this system was 29 MHz. For Non Return to Zero (NRZ) data, the clock frequency was two times the channel bandwidth or 58 MHz. A simple calculation, 58/9=7.3 shows that the required control system bandwidth should be approximately 7 times the spectral bandwidth shown in this Figure. This frequency response can be used to determine the approximate variance of the PLL input signal and shows the input phase noise was not strictly random. There was some sort of resonance causing the response peaks at 6 KHz from the center frequency. This seems a little high for a mechanical system problem, but the parts in the head assembly were very small and were mounted with stiff mechanical components. 2.3.3 Time domain analysis The time interval analyzer can also be used to characterize the transport speed variations. By utilizing the digital sync detection circuitry in the recorder, the timing between known locations in the recorded track can be measured. The top part of Figure 2.9 shows an actual reproduced data trajectory. Initially, the head enters the tape track at a lower than nominal speed. Towards the middle of the track, the head to tape speed has increased to higher than average speed to compensate for initial lower than average tape speed. Near the track end there can be an under-shoot in tape speed. The bottom part of Figure 2.9 shows another head to tape trajectory. In this case, a different velocity profile was obtained. This information was equivalent to the frequency spectrum data, but was represented in a different domain. 55 Sync Word Relative Time (ns) Sync Word Relative Time (ns) 140 0 - -20 - 0 1.89 3.77 5.66 7.54 9.43 11.31 13.20 15.09 16.97 18.86 Scanner Position (Mili sec) Scanner Position (Mili sec) Figure 2.9 Time domain analysis of the sync word timing 56 Using the data from many measurements of the sync word timing data, a histogram of the average sync word timing and variance as a function of head rotation can be obtained. This information combined with the frequency domain data described above can be used to design a colored noise source for predicting the best control parameters for this particular machine. 2.3.4 Tracking errors The helical machines have a track pitch, or the distance between track centers, of 20 to 50 microns. In some recorders, a guard band, an unrecorded area, of 5 microns was placed between the tracks for additional separation. In reproduce mode, the head would have 5 microns of tracking tolerance before picking up the signal from an adjacent track. Azimuth recording was another popular method of providing adjacent track signal rejection. By recording sequential tracks at alternating 15 degree angles, unwanted signals from adjacent tracks were attenuate by a 30 degree azimuth loss. This method was better at rejecting high frequency cross talk signals. PLL input transition interference caused by an adjacent track was often the worst kind of problem. This was because the adjacent track data was written with exactly the same clock as the track being read. Since these signals were correlated, their interference vectors effect must be added to the desired signal. This was much worse than random noise which has a RMS interference effect. Figure 2.10 shows as actual data detection situation in which a bit could have been read falsely because of adjacent track interference. Notice that the pulse response happened a little early for that single bit transition occurring 1/3 of the way from the beginning of the trace. 57 Azimuth recording, guard bands, and auto tracking can alleviate these problems, but they were never eliminated. 2.3.5 Rotary transformer frequency response The rotary heads were electrically coupled to the stationary transport frame via a rotary transformer located in the scanner. The frequency response of this transformer was limited by several design constraints. At low frequencies, the transformer shunt inductance reduces the coupling efficiency between the rotating preamplifier and the transformer secondary load. At high frequencies, ferrite losses in the rotary transformer core can limit the maximum frequency response. When the reproduced data signal was "filtered" by the rotary transformer's band pass response, amplitude and phase errors can result. Some of the effects of the rotary transformer were shown in Figure 2.11. 58 DSA 602 DIGITIZING SIGNAL ANALYZER Zoom Figure 2.11 Low frequency response limitations in the rotary transformer 2.3.6 Equalization magnitude and phase response Helical recorders use inductive heads which reproduce the derivative of the recorded magnetic flux. Equalization, which was necessary to restore the proper transition timing, can cause pulse amplitude and timing shifts which can adversely affect data re-synchronization. These errors depend on the actual data pattern recorded on tape, and not on mechanical limitations in the helical deck, and were described as "code sensitivity". Examples of code sensitivity problems were shown in Figure 2.12. an 61 Unlike time base errors which can be modeled using the helical transport mechanical dynamics, code sensitivity errors depend on the data which the user has previously recorded on tape. These errors were modeled as control system noise. 2.4 Conclusion Designing a PLL for magnetic data recovery requires detailed knowledge in mechanical and electrical data channel areas. PLL control systems for data recovery must operate through unexpected input signal situations. Some of these problems can be alleviated by designing with one or more nonlinear components in the control loop. The data shown in the above figures was taken on a D-1 helical data recorder with a non-linear PLL in the data synchronizer. The phase detector was similar to the type- 1 phase detector as described above. The VCO was a digitally synthesized phase modulator. This added significant phase stability and center frequency control over linear analog type VCOs. This system had the capability of recovering data at over 100 Mb/sec, and could re- synchronize after data loss in only a few code words. The re-synchronization ability was primarily due to the non-linear phase modulator (DVCO) which could instantaneously change phase upon command from the digital loop controller. Code words with long sections between transitions caused this design to drift in phase. The loop gain was adjusted to minimize this problem, but it still existed. Changing the phase detector to a type-2 or 3 would have probably helped this problem. Since this design was done before my graduate work in controls (1986 1988) classical simulation methods were used to predict and verify performance. These older classical methods worked quite well. 3. Future correction Analysis and simulation methods for designing control systems with non-linear components have become more prevalent in the future. The non-linear PLL described in this thesis was very beneficial to the design in which it was applied. Using parameter estimation for non-linear control system design may have a future after some of the problems which were encountered in this thesis were resolved. The beauty of this method was that one can design a controller using the actual input signal as a design parameter. Classical controls assumes a step, white noise, or impulse signals as system inputs. It is rare when a control system must only respond to such a narrow class of signals. Time to market has become increasingly more important. The design methods discussed in this thesis could be automated so that a complete control design could be accomplished by connecting an instrument into a plant and associated components. Using prediction, this system could compute optimal control parameters. The user may know little or nothing about the actual system. <53 4. Simulation listings Program #1: Continuous Time Simulations //thesis_a.cpp; Continuous time frequency response and step response // jw transform of linear PLL (classical appraach) for comparisons // and Euler integrator transient simulation #include #include #include main() { FILE ^stream; float REFph, // phase of reference signal VCOph, // phase of VCO B, pd, al,a2,a3, b0,bl,b2,b3; int T,Tl,i; // simulation time stream = fopen("c:\\school\\ctl2\\CLASS.DAT", "w"); // open a file for update fprintf(stream, "\n\ndata sync classical frequency response\n"); float w, f, num_r, num_i, den_r, den_i, mag; // CONTINUOUS TIME FREQUENCY RESPONSE OF EXAMPLE PLL: fprintf(stream, "\n\ndata sync classical frequency response\n"); #define k 3.6e4 #define a 0.1*6.28 #define b 100*6.28 #define N 1 for (i=-10;i<=20;i++) { 64 f = pow(10,(float)i/10); w = 6.28*f; num_r = k*a; num_i = k*w; den_r = -b*w*w+k*a/N; den_i = -w*w*w + k*w/N; mag = 20*Iog 10(sqrt((num_r*num_r + num_i*num_i)/(den_r*den_r + den_i*den_i))); fprintf(stream, "\nfreq:%10.4f mag: %10.4f",f,mag); } // CONTINUOUS TIME STEP RESPONSE OF EXAMPLE PLL // SYSTEM SIMULATED AS A WHOLE SYSTEM: fprintf(stream, "\n\ndata sync classical step response #l\n"); VCOph =0; B=0; pd=0; al=a2=a3=0; bl=b2=b3=0; REFph = 1; // input was unit step in phase for (T=0;T<=20;T++) // 20 output points { fprintf(stream, "\n%10.4f % 10.41 %10.4f %10.4f",(float)T/200,REFph,B,VCOph); for (T1=1;T1<100;T1++) // inner loop 0.01 sec { #define INT 0.00005 // integrator time a3 += INT a2; a2 += INT al; al += INT REFph; b3 += INT b2; b2 += INT bl; bl += INT VCOph; VCOph = a2*k + a3*k*a -bl*b b2*k b3*k*a; } } // SYSTEM SIMULATED IN PARTS fprintf(stream, "\n\ndata sync classical step response #2\n"); VCOph =0; B=0; pd=0; al=a2=a3=0; bl=b2=b3=0; REFph = 1; for (T=0;T<=20;T++) // 0.1 seconds { fprintf(stream, "\n%10.4f %10.4f %10.4f % 10.4f' ,(float)T/200, REFph, B, VCOph); for(Tl=100;Tl;Tl) // 0.001 sec integration period { pd = REFph-VCOph ; b3 += INT*VCOph; b2 += INT*bl; bl += INT*B; VCOph = b2 b3*b; al += INT*pd; B = pd*k + al*k*a; } // linear phase detector // VCO; Euler integrator // Loop filter; Euler integrator } fclose(stream); } Program #2: Sampled Time Simulations //thesis_b.cpp; Sampled time frequency response and step response // jw transform of discrete time PLL // and discrete time transient simulation #include #include #include include "c:/school/ctl2/MAT CLS.CPP" main() { FILE *stream; float REFph, // phase of reference signal 66 VCOph, VCO_l, VCO_2, // phase of VCO B, B_l, B_2, pd, pd_l, al,a2,a3, b0,bl,b2,b3; int T,i; // simulation time stream = fopen("c:\\school\\ctl2\\CLASS.DAT", "w"); // open a file for update fprintf(stream, "\n\nPLL sampled time frequency response\n"); float w, f, num_r, num_i, den_r, den_i, mag; // FREQUENCY RESPONSE OF SAMPLED TIME SYSTEM: #defme k 3.6e4 // same as linear case, but -3.5dB @ 10Hz #define a 0.1 *6.28 #define b 100*6.28 #defineN 1 #define Tau 0.001 // Tau =0.001 gives -3.5dB instead of -3dB(analog) @ 10Hz // Tau =0.01 gives 2Hz -3dB bandwidth // Tau =0.0001 gives results similar to analog case for (i=-10;i<=20;i++) { f = pow(10,(float)i/10); w = 6.28*f; num_r = -k*cos(Tau*w) +k*a -k*a*sin(Tau*w); num_i = k*w -k*w*sin(Tau*w) +k*a*cos(Tau*w); den_r = w*w*w*w*Tau +k*w*cos(Tau*w)/N +k*a/N -k*a*sin(Tau*w)/N; den_i = -w*w*w*b*Tau -k*w/N +k*w*sin(Tau*w)/N +k*a*cos(Tau*w)/N; mag = 20*log 10(sqrt((num_r*num_r + num_i*num_i)/(den_r*den_r + den_i*den_i))); printf("\nfreq:%10.4f mag: %10.4f",f,mag); //testprint fprintf(stream, "\nfreq:% 10.4f mag: % 10.4f",f,mag); } // SAMPLED TIME STEP RESPONSE OF EXAMPLE PLL // SYSTEM SIMULATED AS A WHOLE SYSTEM: fprintf(stream, "\n\nPLL sampled data step response whole system simulation\n"); VCOph =0; B=0; pd=0; al=a2=a3=0; bl=b2=b3=0; REFph = 1; fprintf(stream, "\n%10.4f %10.4f %10.4f",0,REFph,VCOph); // print initila conditions for (T=1;T<=100;T++) // .1 seconds total, 0.01 sec each step { a3 = a2; a2 = al; al = REFph; b3 = b2; b2 = b 1; bl = VCOph; #define G 0.975 // correct for steady state response VCOph = G*0.099757*al -G*0.17289*a2 +G*0.073106*a3 // Tau = 0.001 +2.4339*bl -1.8944*b2 +0.46055*b3; fprintf(stream, "\n%10.4f %10.4f %10.4f,(float)T/1000,REFph,VCOph); } // STEP RESPONSE OF SAMPLED TIME SYSTEM SIMULATED IN PARTS: fprintf(stream, "\n\nPLL sampled data step response simulated in parts simulation\n"); VCOph = VCO_ 1 = VCO_2 =0; B = B_1 = B_2 =0; pd = pd_l =0; al=a2=a3=0; bl=b2=b3=0; REFph = 1; fprintf(stream, "\n% 10.4f % 10.4f % 10.4f % 10.4f",0,REFph,B,VCOph); // print initila conditions for (T=l ;T<= 100;T++) // 0.1 seconds in 0.01 sec steps { //---------------------linear phase detector pd_l= pd; pd = REFph-VCOph ; //---------------------Loop filter B_2 = B__1; B_1 = B; B = pd*k + pd_l *k*((a*T au)-1) + B_l; 68 //------------------------ #define coefDl 7.43e-7 #define coefD2 1.53 #define coefD3 -0.53 vco // (l-exp(-b*T)/b // l+exp(-b*T) // -exp(-b*T) VCO_2 = VCO_l; VCO_l = VCOph; VCOph = B_1 *coefD 1 + VCO_l*coefD2 + VCO_2*coefD3; fprintf(stream, "\n%10.4f %10.4f %10.4f %10.4f",(float)T/1000,REFph,B,VCOph); printf("\n% 10.4f", VCOph); // test print fclose(stream); } Program #3: Parameter Estimation #include "c:/school/ctl2/MAT_CLS.CPP" float gausian_noise() // Returns a normally distributed deviate with zero mean and unit variance. static int iset=0; static float gset; float fac,r,vl,v2; if (iset ==0) { do { v 1 =2.0*(((float)rand())/RAND_MAX)-1; v2=2.0*(((float)rand())/RAND_MAX)-l; r=vl*vl+v2*v2; } while(r>=1.0llr==0); fac = sqrt(-2.0*log(r)/r); // Box Muller transformation gset=v 1 *fac; // save second deviate iset= 1; return v2*fac; // return calcualted deviate else // use saved deviate { iset =0;; return gset; } } #define PART_C 2 // 0: old school problem; 3 zeros, one pole // 1: PLL estimator bO bl // 2: PLL estimator cO; bO bl main() { FILE ^stream, *poly; // HW adaptive filter: #if PART_C ==0 // Class example matrix F(4,4,"F[[.2 0 0 0]" //F matrix "[0.2 0 0]" "[ 0 0 .2 0 ]" "[0 0 0 .2]]"); matrix f(4,1 ,"f[0 0 0 0]"), // estimated parameters xr(4,1 ,"xr[0 0 0 0]"), // reference path state x(4,l,"x[0 0 0 0]"), // system state t(4,1), // temporary column matric p(l,4,"p[0.1 0.17 0.07 0.48]"),// real pole part of thesis polynomial Fn(4,4); #endif #if PART_C == 1 // compute aO+a 1 z-1 matrix F(2,2,"F[[ .2 0]" // F matrix "[ 0 .2]]"); matrix f(2,1 ,"f[36000 -35773]"), // estimated parameters xr(6,1 ,"xr[0 0 0 0 0 0]"), // reference path state nn x(2,l,"x[0 0]"), //system state t(2,1), // temporary column matric tr(6,1), // temporary column matric p(l,6,"p[0.099757 -0.17289 0.073106 2.4121 -1.8632 0.4505]"),// roots: 0.98, 0.9463, 0.4858, Tau = 0.001 Fn(2,2); #endif #if PART_C ==2 matrix F(3,3,"F[[ .02 0 0]" // F matrix "[ 0 .02 0 ]" "[ 0 0 .02]]"); matrix //f(3,1 ,"f[l 36000 -35773]"), // estimated parameters f(3,l,"f[l 0 0]"), xr(6,l,"xr[0 0 0 0 0 0]"), // reference path state x(3,l,"x[0 0 0]"), //system state t(3,1), // temporary column matric tr(6,1), // temporary column matric p(l,6,"p[0.099757 -0.17289 0.073106 2.4121 -1.8632 0.4505]"),//roots: 0.98, 0.9463, 0.4858, Tau = 0.001 Fn(3,3); #endif double e, y, n, nO, nl, lam, d, es, Vo; unsigned int i,j,k; printf("\nnew start\n"); stream = fopen("c:\\school\\ctl2\\CLASS.DAT", "w"); // open a file for update poly = fopen("c:\\school\\ctl2\\poly.DAT", "w"); // open a file for update //=========================== RLS ALGORITHM fprintf(stream, "\n\nProject #2 RLS Algorithm\n"); 71 // forgetting factor lam = 0.9999; es = 0; Vo =0; j =0; for (i=0;i<=1000;i++) // i = number of iterations { for (k=0;k<10;k++) { n = l*gausian_noise(); // noise source #if PART_C ==0 //====================================== school program; 3 zeros, one pole //-----------------------------------------------------REFERENCE PATH xr = t.elmt(4,l,n,coef(xr,l,l),coef(xr,2,l),Vo); // next x, using last value of "y" Vo = p*xr; //-----------------------------------------------------ESTIMATED PATH x = t.elmt(4,l,n,coef(x,l,l),coef(x,2,l),y); // next x, using last value of "y" y = ~f*x; // output, computes next value of "y" #endif #if PART_C ==1 //====================================== PLL aO+alz-1 calcualtion double pd,VCOph,VCO_2,VCO_l; if(!i) pd=VCOph=VCO_2=VCO_l=0; // initialize variables //-----------------------------------------------------REFERENCE PATH xr = tr.elmt(6,l,n,coef(xr,l,l),coef(xr,2,l),Vo,coef(xr,4,l),coef(xr,5,l)); // next x, using last value of "y" Vo = p*xr; //-----------------------------------------------------ESTIMATED PATH pd = n-VCOph ; // linear phase detector x = t.elmt(2,l,pd,coef(x,l,l)); //Loop filter y += coef(f,l,l)*coef(x,l,l) + coef(f,2,l)*coef(x,2,l); // add integrator // VCO, parameters were given // (l-exp(-b*T)/b gain adjusted by 1000 // l+exp(-b*T) #define coefDl 7.43e-7 #define coefD2 1.53 #define coefD3 -0.53 // -exp(-b*T) VCO_2 = VCO_l; VCO_l = VCOph; VCOph = y*coefDl + VCO_l*coefD2 + VCO_2*coefD3; #endif #if PART_C ==2 //====================================== PLL cO; aO+alz-1 calcualtion double pd,VGOph,VCO_2,VCO_l; if(!i) pd=VCOph=VCO_2=VCO_l=0; // initialize variables //--------------------------REFERENCE PATH xr = tr.elmt(6,l,n,coef(xr,l,l),coef(xr,2,l),Vo,coef(xr,4,l),coef(xr,5,l)); // next x, using last value of "y" Vo = p*xr; //--------------------------ESTIMATED PATH //---------------------linear phase detector pd = n*coef(f, 1,1)-VCOph ; //linear phase detector (uses Co term) //---------------------Loop filter, find parameters with RLS algorithm x = t.elmt(3,l,n,pd,coef(x,2,l)); // next x, using last value of "y" y += coef(f,2,1 )*coef(x,2,1) + coef(f,3,l)*coef(x,3,l); // add integrator //---------------------VCO, parameters were given #define coefDl 7.43e-7 // (l-exp(-b*T)/b gain adjusted by 1000 #define coefD2 1.53 //l+exp(-b*T) #define coefD3 -0.53 // -exp(-b*T) VCO_2 = VCO_l; VCO_l = VCOph; VCOph = y*coefDl + VCO_l*coefD2 + VCO_2*coefD3; #endif //======================================= parameter estimation e = Vo y; f = f + F*x*e; // next state of parameter matrix d = lam + (double)(~x*F*x); // pre compute denominator F = (F (F*x*~x*F)/d)/lam; // next state of matrix F (gain matrix) }// for k #if PART_C ==0 // class example 73 fprintf(stream, "\n%d %10.4f %10.4f %10.4f %10.4f", i, coef (f, 1,1 ),coef(f,2,1) ,coef(f ,3,1 ),coef(f,4,1)); #endif #if PART_C == 1 // PLL example cO; aO+a 1 z-1 if(!H { fprintf(stream, "\n%d % 10. If % 10. If", i, coef(f, 1,1),coef(f,2,1)); j=9; } #endif #if PART_C ==2 // PLL example cO; aO+alz-1 if(U-) { fprintf(stream, "\n%d %10.4f%10.4f %10.4f", i, coef(f, 1,1 ),coef(f,2,1 ),coef(f,3,1)); j=9; } #endif }// for i fclose(stream); } 74 Glossary Bandwidth Continuous Time Frequency Frequency Response Loop Filter Linear System Non-linear System PLL Phase Phase Detector Simulated in Parts Sampled Time Step Response SNR Whole System vco Design characteristic of a system which determines its response rate. An analog type control system based on integrators. A repetition characteristic of a signal. Characteristic of system which was stimulated with sine waves. The part of a control system which stabilizes the control loop and provides performance adjustment. A time and signal amplitude invariant system. A system which depends on time and signal amplitude. Phase Locked Loop. The position of a signal relative to another or other reference. A part of a PLL which determines the phase error between the input signal and the VCO output phase. A linear or non-linear system which was broken apart into smaller linear and non-linear sections. A digital control system based on delay functions. Characteristic of a system which was stimulated with a sudden level change. Signal to Noise Ratio. A linear system which was reduced into a single transfer function. Voltage Controlled Oscillator. 75 Bibliography Aram Budak, Passive and Active Network and Synthesis, Houghton Mifflin Company, 1974. Peter M. Clarkson, Optimal and Adaptive Signal Processing, CRC press, 1993. John Dazzo & Constantine Houpis, Linear Control System Analysis and Design, McGraw-Hill, 1975. Simon Haykin, Adaptive Filter Theory, Prentice Hall, 1991. Joe D. Hoffman, Numerical Methods For Engineers and Scientists, 1992. loan Dore Landau, System Identification and Control Design, Prentice Hall, 1990. Lennart Ljung, System Identification, Theory For The User, Prentice Hall, 1987. K. Ogata, Discrete Time Control Systems, Prentice Hall, 1987. Mike Radenkovic; class notes, assignments, and handouts, 1992. Ulrich L. Rohde, Digital PLL Frequency Synthesizers, Prentice-Hall, 1993. 76 |

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PAGE 1 I NON-LINEAR PHASE LOCKED LOOP DESIGN AND VERIFICATION by Robert Nelson Spurr B.S., University of Colorado, 1977 M.S., University of Colorado at Denver, 1995 A thesis submitted to the Faculty of the Graduate School of the University of Colorado at Denver in partial fulfillment of the requirements for the degree of Master of Science Electrical Engineering 1995 PAGE 2 This thesis for Master of Science degree by Robert Nelson Spurr has been approved by PAGE 3 Spurr, Robert Nelson (M.S. Electrical Engineering) Non-Linear Phase Locked Loop Design and Verification Thesis directed by Professor Miloje Radenkovic ABSTRACT A simple Phase Locked Loop (PLL) example was used to develop a model which can be simulated with non-linear components, in particular, a non-linear phase detector with linear control loop and Voltage Controlled Oscillator (VCO). Variable loop bandwidth which was dependent on input signal amplitude was demonstrated. An attempt was made to estimate internal control loop parameters using a recursive least squares estimation algorithm. The method described is applicable to other types of control systems containing non-linear elements. An actual example based on a helical data recorder is included to show the types of input signals which were present in the analog to digital conversion of the data detection process. A clock signal was extracted from these signals using a non-linear PLL. PAGE 4 This abstract accurately represents the content of the candidate's thesis. I recommend its publication. s Mi loje Radenkovic PAGE 5 CONTENTS Chapter 1. Analyzing specialized control systeme with non-linear components .............................. 1 1.1 Introduction ................................................................................................................... 1 1.1.1 Thesis objectives ........................................................................................................ 2 1.2 Classical PLL design ..................................................................................................... 2 1.2.1 Types of PLLs .................................................................. ........................................... 3 1.2.2 Translation between frequency and phase .................................................................. 4 1.2.3 Analysis of a type-2 PLL with an integrator.. ............................................................. 4 1.2.4 Third order PLL with an integrator ............................................................................ 6 1.2.5 Conclusion .................................................................................................................. 8 1.3 Continuous and sampled time third order PLLs ............................................................ 9 1.3.1 Whole system model ................................................................................................ 10 1.3.2 Simulation in parts model. ........................................................................................ 12 1.3.3 System equivalence .................................................................................................. 14 1.3.4 Conclusion ................................................................................................................ 18 1.4 Adding non-inear elements .......................................................................................... 19 1.4.1 Step response ............................................................................................................ 23 1.4.2 Noise response .......................................................................................................... 24 iv PAGE 6 1.4.3 Pulse response ................................... . ... . ........................ ... ... . . ......................... . 27 1.4.4 Bandwidth approximation method .......................................... . ...... ..... ................. 28 1.4.5 Conclusion .......................................................................................... .................... 29 1.5 Parameter estimation of systems with non-linear components . ................................. 30 1.5. 1 Noise cancellation review ............... ...... ... ..... . ..... ..................... ... .......................... 30 1.5.2 Estimating parameters in non-linear control systems ........ ............................... ...... 33 1.5.3 Application to the non-linear PLL example ............................. ......... ..................... 34 1.5.4 Input stimulus ..... .......................... . ..................................... ........ ... ....................... 37 1.5.5 Simulation results . ................................................................ .......... . ..................... 37 1.5 .6 Possible reasons for non-convergence of parameters ................. ................ ...... .... 41 1.5.7 Conclusion ......................................... . ...... ............................................................ 42 2. Application to a high density helical digital tape recorder ............................................ 43 2.1 Helical recording .... .... ......................... ........ ..... ........................................................ 43 2.2 Description of helical recording .... ..... .... . ...... ...... . .......... .... . ... .... . ............ .......... 44 2.2.1 Machine basics ...................... ............................. ....... ........................................... 44 2.2.2 Recording format ...................... : ............................................................................... 45 2.2.3 Electro-mechanical system model .......................................... ................................. 48 2 2.4 Data synchronizer ..... .... ...... ........... ... ...... ........... . . ................... ....... ..... . ..... ...... . 49 2.3 Identification of the synchronization process ................................. ............................ 51 2.3.1 Time base error (TBE) and jitter ...... ..... .................................................................. 53 v PAGE 7 2.3.2 Frequency domain analysis ....................................................................................... 53 2.3.3 Time domain analysis ............................................................................................... 55 2.3.4 Tracking errors ......................................................................................................... 57 2.3.5 Rotary transformer frequency response .................................................................... 58 2.3.6 Equalization magnitude and phase response' 60 2.4 Conclusion ................................................................................................................... 62 3. Future dirrection ............................................................................................................ 63 4 Simulation listings ......................................................................................................... 64 Glossary .............................................................................................................................. 75 Bibliography ............................................................................... ...... ................................ 76 vi PAGE 8 1. Analyzing specialized control systeme with non-linear components 1.1 Introduction Previous engineering problems associated with the detection of analog data recorded on helical tape recorders have promoted an interest in designing better data recovery circuitry. An important part of the data recovery circuitry and part of the detection problem was the Phase Locked Loop (PLL) which regenerates the clock of Non Return to Zero (NRZ) recorded data. Basic PLL technology has been in existence for many years, and is still widely used in many modern analog and digital applications. Since the theory of the analog PLL is well developed in literature, only a brief description of the basic concept was presented. This thesis will add to the basic PLL technology by adding a nonlinear phase detector to the basic PLL structure, and analyze the effect of this change Least squares parameter estimation methodology was applied to the nonlinear PLL example to automatically determine control parameters for a specific class of input signals. Inserting non linear components to an otherwise linear control system adds an interesting twist to the usual analysis methods. Since superposition as defined in linear control systems no longer applies to a non-linear system when signals of large dynamic range were applied, an alternative simulation method was proposed to determine desirable control parameters. Basic theory and results derived from linear and non-linear PLL examples were provided. Part 2 provides an example of how non linear methods of PLL control have application to the field of high density helical tape recorders 1 PAGE 9 1.1.1 Thesis objectives -To briefly review existing PLL technology. Starting with a continuous time PLL control system, develop the sampled time equivalent system. Verify the equivalent sampled time PLL model. Propose a method for simulating control systems with non-linear components. Separate the linear sampled time equivalent control system into parts, and compare simulation results to previous simulations. Add a non-linear phase detector to the system simulated in parts and re-simulate. Show advantages and disadvantages of PLLs with non-linear phase detectors. Discuss classical methods of determining performance of PLLs with non-linear phase detectors. Propose the use of parameter estimation as a tool for determining control system parameters for non-linear control systems. Apply this method to a simple PLL example. Provide a practical example of the use of non-linear control methods for a data separator in a high density helical tape recorder. 1.2 Classical PLL design The basic PLL shown in Figure l.l, contains a phase detector, a loop filter, a Voltage Controlled Oscillator (VCO), and a feed back divider. The input was a frequency source which was applied to the phase detector. The output was a VCO which was controlled by the loop filter. The phase of the VCO output was compared to the phase of.the reference signal in the phase deteCtor, and the error signal was applied to the loop filter. The loop filter controlled the performance characteristics of the PLL. 2 PAGE 10 Input Loop Filter Feed Back .___ __ _, Divider Figure 1.1 Basic PLL block diagram Voltage Controlled Oscillator Output Historically, PLLs have been designed from classical second order control system models. The characterization of these models have been improved by using third order models to compensate for one additional pole in the VCO circuitry. Further model improvements have been made for digital PLL by adding a sample and hold to more accurately model the effect of a sampling phase detector. 1.2.1 Types of PLLs PLLs can be classified by their ability to track step, ramp, and parabolic input signals. The following three classifications were commonly used: Type-0: Follows a step frequency input with constant frequency error. Will not follow a ramp or parabolic frequency inputs. This type was really frequency locked loop TypeI: Follows a step frequency input with zero error, follows a ramp frequency input with constant error. Will not follow a parabolic frequency input. Type-2: Follows both a step and ramp frequency input with zero error, and follows a parabolic frequency input with constant error. In the remainder of this thesis the type-2 PLL was considered because of its ability to track a step phase change with diminishing phase error. This feature was ideal for data recovery in a digital tape recorder. PAGE 11 1.2.2 Translation between frequency and phase PLLs were very similar to other control systems with the exception of the generation of the loop error signal. PLLs perform an analog subtraction of the phase of the input frequency from the phase of the output frequency. Since frequency is the derivative of phase, calculations at the phase detector must use the integral of the frequency. This was why the VCO was modeled as an integrated gain function, and the PLL input was defined in terms of phase. Using this frequency to phase translation, a type-2 PLL will follow a step phase input with zero error, a ramp phase input with constant error, and will not track a parabolic phase input change. 1.2.3 Analysis of a type-2 PLL with an integrator Figure 1.2 shows the control system diagram for a second order PLL with a perfect integrator. The reference signal input ' PAGE 12 Phase Detector Loop Riter Voltage Controlled Oscillator Reference __ PAGE 13 By rearranging the loop components, a transfer function at the phase detector output can be obtained. Using the final value theorem with a step phase input (a ramp frequency function) the steady state error can be found. Equation 3 This means that theoretically a second order PLL with an integrator will track a step phase input change with no output error. In practical PLLs, perfect integrators can not be achieved because amplifiers with infinite gain were not realizable. The phase error due to this practical consideration is usually far to small to be seen, and phase errors were usually dominated by time delays in the circuit components. 1.2.4 Third order PLL with an integrator The type-2 PLL described above was modified to include the effects of a third pole in the VCO which was usually placed just above the desired control system bandwidth. Some VCO have a limit on the rate of frequency change due to their design. Often the VCO performance was intentionally reduced by adding a rate of frequency change limit because it has the effect of filtering out spurious noise signals which were outside the PLL control loop bandwidth. This feature was added to Figure 1.3 with the "(s+b )" term in the VCO block. Phase Detector Reference Input , Figure 1.3 Third order PLL Loop Filter 1 N 6 Voltage Controlled Oscillator Output PAGE 14 Transfer function of the third order PLL: Equation 4 G(s) T(s) = = 1 + G(s) N kvco 1 5 5 (5+b) 1 ko1. 5+a kvco N 5 5 (5+b) Frequency response: Equation 5 kvco (S+a) T(s) = --------,--53+ b 52+ kvco 5 + k41 k vco a N N 5=jro kvco(a+jro) T(jro) = ----,----------,------jof bro2 +j k $ kvco ro + k41 kvco a N N Using the following performance parameters, Equation 6 Given : a = 0.1 6.28 b = 100 6.28 k = kct> kvco = 36000 N=1 _____ T(s) =-= 5 3 + 628 5 2 + 36000 5 + 36000 a the following simulation diagram can be obtained. 7 PAGE 15 Figure 1.4 Continuous time implementation of the third order PLL 1.2.5 Conclusion The above third order continuous time PLL model serves as a starting point for the design of the PLL with a non linear phase detector. Thorough characterization of this system will set a performance reference to which changes in the system can be compared. Following analysis and simulations replace the linear phase detector with a nonlinear phase detector. Before these changes could be made, however, the following issues were first addressed: 1) Practical control parameter values were need to allow for frequency response and transient response simulations. A loop bandwidth of 10 Hz was chosen for convenience. Actually, data recovery systems use much wider band width. The results presented were independent of the actual bandwidth because the design can be scaled to any frequency. 2) A sampling phase detector was added because our application uses a phase detector which was built out of digital components and because discrete time simulations require a sampled data input. Analog phase detectors were some times used in this application, but they have the disadvantage of lower noise immunity. The frequency response of the continuous time and sampled time systems were compared to insure that the sampled time system was nearly equivalent to the continuous time systems. 3) Adding a nonlinear phase detector requires a different modeling approach. In general, linear system properties such as superposition no longer apply to non linear systems. Because of this difficulty, the third order PLL with a sampling phase detector was simulated in parts. The performance of the system simulated PAGE 16 in parts needs to be verified against the original system to insure equivalence. To do this, the system with the linear sampled phase detector was separated into parts and simulated. The results were compared to the nearly equivalent system which was simulated as a whole. Once equivalence was obtained, the linear phase detector was replaced with the nonlinear phase detector and the system were simulated again. 4) Parameter estimation was tried to automatically determine controller parameters. Nonlinear components provide different characteristics at different signal amplitudes. Stimulating the system with a "typically good" input signal levels provides one set of results. Stimulating the system with a "typically bad" input signal level provides another set of results which may not be related in magnitude to the "typically good" input signal levels. To determine optimum system parameters, a "typically good" input signal was applied to the system and control parameters were automatically generated which minimize the least squared error as compared to the desired system result. "Typically bad" input signal levels were then applied to verify the effect of the non linear element. 1.3 Continuous and sampled time third order PLLs The intent was to use a pure sampled data system for PLL simulation because parts of a digital PLL were implemented using discrete time components and simulations were in general faster and easier in the discrete time domain. The design requirement, however, was based on an analog requirements which was recovering the clock of digital data recorded and reproduced with a mechanical interface. Frequency response analysis was intended to show that the continuous time (analog) and sampled time implementations have approximately the same amplitude performance The second complexity was separating both the analog and sampled time systems into parts to be simulated with separate lines of code which were subsequently combined to form the completed control system. Justification was necessary to prove that after the system was separated into parts, it was roughly equivalent to the original system. The designations "Whole System" and "Simulated in Parts" were used to distinguish between the different methods which ultimately achieve the same result. PAGE 17 1.3.1 Whole system model The "Whole System" designation refers to the system which was simulated as a single mathematical equation as shown in Figure 1.5. This was a common simulation method for linear systems because for linear systems the effects of individual system components can be combined into a single easy to solve equation. Systems with non linear components can not be reduced in this way. Figure 1.5 Phase Detector , Sample/Hold 1 N Loop Riter Voltage Controlled Oscillator Sampled time block diagram of third order PLL Output The transfer function of Figure 1.5 was derived by taking the t transfonn of the forward path, and using the feed back control equation, Equation 7, to close the loop. Equation 7 ST G(s) = 2...:....:..... k* kvco s s s (s+b) G(z) = (1 i1 ) .g; [ (S+a) k* kvco] s1 (S+b) G(z) T(z) = 1 + G(z) N The frequency response for this model can be derived as follows: 10 PAGE 18 Equation 8 T(s) = G(s) G(s) 1+N -sT .:!...:.!__ kvco T(s) = __ 1_T_s_---=s __ -sT 1 + .:!...:.!__ kvco N T s s s (S+b) [(1 -e -sT)s + (1 -e -sT)a] kq, kvco T(s) = __ .;..___ ____ .;..___ ___ Ts4 + Tbs3 + k.p kvco (1 -e-sT)s + k.p kvco (1 e -sT)a N N S=joo jwk[1-cos(Too)+jsin(Too)] +ka[1-cos(Tw)+jsin(Too)] TUw) ro4T-jro3 bT + j k: [1 cos(Tro) + j sin(Tro)] + (1 cos(Tro) + j sin(Tro)] Using values the simulation diagram (Figure 1 6) can be found. Equation 9 Given : a = 0. 1 6 .28 b = 100 6 .28 T(q) = k = k$ kvco = 36000 T=0.001 N= 1 0.0997 Q-1 0.1728 q -2 + 0.0731 q -3 1 2.433 q-1 + 1.894 q -2 0.460 q-3 The simulation diagram was shown in terms of the delay operator 'q-1 which was the unit time delay "T". 11 PAGE 19 Reference Input Figure 1.6 Discrete time implementation of third order PLL 1.3.2 Simulation in parts model The "Simulated in Parts" designation Wl:!.S used to show results of an equivalent system in which the individual system components were simulated separately, and the simulation results were combined to form an equivalent control system. This ap proach is necessary when some of the system components were non linear. Figure 1.5 was used again as the system diagram, but the !( transforms of the loop filter and VCO were computed separately. Later this will allow the insertion of a nonlinear phase detector, and the computation of only the loop filter parameters without changing the constant VCO parameters. The loop filter can be described as: Equation 10 -sT 1 -e s+a G (s)= ----1 s s 1?. PAGE 20 The voltage controlled oscillator can be described as: Equation 11 (s) = kp kvco """2 S (S+b) G) [ kp kvco J G2(z) = 'r s (s+b) System model: Phase Detector Reference Input tjlr-$, $, E loop Filter Voltage Controlled Oscillator [ 1 -be-bT] q-1 k+ k(aT-1)q 1 1 q 1 1 -(1 abT)q \ e -bT q 2 1 _, Figure 1.7 Third order PLL simulated in parts Given values: Equation 12 Adding values to the to the design variables. Given : a = 0.1 6 .28 b = 100 6.28 k = kljl kvco = 36000 T= 0.001 N=1 Simulation Diagram: 1 1 -q 7.43e-4 q1 13 Output PAGE 21 Output Figure 1.8 Implementation of third order PLL simulated in parts The simulation diagram shown in Figure 1.6 was used as the linear "Reference" system to be compared to the results obtained by simulating the system shown in Figure 1.8. The system shown in Figure 1.8 was first simulated with a linear phase detector to prove equivalence to the system shown in Figure 1.6. The next step was to simulate Figure 1.8 with a nonlinear phase detector and show its performance with various classes of input signals. Finally, the system model shown in Figure 1.8 was simulated in conjunction with least squares parameter estimation to estimate good control parameters for a given class of input signals. 1.3.3 System equivalence Since the system simulated as a "whole system" (Figure 1.6) and the system simulated in parts (Figure 1.8) were based on the continuous time model shown in Figure 1.9, they should have similar characteristics. System similarity was done in the following two steps: Continuous time Vs sampled time modelsFirst, the frequency response of the linear continuous time system shown in Figure 1.3 was compared to the linear sampled time version of the same PLL shown in Figure 1.5. Figure 1.9 shows that the two systems were nearly equivalent at frequencies below 100Hz. Since the -3dB bandwidth was set to 10Hz, this plot shows very good similarity. There were some differences between the two systems at frequencies above 100 Hz. These differences were due to the sampled phase detector used in the system described in Figure 1.5. As one would expect, there was a response null for the sampled time system at 1000 Hz because the sample time 'T' was 0.00 I second. 14 PAGE 22 20 0 --20 (Q "'C -40 CD "'C -60 :::J .:t::: c::: -80 C) as -100 2 -120 -140 Figure 1.9 time PLLs 1 PLL Frequency Response Continuous VS Sampled Time -m-BP.-Q M " . V. -----\ -\ --\ I \ I I f-............ .... --.. -.. --....... --.. --.. ---i .. .. \ -:-\ .. If \ 'A I I \ I i I f -----------------------------------x--x ---10 100 1000 Frequency (Hz) 1--Continuous Time ....,.,,_. Sampled Time Frequency response comparison between continuous time and sampled Figure 1.10 shows the step response of linear continuous time system shown in Figure 1.3 as compared to the step response of the sampled time PLL shown in Figure 1.5. Again the linear continuous time system and the linear sampled time system looked nearly identicaL PAGE 23 ..... Continuous Time PLL Step Response 1.2 1 .9-0.8 0 E 0.6 Q) ..... 0.4 CJ) 0.2 -/ / 0 0 0.02 0.04 0.06 0.08 0.1 Time (Seconds) 1--Continuous Time -'m-Sampled Time Figure 1 .10 Step response comparison between continuous time and discrete time PLLs "Whole system" VS system "simulated in parts" models-The second test for similarity compared the step response of sampled time system shown in Figure 1.6 which was the "whole system" simulation to the same system shown in Figure 1.8 which was "simulated in parts". Figure 1.11 shows the simulation results were similar, but not identicaL Modeling errors associated with breaking the system apart caused the transient response to take slightly different trajectories. Also the steady state response was slightly different. The system simulated in parts" had unity feedback which was absolutely set by the feed back path to the phase detector as shown in Figure 1 8 This forces the DC gain to be exactly 1 0. The system simulated as a "whole system" also has a gain of 1.0, but the gain was numerically set by the accuracy of the system zeros. Model round off errors and small simulation numerical errors will cause a small gain difference. This fact was important later. 16 PAGE 24 +'"" 1.2 1 0. "5 0.8 0 E 0.6 CJ) en o.4 >. en 0.2 0 Sampled Time PLL Step Response 0 .. .. ... .. .. .. .. .. .. .. .. - .. ..... : :...:.. --:: J ....... ...... ..... ... . -... -.. --....... /':-':"" ---............ -. -.. ------.. -..... -.... -.. // ..?./. ,. / ..... ........ -.. -. -.. -.. -......... -...... ...... -.. -............ ---.. ..... ---.-.... -.... -.-... -..... -........ I / I 0.02 0.04 0.06 0.08 0.1 Time (Seconds) 1-Whole System Simulated In Partsl Figure 1.11 Differences in step response between sampled time PLL simulated as a "whole system" and "simulated in parts" Noise responseFigure l.l2 shows the Gaussian noise response of the system simulated as a "whole system" and the system simulated in parts. The trend was similar, but the system "simulated in parts" did not respond to the noise as much as the system simulated as a "whole system". Later, we will see that this effect will cause difficulty in estimating equivalent parameters for the controller. 17 PAGE 25 ..... 0.6 0.4 :::l .80.2 0 0 ..... (/) -0.6 -0.8 0 Sampled Time PLL Noise Response 0.1 0.2 0.3 0.4 0.5 Time (Seconds) 1Whole System Simulated in part4 Figure 1.12 Differences in noise response between a sampled time PLL simulated as a "whole system" and "simulated in parts" 1.3.4 Conclusion The system simulated as a "Whole System" and the nearly equivalent system simulated as a "Simulated in Parts" system had some notable differences. The high frequency response of the sampled data system did not have a high degree of correlation between the two systems. For a real system which was built with specialized components connected together to form the "Simulated in Parts" system, an equivalent "whole system" model may become very complex or not possible. In many cases, complicating the "whole system" to represent the "simulated in parts" system adds complexity to the design process without significant benefit. In general, a design specification should be as simple as possible. PAGE 26 Examples of small differences between different system topologies were fractional time delays, numerical limitations, amplifier offsets, band width limitations, and noise. For the purpose of this thesis it was better that the system simulated as a "whole system" and the system "simulated in parts" have the same trend, but have small differences in transient and noise response because a physical implementation of a system usually will not totally agree with the model. 1.4 Adding non-inear elements The linear phase detector can be converted mathematically to a nonlinear phase detector by making the phase detector output a special function of the input phase difference. The simplest method was to use the mathematical SIGN function which converts a number greater than or equal to 0 to a + 1 in value, and numbers less than 0 were converted to a -1. A zero output for a zero input was not allowed in this conversion. The actual gain of the phase detector was modified by multiplying the + 1 and -1 numerical SIGN output by "k" which established the phase detector's gain. The SIGN method has the characteristic of making the phase detector output a constant positive or negative value for any input difference. This means that its effective gain was variable It was dependent on the input phase error, and in a control system, the loop gain will also be variable. Variable loop gain will cause change in system bandwidth. Hence a SIGN type phase detector will produce a PLL which will respond quickly to small input phase errors due to its high gain for small phase error inputs, and will tend to reject large phase error inputs This system, however, has the tendency to drift or "hunt" when the input phase detection rate approaches the control system bandwidth. We will call this system a non-linear type-1 phase detector. A type-0 phase detector was defined as the common linear phase detector as described in previous sections. Figure 1.13 shows a practical implementation of a non-linear type-1 phase detector. 10 PAGE 27 Input Data 180 degree Signal Splitter pu Type-1 Non-linear Phase Detector Loop Filter Pole@ ro=O Zero@ ClFa Voltage Controlled Oscillator vco 1---t------t Recovered Clock pu Recovered Data Figure 1.13 A practical implementation of a PLL with a non-linear phase detector Other nonlinear phase detectors can also be devised. For example, instead of a constant positive or negative level output level for any phase error, one could devise a system which provides a SIGN magnitude output pulse for every transition. The phase detector output error would then return to zero in a specified time after every phase detection. Similar to the previous SIGN system, this system has variable gain dependent on input phase error, but wou1d not "hunt" as much when the input phase detection rate approaches the control system bandwidth .. This system also has variable gain dependent on the frequency and the magnitude of the input phase error. This system is defined as a non-linear type-2 phase detector. Figure 1.14 shows a practical implementation of a non-linear type-2 phase detector. PAGE 28 Input Data Type-2 Non-linear Phase Detector To Loop Filter Figure 1.14 Improved non linear phase detector for missing pulse applications Figure 1.15 shows a graphical output of various phase detectors stimulated with an early and late data transition. The linear phase detector integrates the phase error causing a proportional control error for all input errors. The type-1 phase detector provides a constant large phase correction for all levels of input phase errors. The type-2 phase detector provided variable duty cycle correction depending on the input data transition rate. Higher order phase detectors (Type-3, etc.) could also implemented by creating an exponential phase detector output pulse for every phase detection. Although a circuit diagram was not shown for this type of detector, it could look similar to the phase detector shown in Figure 1.14 with the one shot replaced with exponential decaying circuit. The perfonnance of this phase detector could be better than Type-1, 2 phase detectors for missing pulse phase detection applications because it has a diminishing effect on following phase samples. During data periods having maximum transitions, the type-3 phase detector would provide maximum correction, but during infrequent data phase detections, that is during the period before the next data transition, this detector would provide diminishing phase correction. ')1 PAGE 29 Early Late Data Transition Data Transition Input Data Transitions Clock (VCO) Output Figure 1.15 Comparison of phase detector output wave forms The type-2 phase detector is probably the best compromise between ease of implementation and performance. The introduction of nonlinear components into a control system causes simulation difficulties because the control system can not be reduced into a simple formula. Instead, the loop components must be simulated separately. This was why a great degree of effort was devoted in the previous section to show similarity between a "whole system" and the system "simulated in parts". The benefit of nonlinear phase detector was primarily to filter unwanted PLL input signals. Other benefits such as an all digital design, and more predictable phase error and slew characteristics were also provided. The disadvantage was increased phase detector noise at low input levels. These features were illustrated in the following sections. ,.,,., PAGE 30 1.4.1 Step response Figure 1.16 shows a simulation of the step response obtained with a nonlinear phase detector. All other parameters were identical to the previous examples which used a linear phase detector. The nonlinear phase detector caused the system to approach its final value in a predictable linear trajectory. This could be an important advantage for control systems which rely on predictable settling times. An example of such a system would be a disk drive head seek problem where the track to track servo would apply a calculated amount of control to achieve the desired control response. To obtain this response, the phase detector gain must be set appropriately. One could use the step response to calibrate the gain, but in this example, the noise response (to be described next) was used. +-' :::J a. +-' :::J 0 E Q) +-' en >Cf) 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 Step Response Input= 1 unit Step ;.,, .. .. .......,.y..,..'"Vt'! ..... Q.>IJC --.. -... --.. } ... -.. -.. ---.. -.... -............................ .. ............ ) .. ............................ I ......... "!" ............................... ; 0.05 0.1 0.15 0.2 0.25 0.3 Time (Seconds) 1Linear Non-Linear Figure 1.16 Comparison between the step response of linear and non-linear PLL PAGE 31 1.4.2 Noise response Figure 1.17 shows the system response when noise with unity variance was applied. The linear system replicates the noise within its bandwidth, but the nonlinear system actually attenuates the noise extremes. This feature was useful in the PLL problem because noise transients can cause a significant output phase error. The operation of the PLL with the non-linear phase detector was dependent on the combination of the loop gain and the expected input phase variation. 0.6 -0.4 :::J 0.. -0.2 :::J 0 E 0 Q) -0.2 -(/) >. en -0.4 -0.6 0 Noise Response Input = 1.0 Gaussian Noise 0.1 0.2 0.3 Time (Seconds) 1Linear Non-Linear 0.4 0.5 Figure 1.17 Comparison between the noise response of linear and non-linear PLL The phase detector gain in this example was adjusted such that the linear and nonlinear example would produce approximately the same noise tracking with unity variance Gaussian noise applied. If the expected normal input variance was smaller then the phase detector gain should be larger to compensate. Similarly, if the input variance was larger the phase detector gain should be less. Actually, this gain need not appear in the phase detector, it can be inserted anywhere in the forward control path. Figure 1.18 easily shows the greater noise rejection of the PLL with a non linear phase detector when a Gaussian noise source with a variance of 4 was applied to the 111 PAGE 32 input. The reason for the rejection was because the magnitude of the limited phase detector error output was the same as the unity variance case. ...... 5. 1 ...... ::::::s 0 0 E Q) ...... -1 Cf) -2 0 Noise Response Input = 4 Gaussian Noise 0.1 0.2 0.3 Time (Seconds) 0.4 1-Linear Non-Linear 0.5 Figure 1.18 Comparison of output noise dependence on input signal amplitude of linear and non-linear PLL. The non-linear PLL reduces noise under large input noise signal conditions The price to be paid for noise rejection was shown in Figure 1.19. For very low input noise levels, the control system actually amplifies the output phase noise because the phase detector can only output a +k or -k error signal. In data detection systems a noise threshold is usually defined which provides a level of diminishing returns on system performance. In other words, if the PLL provides a constant low level of output noise below a predetermined threshold, it will not significantly affect the data recovery performance because there were other error sources which dominate the system performance. 25 PAGE 33 0.3 "5 0.2 .9-0.1 :::J 0 0 -0.1 ...... -0.2 en -0.3 -0.4 0 Noise Response Input= 0.5 *Gaussian Noise 0.1 0.2 0.3 Time (Seconds) 0.4 1Linear .......... Non-Linear I 0.5 Figure 1.19 Comparison of output noise dependence on input signal amplitude of linear and non linear PLL. The non-linear PLL increases output phase noise under low input noise input signal conditions Although this example loop has been optimized for a unity variance Gaussian noise performance other criteria such as colored noise or transient response could be used. When matching lower frequency content input signals is desirable, adding more noise signal power in the lower frequency area will intensify the response in this frequency band. The fixed phase detector gain "k" can be re-adjusted for the best tracking. 26 ...... PAGE 34 1.4.3 Pulse response Figure 1.20 shows the pulse response for the linear and nonlinear PLL. Since the nonlinear phase detector causes constant error correction rate independent of input magnitude, it does not follow the transient as quickly as the linear PLL. The step response for the expected input magnitude was nearly equivalent to Figure 1.11 for both PLLs, but the pulse response for larger than expected inputs has been attenuated in the nonlinear case. This result was expected because of the constant rate of phase change characteristic on the control system with the nonlinear phase detector. 4 "S 3 c. +-' 0 2 1 +-' C/) Pulse Response Input = 5 Unit Pulse -1 0.05 0.1 0.15 0.2 0.25 Time (Seconds) 1Linear -Non-Linea1 0.3 Figure 1.20 Comparison between the pulse response of the linear and non-linear PLL For magnetic tape data detection systems, a run up sequence of transitions without user data can be used to lock the PLL at the beginning of the data stream. Lengthening 27 PAGE 35 this lock up region can give the non-linear PLL adequate time to lock before data is present. Although mechanics variances causing changes in head to tape speed can be obvious sources of transition timing variance, other significant sources such as code sensitivity, media problems and tracking can also exist. The output phase of the nonlinear PLL will not deviate as much as the linear PLL under these conditions, and therefore will more accurately track the data to be recovered. 1.4.4 Bandwidth approximation method Classical control methods can be applied to the PLL with the nonlinear phase detector by considering effect of phase detectors dependence on the magnitude of the input phase error. The result was a family of frequency response curves shown in Figure 1.21. Notice that large input signal were over damped by the PLL non-linear control system, while very small input signals can cause peaked response or have a tendency of instability. The over damping was caused by the constant magnitude output of the phase detector which in the large signal case was smaller in magnitude than in the linear phase detector case. Similarly, the under damped response was caused by an excess phase detector output. This instability was sometimes observed as a "hunting" of the output phase. PAGE 36 Non-Linear PLL Frequency Response Dependence on Input Magnitude 20 .-. 0 m -2o "C ._. -40 -60 -80 ,-1 00 as -120 ::2: -140 .'f. .... . ...... "'x ....... -v, ... __ -.. -----------------------------_ ..... "J .. "?..--.. "7..'(' .... '9": -------.-------------------------------"""( -1 60 -'t-Hi-t+t-++++++t-t-Hi-t+t-++++++t-t+-11-t+t-++++++t+t-H-H-t-t-t-t-t-t' 0.1 1 10 100 1000 Frequency (Hz) -+-Input= 0.01 .... Input = 0.1 -Input = 1 Input = 1 0 '# Input = 100 10000 Figure 1.21 Effect of input signal amplitude on the frequency response of a nonlinear PLL I .4 5 Conclusion Substituting a non-linear phase detector for the linear phase detector found in many PLL has the advantage of filtering "out of bounds" input signals. These erroneous signals can be caused from excessive channel noise bursts or when the reproduce head goes off track and intercepts signals from an adjacent track Sources of such problems were from media damage, mechanical vibration of the drive, splice points of the recorded data, or simply normal tracking variances. A data synchronizer was a good application of this technology because detection Signal to Noise Ratio (SNR) was limited by the head to media interface, and the low level of additional phase noise created as a by product of the nonlinear phase detector was not significant to the data recovery operation as a whole. ?.Q PAGE 37 A low phase noise frequency synthesizer, however, would not be an application of this technology because of the residual low level phase noise produced by the non linear phase detector. The remaining question was how to develop a good control system to be used with the non-linear phase detector operating with various input signals. Linear methods which rely on frequency-phase design methods were no longer applicable when the non linear phase detector was operated over a large range of input phase errors. Transient response methods can be used, but have the disadvantage of using a very restricted class if input signals and therefore may not yield a worst case design. The next section will propose a method which will automatically determine the appropriate control system for a given input signal. 1.5 Parameter estimation of systems with non-linear components The previous section has shown the operation of a PLL after the linear phase detector was replaced with a non-linear phase detector. The loop filter and the VCO models used in the non-linear phase detector case were identical to the models used in the all linear PLL example. The phase detector gain was adjusted to match the expected input phase deviations. The operation of a system with one or more non-linear component can be highly dependent on the input signal characteristics as well as the internal control system characteristics. Experimental methods can be used to "tweak in" the optimal performance with a given signal, but changing component values and re-running simulations, or bench testing with actual components is time consuming, and in general does not produce a worst case design. 1.5.1 Noise cancellation review The adaptive noise cancellation circuit was a starting point for a system which can automatically calculate the control parameters in a non-linear control system. Since the non-linear control system behaves differently with different input signal levels, the adaptive nature of the noise canceling circuit can be used determine control system PAGE 38 parameters which mimic the desired linear control system performance under specified "normal" signal constraints. The parameters of the non-linear control system were then fixed, and the noise reduction and step response characteristics were tested with significant input deviations. Figure 1.22 shows the noise cancellation circuit. Noise Source Input x(n) Noise path Characteristic Noise path estimator Parameter Estimator Figure 1.22 Adaptive noise cancellation block diagram The noise canceling circuit applies the noise source to the fixed noise path characteristic model, and at the same time applies the same noise to an adaptive noise path estimator. In practice, the noise path was some physical realizable transfer function which conducts noise into the desired signal. The adaptive noise path estimator attempts to adjust its filter coefficients to electronically match the physical noise path characteristic. Once matched, y(n) is equivalent to interference signal v0(n), and the noise can be subtracted out in the last summer. Initially, the noise path estimator was not calibrated to the actual parameters of the physical noise path. The parameter estimator accomplishes this by measuring the resulting error and adjusting the noise path estimator parameters to minimize this error. Since the noise applied to both the noise path characteristic block and the noise path estimator was the same signal, it was correlated. The parameter estimator PAGE 39 actually minimizes this correlated noise leaving the signal which was not correlated with the noise. Equation 13 describes the output of the noise path characteristic when the noise signal, x(n) was applied. Equation 13 -1 v (n) = B(z_ ) x(n) 0 A(z ) B(1 ) = b0+ b1Z-1 + +bmz-n A( -1} 1 -1 -n z = + a 1 z + + a1 z Equation 14 describes the output of the noise path estimator when the noise signal, x(n) was applied. Equation 14 s() y(n) = -;-:-:;:x(n) =The output of the adaptive filter A(z ) B(1 ) = b0(n-1}+ b 1(n-1)Z-1 + +bn(n-1}z-'' The transfer function shown in Equation 15 represents the noise path transfer function which in this case was estimated using Recursive Least Squares (RLS) parameter estimation (RLS). Equation 15 s() ,.. _, = The transfer function to be estimated A(z ) The actual mechanics of parameter estimation process can be shown in Equation 16 and Equation 17. These equations were calculated recursively, and will usually converge to reduce the level of the noise. l?. PAGE 40 Equation 16 T e = [b b ... b a .. a l o 0 1 m 1 I e(n-1) b [60(n-1) 61(n-1) 6"(n-m) a1(n-1) a"(n-1) J cj>(n) I:: [x(n) x(n-1) ... x(n-m) -y(n-1) ... -y(n-1)] A T y(n) = e(n-1) cj>(n) Equation 17 A ,.. T e(n) = e(n-1) + p{n) PAGE 41 Colored Noise Input Linear System Model Linear or Non-linear Element Variable Loop Filter A A A 1 B(z ) = b0(n-1)+ b1(n-1)z+ ---+ bn(n-1)z-n Variable Loop Filter .... -1 "" 1 A(z ) = 1 + a,(n-1 )z-+ ---+ an(n-1 )z"" Linear or Non-linear Element Parameter Estimator + Figure 1.23 Noise cancellation circuit modified for automatic parameter estimation of a control system with non linear elements Under certain conditions the gain of the estimated path must be variable and was controlled by the C0 In the PLL example discussed next, the gain of the model was close, but not exactly equal to the gain of the control system to be adapted. This small gain difference can cause a residual output error which makes parameter estimation difficult. 1.5.3 Application to the non-linear PLL example An automated method of determining control system parameters for the non-linear PLL example illustrated should be possible using the noise cancellation process described in the previous section. This method is not limited to the simple lag-lead compensater used previously, but instead considers a general class of loop filters containing multiple poles and zeros. Figure 1.24 shows the general architecture of a system which compared the outputs of a linear and non-linear PLL connected to the same signal source. Using a noise source representing the expected input and least PAGE 42 squares parameter estimation, the parameters of only the loop filter in the non-linear PLL were automatically adjusted by the algorithm to produce an output which was similar, in the lease squared sense, to the linear system model. The linear system model was not part of the final design, but serves as performance standard to which system with the non-linear phase detector was to be adjusted. Colored Noise Input T(q) = Linear System Model 0 .0997 q'-0.1728 q + 0.0731 q"3 1 -2.433 q "' + 1 .894 q"2 -0.460 q "3 Non-linear Variable Loop Filter Voltage Controlled Oscillator Phase Detector Loop Filter Parameter Estimator Figure 1.24 Parameter estimator for the non-linear PLL example Notice that the feed back path was set to simply a gain of 1. This was a practical requirement in the PLL example because physical implementation of this path was digital clock signal. Some sort of digital phase compensater could be implemented in this path, but this would unnecessarily complicate the PLL example, and would not be a practical solution. A gain block was added for numerical reasons. The gain of the linear system model was set by the zeros in that model. The gain of the PLL was set by the unity feed back path. Since the system model was calculated with fixed precision, the gain of the two paths will never be exactly equal. This causes a consistent offset error, and the loop parameter estimator falsely tried to adjust other parameters to reduce this error. The variable loop filter can be simplified by adding a integrator. This helps prevent possible convergence instability since the integrator pole was calculated near the instability zone. PAGE 43 If poles close to the instability zor.::; must be estimated, care must be taken so that these potentially unstable poles do not cause instability in the convergence of the parameters. During every iteration of convergence, one could calculate the stability of the poles, and provide hard limits to prevent oscillations. In the discrete time domain, one could multiply all the poles by a constant less than one to bring the locus of poles back within the unit circle. After parameter convergence, the loop parameters in the non-linear PLL were fixed, the linear model and the loop filter parameter estimator and were removed, and basic PLL was tested with input signals having a large dynamic range. The block diagram shown in Figure 1.24 was further reduced in Figure 1.25. The variable poles of the controller ( 1 +aoq1 + ajq-2 ) were replaced by a single fixed pole at z = 1. This serves as a loop integrator to maintain zero phase error under step input phase conditions. The zeros of the controller (bo + b1q-1 ) were left adjustable by the least squares parameter estimator. The non-linear PLL path gain was adjustable by c0 to provide the small gain adjustment needed to match the gain of the zeros in the linear system model. Colored Noise Input T(q) = Linear System Model 0.0997 q -G 1728 q 2 + 0.0731 q 3 1 2 433 q ' + 1.894 q'2 0.460 q '3 + Non-linear Variable Loop Filter Voltage Controlled Oscillator Phase Detector b0+b1q' 1 1 q [ bT ] Loop Filter Parameter Estimator Figure 1.25 Actual PLL estimator block diagram PAGE 44 A small modification to the parameter estimation algorithm shown in Equation 18 and Equation 19 below was necessary. Equation 18 T 80 = [Co c,Ck bo b1 bm] e(n-1) b [c0(n-1) c1(n-1) c"(n-k) 60(n-1) b1(n-1) 6"(n-m>] T cj>(n) = [u(n) u(n-1) ... u(n-k) x(n) x(n-1) ... x(n-m)] A T y(n) = e(n-1) cj>(n) Equation 19 ,.. ,.... T e(n) = S(n-1) + p(n) cj>(n) [ d(n) S(n-1) (n) cj>(n) p(n-1) p(n)=p(n-1)r p(O)=cj>I, p0>0 1 cj>(n) p(n-1) cj>(n) 1.5.4 Input stimulus Up to this point we have considered only Gaussian or colored random noise sources. This was a good choice if the system to be optimized has an input which has an even distribution of signals which can be represented by a noise source. Other input signal choices representing the actual applied input could produce a more optimized control parameters. One must be careful about choosing narrow band signals as input stimulus because the parameters may not converge properly if only a restricted number of modes were excited. The best solution was to add some noise with the specialized input signal to insure good parameter convergence. Part 2 of this thesis begins to describe the actual input signals to be applied to the example PLL. 1.5.5 Simulation results |